JPS5446418A - Circuit system of picture display unit - Google Patents

Circuit system of picture display unit

Info

Publication number
JPS5446418A
JPS5446418A JP11372577A JP11372577A JPS5446418A JP S5446418 A JPS5446418 A JP S5446418A JP 11372577 A JP11372577 A JP 11372577A JP 11372577 A JP11372577 A JP 11372577A JP S5446418 A JPS5446418 A JP S5446418A
Authority
JP
Japan
Prior art keywords
signal
time
tdo
generated
sampling start
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11372577A
Other languages
Japanese (ja)
Inventor
Nobutoshi Gako
Yasukuni Yamane
Chuji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP11372577A priority Critical patent/JPS5446418A/en
Publication of JPS5446418A publication Critical patent/JPS5446418A/en
Pending legal-status Critical Current

Links

Landscapes

  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To obtain an excellent picture by removing the disturbance at the sampling start time of a video signal generated by the time lag of a CMOS.IC, by generating a sampling pulse which bases upon a horizontal synchronizing signal.
CONSTITUTION: On the basis of horizontal synchronizing signal PH to be inputted to counter C1, signal PM of pulse width tdo is generated at its trailing edge and then mixed with video signal sampling start signal Ps by AND gate 4. Time tdo is set to a value slightly larger than the maximum delay time (td and td) of signal Ps, thereby obtaining signal P's of the same delay time tdo as signal PH. Then, a timing pulse for the A/D conversion of a video signal is generated by signal P's, so that the disturbance of a sampling start time can be eliminated
COPYRIGHT: (C)1979,JPO&Japio
JP11372577A 1977-09-20 1977-09-20 Circuit system of picture display unit Pending JPS5446418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11372577A JPS5446418A (en) 1977-09-20 1977-09-20 Circuit system of picture display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11372577A JPS5446418A (en) 1977-09-20 1977-09-20 Circuit system of picture display unit

Publications (1)

Publication Number Publication Date
JPS5446418A true JPS5446418A (en) 1979-04-12

Family

ID=14619549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11372577A Pending JPS5446418A (en) 1977-09-20 1977-09-20 Circuit system of picture display unit

Country Status (1)

Country Link
JP (1) JPS5446418A (en)

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