JPS54159840A - Micro address generation control circuit - Google Patents

Micro address generation control circuit

Info

Publication number
JPS54159840A
JPS54159840A JP6946878A JP6946878A JPS54159840A JP S54159840 A JPS54159840 A JP S54159840A JP 6946878 A JP6946878 A JP 6946878A JP 6946878 A JP6946878 A JP 6946878A JP S54159840 A JPS54159840 A JP S54159840A
Authority
JP
Japan
Prior art keywords
signal
coincidence
stop
micro address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6946878A
Other languages
Japanese (ja)
Inventor
Yoshiro Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6946878A priority Critical patent/JPS54159840A/en
Publication of JPS54159840A publication Critical patent/JPS54159840A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to stop the operation of a control unit at the just position where the stop of the operation of the control unit is required, by providing a micro address coincidence frequency setting circuit in the micro address control circuit.
CONSTITUTION: Output signal 5 of micro address stop register 1 and output signal 6 of micro address register 2 are subjected to coincidence check by comparator 3; and in case of coincidence, coincidence signal 7 of logical value "1" is generated. Subtraction signal 14 is generated in NAND circuit 10 by coincidence signal 7 and set signal 13, and 1 is subtracted from a coincidence frequency set previously. Then, when output signal 16 of frequency setting circuit 11 becomes the value of constant 17, coincidence signal 18 of comparator 12 becomes logical value "1", and AND between micro address stop effective signal 8 and signal 18 is operated in AND circuit 4, and a unit stop signal is generated to stop the unit.
COPYRIGHT: (C)1979,JPO&Japio
JP6946878A 1978-06-08 1978-06-08 Micro address generation control circuit Pending JPS54159840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6946878A JPS54159840A (en) 1978-06-08 1978-06-08 Micro address generation control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6946878A JPS54159840A (en) 1978-06-08 1978-06-08 Micro address generation control circuit

Publications (1)

Publication Number Publication Date
JPS54159840A true JPS54159840A (en) 1979-12-18

Family

ID=13403520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6946878A Pending JPS54159840A (en) 1978-06-08 1978-06-08 Micro address generation control circuit

Country Status (1)

Country Link
JP (1) JPS54159840A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61249150A (en) * 1985-04-27 1986-11-06 Nec Corp Inspecting device for microprogram control device
JPS61250745A (en) * 1985-04-27 1986-11-07 Nec Corp Inspecting device for microprogram controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61249150A (en) * 1985-04-27 1986-11-06 Nec Corp Inspecting device for microprogram control device
JPS61250745A (en) * 1985-04-27 1986-11-07 Nec Corp Inspecting device for microprogram controller

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