JPS54157049A - Interrupt address determination processing system - Google Patents

Interrupt address determination processing system

Info

Publication number
JPS54157049A
JPS54157049A JP6543078A JP6543078A JPS54157049A JP S54157049 A JPS54157049 A JP S54157049A JP 6543078 A JP6543078 A JP 6543078A JP 6543078 A JP6543078 A JP 6543078A JP S54157049 A JPS54157049 A JP S54157049A
Authority
JP
Japan
Prior art keywords
interrupt
request
priority
register
branching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6543078A
Other languages
Japanese (ja)
Other versions
JPS6143747B2 (en
Inventor
Masahiro Kawakatsu
Shigeyuki Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6543078A priority Critical patent/JPS54157049A/en
Publication of JPS54157049A publication Critical patent/JPS54157049A/en
Publication of JPS6143747B2 publication Critical patent/JPS6143747B2/ja
Granted legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To make it possible to extract effectively a higher-priority interrupt factor by branching for an interrupt factor having the highest priority when a micro processor branches to an interrupt processing routine actually.
CONSTITUTION: Interrupt control circuit 17 which has received an interrupt request from an input/output control register supplies the interrupt request signal to MPU 13. Then, micro processor MPU 13 starts the interrupt processing, and reads contents of interrupt vector address register 22 when branching to the interrupt routine. Meanwhile, if a new interrupt request is supplied to circuit part 17, register 22 stores this request. Then, the interrupt processing is performed for the highest- priority interrupt request at a timing when MPU 13 reads content of register 22, and branching is performed in a prescribed routine. As a result, a higher-priority interrupt request can be extracted.
COPYRIGHT: (C)1979,JPO&Japio
JP6543078A 1978-05-31 1978-05-31 Interrupt address determination processing system Granted JPS54157049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6543078A JPS54157049A (en) 1978-05-31 1978-05-31 Interrupt address determination processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6543078A JPS54157049A (en) 1978-05-31 1978-05-31 Interrupt address determination processing system

Publications (2)

Publication Number Publication Date
JPS54157049A true JPS54157049A (en) 1979-12-11
JPS6143747B2 JPS6143747B2 (en) 1986-09-29

Family

ID=13286862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6543078A Granted JPS54157049A (en) 1978-05-31 1978-05-31 Interrupt address determination processing system

Country Status (1)

Country Link
JP (1) JPS54157049A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940446A (en) * 1972-08-19 1974-04-16
JPS4952944A (en) * 1972-06-27 1974-05-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952944A (en) * 1972-06-27 1974-05-23
JPS4940446A (en) * 1972-08-19 1974-04-16

Also Published As

Publication number Publication date
JPS6143747B2 (en) 1986-09-29

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