JPS54151330A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54151330A
JPS54151330A JP5951678A JP5951678A JPS54151330A JP S54151330 A JPS54151330 A JP S54151330A JP 5951678 A JP5951678 A JP 5951678A JP 5951678 A JP5951678 A JP 5951678A JP S54151330 A JPS54151330 A JP S54151330A
Authority
JP
Japan
Prior art keywords
instruction
circuit
cash
operand
hold circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5951678A
Other languages
Japanese (ja)
Inventor
Yoshihisa Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5951678A priority Critical patent/JPS54151330A/en
Publication of JPS54151330A publication Critical patent/JPS54151330A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To reduce the increase in cash mis-hit as less as possible, by discriminating the operand length, delivering the result to the cash unit, and inhibiting the data write-in to the cash memory.
CONSTITUTION: When the execution of instruction is initiated, the instruction exection circuit 2 reads out the instruction code of the instruction register 1, judges the types of instructions, and delivers the control signal required for each circuit. In case of move-instruction, the first operand address, second operand address, and operand length are respectively stored to the address registers 3, 4 and operand length hold circuit 5 via the buses 14 and 15. The comparison circuit 10 reads out and compares the content of the hold circuits 5 and 7 respectively through the buses 21 and 16. As a result, if the content of the hold circuit 5 is greater than that of the hold circuit 7, "1" is set to the register 11 via the bus 22 to inhibit the write-in to the cash 12.
COPYRIGHT: (C)1979,JPO&Japio
JP5951678A 1978-05-20 1978-05-20 Information processor Pending JPS54151330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5951678A JPS54151330A (en) 1978-05-20 1978-05-20 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5951678A JPS54151330A (en) 1978-05-20 1978-05-20 Information processor

Publications (1)

Publication Number Publication Date
JPS54151330A true JPS54151330A (en) 1979-11-28

Family

ID=13115496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5951678A Pending JPS54151330A (en) 1978-05-20 1978-05-20 Information processor

Country Status (1)

Country Link
JP (1) JPS54151330A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03116231A (en) * 1989-06-20 1991-05-17 Nec Corp Microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03116231A (en) * 1989-06-20 1991-05-17 Nec Corp Microprocessor

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