JPS5414649A - Multi-level output circuit - Google Patents

Multi-level output circuit

Info

Publication number
JPS5414649A
JPS5414649A JP7987277A JP7987277A JPS5414649A JP S5414649 A JPS5414649 A JP S5414649A JP 7987277 A JP7987277 A JP 7987277A JP 7987277 A JP7987277 A JP 7987277A JP S5414649 A JPS5414649 A JP S5414649A
Authority
JP
Japan
Prior art keywords
output circuit
level output
level
circuit
retrenchment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7987277A
Other languages
Japanese (ja)
Inventor
Shuichi Torii
Jiro Sakaguchi
Satoshi Meguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7987277A priority Critical patent/JPS5414649A/en
Publication of JPS5414649A publication Critical patent/JPS5414649A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize the reduction of the number of external parts, retrenchment of power consumption, and improvement of an output level by forming a multi-level output circuit on one semiconductor substrate by means of the semiconductor integrated-circuit technique of normal MISFETs.
JP7987277A 1977-07-06 1977-07-06 Multi-level output circuit Pending JPS5414649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7987277A JPS5414649A (en) 1977-07-06 1977-07-06 Multi-level output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7987277A JPS5414649A (en) 1977-07-06 1977-07-06 Multi-level output circuit

Publications (1)

Publication Number Publication Date
JPS5414649A true JPS5414649A (en) 1979-02-03

Family

ID=13702302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7987277A Pending JPS5414649A (en) 1977-07-06 1977-07-06 Multi-level output circuit

Country Status (1)

Country Link
JP (1) JPS5414649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60156612A (en) * 1983-12-21 1985-08-16 エラン　コ−ポレ−シヨン　ピ−　エル　シ− Absorption-controlled pharmaceutical blend

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60156612A (en) * 1983-12-21 1985-08-16 エラン　コ−ポレ−シヨン　ピ−　エル　シ− Absorption-controlled pharmaceutical blend

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