JPS54134934A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS54134934A
JPS54134934A JP4214578A JP4214578A JPS54134934A JP S54134934 A JPS54134934 A JP S54134934A JP 4214578 A JP4214578 A JP 4214578A JP 4214578 A JP4214578 A JP 4214578A JP S54134934 A JPS54134934 A JP S54134934A
Authority
JP
Japan
Prior art keywords
address
buffer circuit
terminal groups
memory
latched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4214578A
Other languages
Japanese (ja)
Inventor
Kazuo Suganuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4214578A priority Critical patent/JPS54134934A/en
Publication of JPS54134934A publication Critical patent/JPS54134934A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To increase memory capacity without increasing the number of input- output terminals, by multiplexing an addressing signal and an information signal and then by receiving and sending them using the same terminal. CONSTITUTION:In a write cycle, address signals on address bus 300 are supplied to memory 100 via buffer circuit 21 and terminal groups 181 to 18n and latched to address register 12. Next, data bus 400 are written to the address of memory part 11 selected by decoder 13 via bilateral buffer circuit 22, terminal groups 181 to 18n, and buffer circuit 14. In a read cycle, address signal are latched to address register 12 via terminal groups 181 to 18n, and data in the selected address of memory part 11 are read out to data bus 400 by way of buffer circuit 14, terminal groups 181 to 18n, and bilateral buffer circuit 22.
JP4214578A 1978-04-12 1978-04-12 Semiconductor memory device Pending JPS54134934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4214578A JPS54134934A (en) 1978-04-12 1978-04-12 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4214578A JPS54134934A (en) 1978-04-12 1978-04-12 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54134934A true JPS54134934A (en) 1979-10-19

Family

ID=12627763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4214578A Pending JPS54134934A (en) 1978-04-12 1978-04-12 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS54134934A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746391A (en) * 1980-09-05 1982-03-16 Toshiba Corp Semiconductor memory
JPS5877085A (en) * 1981-10-30 1983-05-10 Fujitsu Ltd Semiconductor memory
JPS62282393A (en) * 1986-05-30 1987-12-08 Mitsubishi Electric Corp Ic card
JPS6444588A (en) * 1987-08-12 1989-02-16 Fuji Photo Film Co Ltd Memory cartridge
JPH02177190A (en) * 1988-12-28 1990-07-10 Nec Corp Memory device
US5657288A (en) * 1994-04-13 1997-08-12 Ericsson Inc. Efficient addressing of large memories
JP2006313614A (en) * 2005-05-02 2006-11-16 Samsung Electronics Co Ltd Configuration of memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835736A (en) * 1971-08-31 1973-05-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835736A (en) * 1971-08-31 1973-05-26

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746391A (en) * 1980-09-05 1982-03-16 Toshiba Corp Semiconductor memory
JPS5877085A (en) * 1981-10-30 1983-05-10 Fujitsu Ltd Semiconductor memory
JPS623504B2 (en) * 1981-10-30 1987-01-26 Fujitsu Ltd
JPS62282393A (en) * 1986-05-30 1987-12-08 Mitsubishi Electric Corp Ic card
JPS6444588A (en) * 1987-08-12 1989-02-16 Fuji Photo Film Co Ltd Memory cartridge
JPH02177190A (en) * 1988-12-28 1990-07-10 Nec Corp Memory device
US5657288A (en) * 1994-04-13 1997-08-12 Ericsson Inc. Efficient addressing of large memories
US5680567A (en) * 1994-04-13 1997-10-21 Ericsson Inc. Efficient addressing of large memories
JP2006313614A (en) * 2005-05-02 2006-11-16 Samsung Electronics Co Ltd Configuration of memory device

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