JPS54123842A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS54123842A
JPS54123842A JP3059678A JP3059678A JPS54123842A JP S54123842 A JPS54123842 A JP S54123842A JP 3059678 A JP3059678 A JP 3059678A JP 3059678 A JP3059678 A JP 3059678A JP S54123842 A JPS54123842 A JP S54123842A
Authority
JP
Japan
Prior art keywords
signal
memory
output signal
end output
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3059678A
Other languages
Japanese (ja)
Other versions
JPS579152B2 (en
Inventor
Shigeru Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3059678A priority Critical patent/JPS54123842A/en
Publication of JPS54123842A publication Critical patent/JPS54123842A/en
Publication of JPS579152B2 publication Critical patent/JPS579152B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To speed up the memory element and to make easy the timing design, by outputting the memory operation end signal of the memory element and controlling the control signal or timing signal for the element by this signal. CONSTITUTION:Clock signal is fed to the memory elements 13 to 15 from the generation circuit 19 via the signal lines 16 to 18. The access time end output signal EO1(a type of the operation end output signal) from the elements 13 to 15 is converged with the access time end output signal converging circuit 27 via the signal lines 24 to 26, becomes the memory block access time end output signal BEO1 and is fed to the timing signal generation circuit 23 via the signal line 33 and is used to determine the leading of ''1'' of the latch timing BLT. Further, the memory operation cycle and output signal EO2 from the elements 13 to 15 is converged 31 via the signal lines 28 to 30, becomes the memory block memory operation cycle end output signal BEO2, is fed to the clock signal generation circuit 19, and is used to determine the trailing of the clock signal.
JP3059678A 1978-03-17 1978-03-17 Memory unit Granted JPS54123842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3059678A JPS54123842A (en) 1978-03-17 1978-03-17 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3059678A JPS54123842A (en) 1978-03-17 1978-03-17 Memory unit

Publications (2)

Publication Number Publication Date
JPS54123842A true JPS54123842A (en) 1979-09-26
JPS579152B2 JPS579152B2 (en) 1982-02-19

Family

ID=12308239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3059678A Granted JPS54123842A (en) 1978-03-17 1978-03-17 Memory unit

Country Status (1)

Country Link
JP (1) JPS54123842A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6234252A (en) * 1985-08-06 1987-02-14 ブル・エス・ア− Transfer of data between microprocessor and memory and apparatus for implementation thereof
US6366495B2 (en) * 1995-01-31 2002-04-02 Hitachi, Ltd. Nonvolatile memory device and refreshing method

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6234252A (en) * 1985-08-06 1987-02-14 ブル・エス・ア− Transfer of data between microprocessor and memory and apparatus for implementation thereof
US6366495B2 (en) * 1995-01-31 2002-04-02 Hitachi, Ltd. Nonvolatile memory device and refreshing method
US6459614B1 (en) 1995-01-31 2002-10-01 Hitachi, Ltd. Non-volatile memory device and refreshing method
US6747941B2 (en) 1995-01-31 2004-06-08 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6751119B2 (en) 1995-01-31 2004-06-15 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6751120B2 (en) 1995-01-31 2004-06-15 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6757194B2 (en) 1995-01-31 2004-06-29 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6768672B2 (en) 1995-01-31 2004-07-27 Renesas Technology Corp. Clock Synchronized Non-Volatile Memory Device
US6801452B2 (en) 1995-01-31 2004-10-05 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6804147B2 (en) 1995-01-31 2004-10-12 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6829163B2 (en) 1995-01-31 2004-12-07 Hitachi, Ltd. Clock synchronized nonvolatile memory device
US6847549B2 (en) 1995-01-31 2005-01-25 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6850434B2 (en) 1995-01-31 2005-02-01 Renesas Technology Corp. Clock synchronized nonvolatile memory device
US6868006B2 (en) 1995-01-31 2005-03-15 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6898118B2 (en) 1995-01-31 2005-05-24 Renesas Technology Corp. Clock synchronized non-volatile memory device
US6912156B2 (en) 1995-01-31 2005-06-28 Renesas Technology Corp. Clock synchronized nonvolatile memory device
US6965525B2 (en) 1995-01-31 2005-11-15 Renesas Technology Corp. Clock synchronized nonvolatile memory device
US7161830B2 (en) 1995-01-31 2007-01-09 Renesas Technology Corp. Clock synchronized nonvolatile memory device
US7193894B2 (en) 1995-01-31 2007-03-20 Renesas Technology Corp. Clock synchronized nonvolatile memory device
US7286397B2 (en) 1995-01-31 2007-10-23 Renesas Technology Corporation Clock synchronized nonvolatile memory device
US7324375B2 (en) 1995-01-31 2008-01-29 Solid State Storage Solutions, Llc Multi-bits storage memory
US7327604B2 (en) 1995-01-31 2008-02-05 Renesas Technology Corporation Clock synchronized non-volatile memory device
US7542339B2 (en) 1995-01-31 2009-06-02 Solid State Storage Solutions, Llc Clock synchronized non-volatile memory device

Also Published As

Publication number Publication date
JPS579152B2 (en) 1982-02-19

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