JPS54109769A - Semiconductor device connecting tape - Google Patents

Semiconductor device connecting tape

Info

Publication number
JPS54109769A
JPS54109769A JP1715478A JP1715478A JPS54109769A JP S54109769 A JPS54109769 A JP S54109769A JP 1715478 A JP1715478 A JP 1715478A JP 1715478 A JP1715478 A JP 1715478A JP S54109769 A JPS54109769 A JP S54109769A
Authority
JP
Japan
Prior art keywords
pattern
semiconductor device
wiring
vamp
adhered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1715478A
Other languages
Japanese (ja)
Inventor
Susumu Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1715478A priority Critical patent/JPS54109769A/en
Publication of JPS54109769A publication Critical patent/JPS54109769A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To avoid the short circuit on the side surface of the device when the electrode terminal of the semiconductor device is connected to the wiring through the opening by forming the film carrier by adhering the metal foil wiring on the surface of the flexible tape which is insulating electrically and then coating the electric insulating organic resin containing the fixed opening on the metal foil wiring.
CONSTITUTION: The copper foil is adhered with use of no adhesive on one surface of polyimide film 51, and then lead pattern 52 is formed through the photo etching. Then polyimide resin layer 53 is coated thin on pattern 52 and then hardened by burning, and then fixed opening part 54 is drilled again to layer 53 through the photo etching. After this, the tin plating is applied on exposed pattern 52, and gold vamp 56 of the semiconductor device is pressed there to cause the gold-tin eutectic alloy which is then adhered. In such way, no position shift is caused between vamp 56 and pattern 52, and at the same time the thin copper foil can be used. As a result, pattern 52 becomes minute.
COPYRIGHT: (C)1979,JPO&Japio
JP1715478A 1978-02-16 1978-02-16 Semiconductor device connecting tape Pending JPS54109769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1715478A JPS54109769A (en) 1978-02-16 1978-02-16 Semiconductor device connecting tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1715478A JPS54109769A (en) 1978-02-16 1978-02-16 Semiconductor device connecting tape

Publications (1)

Publication Number Publication Date
JPS54109769A true JPS54109769A (en) 1979-08-28

Family

ID=11936055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1715478A Pending JPS54109769A (en) 1978-02-16 1978-02-16 Semiconductor device connecting tape

Country Status (1)

Country Link
JP (1) JPS54109769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276637A (en) * 1988-03-22 1989-11-07 Bull Sa High density integrated circuit supporter and equipment for selective tin-plating of conductor of the supporter
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process
JPH05235109A (en) * 1992-02-19 1993-09-10 Sumitomo Metal Mining Co Ltd Coplanar-type tape carrier with grounding metal plane and its manufacture

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276637A (en) * 1988-03-22 1989-11-07 Bull Sa High density integrated circuit supporter and equipment for selective tin-plating of conductor of the supporter
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process
JPH05235109A (en) * 1992-02-19 1993-09-10 Sumitomo Metal Mining Co Ltd Coplanar-type tape carrier with grounding metal plane and its manufacture

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