JPS5365072A - Evaulation method of mos type integrated circuit - Google Patents

Evaulation method of mos type integrated circuit

Info

Publication number
JPS5365072A
JPS5365072A JP14091576A JP14091576A JPS5365072A JP S5365072 A JPS5365072 A JP S5365072A JP 14091576 A JP14091576 A JP 14091576A JP 14091576 A JP14091576 A JP 14091576A JP S5365072 A JPS5365072 A JP S5365072A
Authority
JP
Japan
Prior art keywords
evaulation
integrated circuit
mos type
type integrated
elemerts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14091576A
Other languages
Japanese (ja)
Other versions
JPS5343025B2 (en
Inventor
Yoshimitsu Sakakawa
Hiroshi Watanabe
Takeshi Mizusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14091576A priority Critical patent/JPS5365072A/en
Publication of JPS5365072A publication Critical patent/JPS5365072A/en
Publication of JPS5343025B2 publication Critical patent/JPS5343025B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE: To detect the characteristic abnormality of the threshold voltage of elemerts constituting a MOSIC at high sensitivity without depending on circuit formation.
COPYRIGHT: (C)1978,JPO&Japio
JP14091576A 1976-11-24 1976-11-24 Evaulation method of mos type integrated circuit Granted JPS5365072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14091576A JPS5365072A (en) 1976-11-24 1976-11-24 Evaulation method of mos type integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14091576A JPS5365072A (en) 1976-11-24 1976-11-24 Evaulation method of mos type integrated circuit

Publications (2)

Publication Number Publication Date
JPS5365072A true JPS5365072A (en) 1978-06-10
JPS5343025B2 JPS5343025B2 (en) 1978-11-16

Family

ID=15279767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14091576A Granted JPS5365072A (en) 1976-11-24 1976-11-24 Evaulation method of mos type integrated circuit

Country Status (1)

Country Link
JP (1) JPS5365072A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921433A (en) * 1982-07-28 1984-02-03 Ogura Chuck Kk Bend correcting machine
JPH0353767Y2 (en) * 1985-03-22 1991-11-26
JPH066212B2 (en) * 1988-01-12 1994-01-26 株式会社オグラ Bending correction machine

Also Published As

Publication number Publication date
JPS5343025B2 (en) 1978-11-16

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