JPS53118981A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS53118981A
JPS53118981A JP3332977A JP3332977A JPS53118981A JP S53118981 A JPS53118981 A JP S53118981A JP 3332977 A JP3332977 A JP 3332977A JP 3332977 A JP3332977 A JP 3332977A JP S53118981 A JPS53118981 A JP S53118981A
Authority
JP
Japan
Prior art keywords
domain
channel
semiconductor device
drain
less
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3332977A
Other languages
Japanese (ja)
Inventor
Isao Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3332977A priority Critical patent/JPS53118981A/en
Publication of JPS53118981A publication Critical patent/JPS53118981A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To obtain the MOSFET less in the threshold voltage variation, by eliminating the short channel effect, through the provision of groove less than 1μm wide corssing the channel domain and cutting deeper than the bottom surface of the source domain or the drain domain, in the channel domain present between the source domain and the drain domain.
COPYRIGHT: (C)1978,JPO&Japio
JP3332977A 1977-03-28 1977-03-28 Semiconductor device Pending JPS53118981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3332977A JPS53118981A (en) 1977-03-28 1977-03-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3332977A JPS53118981A (en) 1977-03-28 1977-03-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS53118981A true JPS53118981A (en) 1978-10-17

Family

ID=12383506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3332977A Pending JPS53118981A (en) 1977-03-28 1977-03-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS53118981A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
US4874715A (en) * 1987-05-20 1989-10-17 Texas Instruments Incorporated Read only memory with improved channel length control and method of forming
US4979004A (en) * 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5053839A (en) * 1990-01-23 1991-10-01 Texas Instruments Incorporated Floating gate memory cell and device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
US4874715A (en) * 1987-05-20 1989-10-17 Texas Instruments Incorporated Read only memory with improved channel length control and method of forming
US4979004A (en) * 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5053839A (en) * 1990-01-23 1991-10-01 Texas Instruments Incorporated Floating gate memory cell and device

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