JPS5257760A - Phase lock loop circuit - Google Patents

Phase lock loop circuit

Info

Publication number
JPS5257760A
JPS5257760A JP50132978A JP13297875A JPS5257760A JP S5257760 A JPS5257760 A JP S5257760A JP 50132978 A JP50132978 A JP 50132978A JP 13297875 A JP13297875 A JP 13297875A JP S5257760 A JPS5257760 A JP S5257760A
Authority
JP
Japan
Prior art keywords
loop circuit
phase lock
lock loop
phase
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50132978A
Other languages
Japanese (ja)
Other versions
JPS5619769B2 (en
Inventor
Yuzuru Shiozawa
Kunio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50132978A priority Critical patent/JPS5257760A/en
Publication of JPS5257760A publication Critical patent/JPS5257760A/en
Publication of JPS5619769B2 publication Critical patent/JPS5619769B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:The false clock generator circuit is equipped to synchronous control circuit of magnetic memory, and the output and phase of control oscillator are compared. The output pulse is limited to a fixed value and phase margin is increeased. At the same time, reading error of data is reduced.
JP50132978A 1975-11-07 1975-11-07 Phase lock loop circuit Granted JPS5257760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50132978A JPS5257760A (en) 1975-11-07 1975-11-07 Phase lock loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50132978A JPS5257760A (en) 1975-11-07 1975-11-07 Phase lock loop circuit

Publications (2)

Publication Number Publication Date
JPS5257760A true JPS5257760A (en) 1977-05-12
JPS5619769B2 JPS5619769B2 (en) 1981-05-09

Family

ID=15093921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50132978A Granted JPS5257760A (en) 1975-11-07 1975-11-07 Phase lock loop circuit

Country Status (1)

Country Link
JP (1) JPS5257760A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254818A (en) * 1989-03-28 1990-10-15 Nec Corp Pll circuit
US7705645B2 (en) 2005-02-09 2010-04-27 Panasonic Corporation Delay locked loop circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254818A (en) * 1989-03-28 1990-10-15 Nec Corp Pll circuit
US7705645B2 (en) 2005-02-09 2010-04-27 Panasonic Corporation Delay locked loop circuit

Also Published As

Publication number Publication date
JPS5619769B2 (en) 1981-05-09

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