JPS5247684A - Floating gate type transistor - Google Patents
Floating gate type transistorInfo
- Publication number
- JPS5247684A JPS5247684A JP50124058A JP12405875A JPS5247684A JP S5247684 A JPS5247684 A JP S5247684A JP 50124058 A JP50124058 A JP 50124058A JP 12405875 A JP12405875 A JP 12405875A JP S5247684 A JPS5247684 A JP S5247684A
- Authority
- JP
- Japan
- Prior art keywords
- floating gate
- type transistor
- gate type
- obtianing
- channels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To extend floating gate to the outside of channel regions and provide a control gate, thereby obtianing the same characteristics as those when the width and length of channels are changed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50124058A JPS5247684A (en) | 1975-10-14 | 1975-10-14 | Floating gate type transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50124058A JPS5247684A (en) | 1975-10-14 | 1975-10-14 | Floating gate type transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5247684A true JPS5247684A (en) | 1977-04-15 |
JPS5718716B2 JPS5718716B2 (en) | 1982-04-17 |
Family
ID=14875915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50124058A Granted JPS5247684A (en) | 1975-10-14 | 1975-10-14 | Floating gate type transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5247684A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5175210U (en) * | 1974-12-11 | 1976-06-14 | ||
US4997781A (en) * | 1987-11-24 | 1991-03-05 | Texas Instruments Incorporated | Method of making planarized EPROM array |
US5894147A (en) * | 1994-08-30 | 1999-04-13 | National Semiconductor Corporation | Memory transistor having underlapped floating gate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5124186A (en) * | 1974-08-23 | 1976-02-26 | Kogyo Gijutsuin | FUKIHATSUSEI HANDOTAIMEMORIOYOBISONO SEIHO |
-
1975
- 1975-10-14 JP JP50124058A patent/JPS5247684A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5124186A (en) * | 1974-08-23 | 1976-02-26 | Kogyo Gijutsuin | FUKIHATSUSEI HANDOTAIMEMORIOYOBISONO SEIHO |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5175210U (en) * | 1974-12-11 | 1976-06-14 | ||
US4997781A (en) * | 1987-11-24 | 1991-03-05 | Texas Instruments Incorporated | Method of making planarized EPROM array |
US5894147A (en) * | 1994-08-30 | 1999-04-13 | National Semiconductor Corporation | Memory transistor having underlapped floating gate |
Also Published As
Publication number | Publication date |
---|---|
JPS5718716B2 (en) | 1982-04-17 |
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