JPS523381A - Method of treating semiconductor element - Google Patents

Method of treating semiconductor element

Info

Publication number
JPS523381A
JPS523381A JP51073922A JP7392276A JPS523381A JP S523381 A JPS523381 A JP S523381A JP 51073922 A JP51073922 A JP 51073922A JP 7392276 A JP7392276 A JP 7392276A JP S523381 A JPS523381 A JP S523381A
Authority
JP
Japan
Prior art keywords
semiconductor element
treating semiconductor
treating
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP51073922A
Other languages
English (en)
Other versions
JPS613088B2 (ja
Inventor
Maruku Petorofu Pieru
Aasaa Rotsugonii Jiyooji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of JPS523381A publication Critical patent/JPS523381A/ja
Publication of JPS613088B2 publication Critical patent/JPS613088B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31616Deposition of Al2O3
    • H01L21/3162Deposition of Al2O3 on a silicon body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/003Anneal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/06Gettering
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/061Gettering-armorphous layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/097Lattice strain and defects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/928Front and rear surface processing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/938Lattice strain control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
JP51073922A 1975-06-24 1976-06-24 Method of treating semiconductor element Granted JPS523381A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/589,945 US3997368A (en) 1975-06-24 1975-06-24 Elimination of stacking faults in silicon devices: a gettering process

Publications (2)

Publication Number Publication Date
JPS523381A true JPS523381A (en) 1977-01-11
JPS613088B2 JPS613088B2 (ja) 1986-01-30

Family

ID=24360225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51073922A Granted JPS523381A (en) 1975-06-24 1976-06-24 Method of treating semiconductor element

Country Status (11)

Country Link
US (1) US3997368A (ja)
JP (1) JPS523381A (ja)
BE (1) BE843164A (ja)
CA (1) CA1046166A (ja)
DE (1) DE2628087A1 (ja)
ES (1) ES449145A1 (ja)
FR (1) FR2317769A1 (ja)
GB (1) GB1547897A (ja)
IT (1) IT1062377B (ja)
NL (1) NL7606846A (ja)
SE (1) SE414562B (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
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JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
JPS5762538A (en) * 1980-10-01 1982-04-15 Nec Corp Manufacture of semiconductor device
JPS57149256A (en) * 1981-02-17 1982-09-14 Robins Co Inc A H Novel 2-amino-3-(halobenzoyl)-methylphenylacetic acids and antiinflammatory analgesic drug
JPS60157228A (ja) * 1984-01-26 1985-08-17 Fujitsu Ltd 半導体ウエハ−

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JPS5297666A (en) * 1976-02-12 1977-08-16 Hitachi Ltd Production of semiconductor device containing pn junctions
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon
DE2644208C3 (de) * 1976-09-30 1981-04-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung einer einkristallinen Schicht auf einer Unterlage
US4120706A (en) * 1977-09-16 1978-10-17 Harris Corporation Heteroepitaxial deposition of gap on silicon substrates
US4131487A (en) * 1977-10-26 1978-12-26 Western Electric Company, Inc. Gettering semiconductor wafers with a high energy laser beam
US4144099A (en) * 1977-10-31 1979-03-13 International Business Machines Corporation High performance silicon wafer and fabrication process
GB2007430B (en) * 1977-11-03 1982-03-03 Western Electric Co Semicinductor device and fabrication method
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
FR2435818A1 (fr) * 1978-09-08 1980-04-04 Ibm France Procede pour accroitre l'effet de piegeage interne des corps semi-conducteurs
JPS583375B2 (ja) * 1979-01-19 1983-01-21 超エル・エス・アイ技術研究組合 シリコン単結晶ウエハ−の製造方法
US4216489A (en) * 1979-01-22 1980-08-05 Bell Telephone Laboratories, Incorporated MOS Dynamic memory in a diffusion current limited semiconductor structure
US4231809A (en) * 1979-05-25 1980-11-04 Bell Telephone Laboratories, Incorporated Method of removing impurity metals from semiconductor devices
JPS5617011A (en) * 1979-07-23 1981-02-18 Toshiba Corp Semiconductor device and manufacture thereof
US4249962A (en) * 1979-09-11 1981-02-10 Western Electric Company, Inc. Method of removing contaminating impurities from device areas in a semiconductor wafer
US4415373A (en) * 1981-11-17 1983-11-15 Allied Corporation Laser process for gettering defects in semiconductor devices
AT384121B (de) * 1983-03-28 1987-10-12 Shell Austria Verfahren zum gettern von halbleiterbauelementen
JPS60133734A (ja) * 1983-12-21 1985-07-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6124240A (ja) * 1984-07-13 1986-02-01 Toshiba Corp 半導体基板
US4589928A (en) * 1984-08-21 1986-05-20 At&T Bell Laboratories Method of making semiconductor integrated circuits having backside gettered with phosphorus
US4659400A (en) * 1985-06-27 1987-04-21 General Instrument Corp. Method for forming high yield epitaxial wafers
US4830984A (en) * 1987-08-19 1989-05-16 Texas Instruments Incorporated Method for heteroepitaxial growth using tensioning layer on rear substrate surface
DE68925879T2 (de) * 1988-12-21 1996-10-02 At & T Corp Thermisches Oxydierungsverfahren mit verändertem Wachstum für dünne Oxide
US5229306A (en) * 1989-12-27 1993-07-20 Texas Instruments Incorporated Backside gettering method employing a monocrystalline germanium-silicon layer
JPH06103714B2 (ja) * 1990-11-22 1994-12-14 信越半導体株式会社 シリコン単結晶の電気特性検査方法
JP2613498B2 (ja) * 1991-03-15 1997-05-28 信越半導体株式会社 Si単結晶ウエーハの熱処理方法
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JPH0684925A (ja) * 1992-07-17 1994-03-25 Toshiba Corp 半導体基板およびその処理方法
US5562770A (en) * 1994-11-22 1996-10-08 International Business Machines Corporation Semiconductor manufacturing process for low dislocation defects
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JPH10321635A (ja) * 1997-05-16 1998-12-04 Nec Corp 半導体装置及びその製造方法
JP3690563B2 (ja) * 1998-04-28 2005-08-31 富士通株式会社 シリコン基板の評価方法及び半導体装置の製造方法
KR20010041957A (ko) * 1998-06-26 2001-05-25 헨넬리 헬렌 에프 임의인 대 직경의 무결함 실리콘 결정의 성장 공정
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US6358821B1 (en) 2000-07-19 2002-03-19 Chartered Semiconductor Manufacturing Inc. Method of copper transport prevention by a sputtered gettering layer on backside of wafer
US7105050B2 (en) 2000-11-03 2006-09-12 Memc Electronic Materials, Inc. Method for the production of low defect density silicon
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JP2002270516A (ja) * 2001-03-07 2002-09-20 Nec Corp Iii族窒化物半導体の成長方法、iii族窒化物半導体膜およびそれを用いた半導体素子
US7495254B2 (en) * 2005-08-30 2009-02-24 International Business Machines Corporation Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices
US8216362B2 (en) 2006-05-19 2012-07-10 Memc Electronic Materials, Inc. Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during CZ growth
EP2582669B1 (de) 2010-06-15 2015-10-07 Basf Se Verfahren zur herstellung eines zyklischen tertiären methylamins
US8637668B2 (en) 2010-06-15 2014-01-28 Basf Se Process for preparing a cyclic tertiary methylamine
US8933223B2 (en) 2010-10-14 2015-01-13 Basf Se Process for preparing a cyclic tertiary amine
EP2627644B1 (de) 2010-10-14 2014-12-10 Basf Se Verfahren zur herstellung eines zyklischen tertiären amins
US8436169B2 (en) 2010-10-29 2013-05-07 Basf Se Process for preparing 1,4-bishydroxyethylpiperazine
EP2632909B1 (de) 2010-10-29 2015-02-25 Basf Se Verfahren zur herstellung von 1,4-bishydroxyethyl-piperazin
US8884015B2 (en) 2012-06-01 2014-11-11 Basf Se Process for the preparation of a mono-N-alkypiperazine
ES2579088T3 (es) 2012-06-01 2016-08-04 Basf Se Proceso para preparar una mono-n-alquil-piperazina
US8981093B2 (en) 2012-06-06 2015-03-17 Basf Se Process for preparing piperazine
DE102013204839A1 (de) 2013-03-19 2014-09-25 Siltronic Ag Verfahren zum Polieren einer Scheibe aus Halbleitermaterial
WO2018063350A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Methods and apparatus for gettering impurities in semiconductors
RU2680606C1 (ru) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления полупроводниковых структур
JP7476039B2 (ja) 2020-09-02 2024-04-30 キオクシア株式会社 半導体装置の検査装置、及び、半導体装置の検査方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100961A (ja) * 1973-01-30 1974-09-24
JPS5028753A (ja) * 1973-07-13 1975-03-24

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US3418181A (en) * 1965-10-20 1968-12-24 Motorola Inc Method of forming a semiconductor by masking and diffusing
US3494809A (en) * 1967-06-05 1970-02-10 Honeywell Inc Semiconductor processing
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US3579815A (en) * 1969-08-20 1971-05-25 Gen Electric Process for wafer fabrication of high blocking voltage silicon elements
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JPS49100961A (ja) * 1973-01-30 1974-09-24
JPS5028753A (ja) * 1973-07-13 1975-03-24

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
JPS5762538A (en) * 1980-10-01 1982-04-15 Nec Corp Manufacture of semiconductor device
JPS613090B2 (ja) * 1980-10-01 1986-01-30 Nippon Electric Co
JPS57149256A (en) * 1981-02-17 1982-09-14 Robins Co Inc A H Novel 2-amino-3-(halobenzoyl)-methylphenylacetic acids and antiinflammatory analgesic drug
JPH0365338B2 (ja) * 1981-02-17 1991-10-11
JPS60157228A (ja) * 1984-01-26 1985-08-17 Fujitsu Ltd 半導体ウエハ−

Also Published As

Publication number Publication date
JPS613088B2 (ja) 1986-01-30
CA1046166A (en) 1979-01-09
SE7606869L (sv) 1976-12-25
FR2317769B1 (ja) 1980-10-24
DE2628087A1 (de) 1977-01-20
SE414562B (sv) 1980-08-04
DE2628087C2 (ja) 1988-08-04
FR2317769A1 (fr) 1977-02-04
BE843164A (fr) 1976-10-18
IT1062377B (it) 1984-10-10
NL7606846A (nl) 1976-12-28
US3997368A (en) 1976-12-14
ES449145A1 (es) 1977-12-01
GB1547897A (en) 1979-06-27

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