JPS5211769A - Method of adhering semiconductor proper and semiconductor holder - Google Patents

Method of adhering semiconductor proper and semiconductor holder

Info

Publication number
JPS5211769A
JPS5211769A JP50087715A JP8771575A JPS5211769A JP S5211769 A JPS5211769 A JP S5211769A JP 50087715 A JP50087715 A JP 50087715A JP 8771575 A JP8771575 A JP 8771575A JP S5211769 A JPS5211769 A JP S5211769A
Authority
JP
Japan
Prior art keywords
semiconductor
proper
holder
adhering
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50087715A
Other languages
Japanese (ja)
Inventor
Fumio Kubota
Kazuo Nishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP50087715A priority Critical patent/JPS5211769A/en
Publication of JPS5211769A publication Critical patent/JPS5211769A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To prevent damage due to soldering heat fatigue and poor heat radiation by soldering the pellet to the header by the capilliary phenomenon.
COPYRIGHT: (C)1977,JPO&Japio
JP50087715A 1975-07-17 1975-07-17 Method of adhering semiconductor proper and semiconductor holder Pending JPS5211769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50087715A JPS5211769A (en) 1975-07-17 1975-07-17 Method of adhering semiconductor proper and semiconductor holder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50087715A JPS5211769A (en) 1975-07-17 1975-07-17 Method of adhering semiconductor proper and semiconductor holder

Publications (1)

Publication Number Publication Date
JPS5211769A true JPS5211769A (en) 1977-01-28

Family

ID=13922589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50087715A Pending JPS5211769A (en) 1975-07-17 1975-07-17 Method of adhering semiconductor proper and semiconductor holder

Country Status (1)

Country Link
JP (1) JPS5211769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727727A (en) * 1995-02-02 1998-03-17 Vlt Corporation Flowing solder in a gap
US5808358A (en) * 1994-11-10 1998-09-15 Vlt Corporation Packaging electrical circuits
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808358A (en) * 1994-11-10 1998-09-15 Vlt Corporation Packaging electrical circuits
US5906310A (en) * 1994-11-10 1999-05-25 Vlt Corporation Packaging electrical circuits
US6096981A (en) * 1994-11-10 2000-08-01 Vlt Corporation Packaging electrical circuits
US6119923A (en) * 1994-11-10 2000-09-19 Vlt Corporation Packaging electrical circuits
US6159772A (en) * 1994-11-10 2000-12-12 Vlt Corporation Packaging electrical circuits
US5727727A (en) * 1995-02-02 1998-03-17 Vlt Corporation Flowing solder in a gap
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board

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