JPS5056161A - - Google Patents
Info
- Publication number
- JPS5056161A JPS5056161A JP10301873A JP10301873A JPS5056161A JP S5056161 A JPS5056161 A JP S5056161A JP 10301873 A JP10301873 A JP 10301873A JP 10301873 A JP10301873 A JP 10301873A JP S5056161 A JPS5056161 A JP S5056161A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10301873A JPS5056161A (ja) | 1973-09-14 | 1973-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10301873A JPS5056161A (ja) | 1973-09-14 | 1973-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5056161A true JPS5056161A (ja) | 1975-05-16 |
Family
ID=14342894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10301873A Pending JPS5056161A (ja) | 1973-09-14 | 1973-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5056161A (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5390469U (ja) * | 1976-12-24 | 1978-07-24 | ||
| WO2008114374A1 (ja) * | 2007-03-19 | 2008-09-25 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
-
1973
- 1973-09-14 JP JP10301873A patent/JPS5056161A/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5390469U (ja) * | 1976-12-24 | 1978-07-24 | ||
| WO2008114374A1 (ja) * | 2007-03-19 | 2008-09-25 | Renesas Technology Corp. | 半導体装置及びその製造方法 |