JPH1187264A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH1187264A JPH1187264A JP24684497A JP24684497A JPH1187264A JP H1187264 A JPH1187264 A JP H1187264A JP 24684497 A JP24684497 A JP 24684497A JP 24684497 A JP24684497 A JP 24684497A JP H1187264 A JPH1187264 A JP H1187264A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tin
- plug
- via hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に層間配線のためのタングステン（Ｗ）プラグを有す
る半導体装置とその製造方法に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a tungsten (W) plug for interlayer wiring and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】集積回路などの半導体装置の層間配線の
ためにプラグが用いられる。図１にこれまで一般に用い
られている層間配線構造を示す。半導体基板または下層
配線１の上に、例えばＳｉＯ2 などの絶縁膜２を形成
し、絶縁膜２の所望の位置には層間配線を形成するため
のビアホール３が設けられている。ビアホールの内面お
よび絶縁膜の表面を覆って、Ｔｉ膜４およびＴｉＮ膜５
をスパッタリングによって成膜し、ＣＶＤ法によってビ
アホールを埋め込んでＷプラグ６を形成する。Ｔｉ膜４
は絶縁膜および下地の半導体または下層配線との密着性
を高めるため、ＴｉＮ膜４はその上に形成されるＷとの
密着性を高めるために用いられる。さらに、Ｗプラグ６
およびＴｉＮ膜５の上にＡｌ配線７を施し、その上にＴ
ｉＮ保護膜８を形成する。2. Description of the Related Art Plugs are used for interlayer wiring of semiconductor devices such as integrated circuits. FIG. 1 shows an interlayer wiring structure generally used so far. An insulating film 2 of, for example, SiO 2 is formed on the semiconductor substrate or the lower wiring 1, and a via hole 3 for forming an interlayer wiring is provided at a desired position of the insulating film 2. The Ti film 4 and the TiN film 5 cover the inner surface of the via hole and the surface of the insulating film.
Is formed by sputtering, and via holes are buried by CVD to form W plugs 6. Ti film 4
The TiN film 4 is used to increase the adhesion to the insulating film and the underlying semiconductor or the lower wiring, and the TiN film 4 is used to increase the adhesion to W formed thereon. Furthermore, W plug 6
Al wiring 7 is provided on the TiN film 5 and TiN film 5, and T
An iN protective film 8 is formed.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のプラグ
形成法には次のような問題がある。図２および図３にそ
の問題を説明するための模式図を示す。Ｔｉ膜４は一般
的にはスパッタリングで形成されその厚さは３００Å程
度であり、絶縁膜との密着性が良く、絶縁膜の角部を元
の形状を保ったままでよく被覆する。しかし、スパッタ
リングによるＴｉＮ膜５は平均的には１０００Å程度の
厚さであるが、図２に示すように、ビアホールの底面の
角部では薄くなりやすく、ビアホール上部の角部では厚
くなりやすい。そのために、ＴｉＮ膜５の特に上部の角
部にはビアホール下部へ向かう応力と絶縁膜の表面方向
に向かう応力とが働き、その結果、ＴｉＮ膜５のビアホ
ール上部の角部に位置する部分は多孔質になる。ＷＦ6
を原料ガスとしてＣＶＤ法によってビアホール内をＷで
埋め込んでプラグを形成するとき、この多孔質のＴｉＮ
はＷＦ6 のアタッキングを受ける。すなわち、ＴｉＮ膜
５の上部の角部は多孔質のためにＷＦ6 ガスが浸透し
て、下層のＴｉ膜４と反応し、その結果、次式に示すよ
うにＴｉＦ４が生成する。The above-mentioned conventional plug forming method has the following problems. 2 and 3 are schematic diagrams for explaining the problem. The Ti film 4 is generally formed by sputtering, has a thickness of about 300 °, has good adhesion to the insulating film, and well covers the corners of the insulating film while maintaining the original shape. However, the TiN film 5 formed by sputtering has an average thickness of about 1000 °, but tends to be thinner at the bottom corner of the via hole and thicker at the upper corner of the via hole as shown in FIG. Therefore, a stress directed toward the lower portion of the via hole and a stress directed toward the surface of the insulating film act on the upper corner portion of the TiN film 5 in particular. Be quality. WF 6
When the plug is formed by filling the via hole with W by the CVD method using the TiN as a source gas, the porous TiN
Gets attacked by WF 6 . That is, the upper corner portion of the TiN film 5 is porous, so that the WF 6 gas permeates and reacts with the lower Ti film 4, and as a result, TiF4 is generated as shown in the following equation.
【０００４】[0004]
【化１】 ２ＷＦ6 ＋３Ｔｉ→３ＴｉＦ4 ＋２Ｗ （１） ＴｉＮとＴｉＦ4 は密着性が良くないので、図３に示す
ように、ビアホールの上部角部においてＴｉＮ膜５の剥
離が生じる。従って、Ｗプラグの形成、Ａｌ配線層の形
成その他の工程に障害が生じ、良好な層間配線を施すこ
とが困難になる。Embedded image 2WF 6 + 3Ti → 3TiF 4 + 2W (1) Since the adhesion between TiN and TiF 4 is not good, peeling of the TiN film 5 occurs at the upper corner of the via hole as shown in FIG. Therefore, an obstacle occurs in the formation of the W plug, the formation of the Al wiring layer, and other steps, and it becomes difficult to provide a good interlayer wiring.
【０００５】この問題を解決するために、従来はＴｉＮ
膜を厚く成膜したり、あるいはＴｉＮ膜中の未反応のＴ
ｉを再窒化させて、ＷＦ6 との反応を防いだりしていた
が、充分な効果を上げることができなかった。In order to solve this problem, conventionally, TiN
Thick film is formed, or unreacted T in TiN film
Although i was renitrided to prevent the reaction with WF 6 , a sufficient effect could not be obtained.
【０００６】本発明は、このような問題を解決し、Ｗプ
ラグを含む良好な層間配線構造を有する半導体装置およ
びそのための製造方法を提供することを目的とする。An object of the present invention is to provide a semiconductor device having an excellent interlayer wiring structure including a W plug and a manufacturing method therefor, which solves such a problem.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体装置は、絶縁膜に設けられたビ
アホール内にプラグが形成されている半導体装置におい
て、前記プラグが、底面および壁面がＴｉ、ＴｉＮ、Ａ
ｌおよびＴｉＮによって順次覆われたビアホールを埋め
込んだＷからなることを特徴とする。In order to achieve the above object, a semiconductor device according to the present invention has a structure in which a plug is formed in a via hole provided in an insulating film. Is Ti, TiN, A
It is characterized by comprising W in which via holes sequentially covered with 1 and TiN are buried.
【０００８】本発明による半導体装置の製造方法は、絶
縁膜に設けられたビアホール内にプラグを形成する工程
を有する半導体装置の製造方法において、前記ビアホー
ルの底面および壁面にＴｉ、ＴｉＮ、ＡｌおよびＴｉＮ
を順次成膜し、さらに前記ビアホールを埋め込んでＷを
成膜してプラグを形成する工程を有することを特徴とす
る。According to a method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device having a step of forming a plug in a via hole provided in an insulating film.
Are sequentially formed, and the plug is formed by forming W by filling the via hole.
【０００９】[0009]
【発明の実施の形態】本発明においては、ビアホール内
にＷプラグを形成する際に、まず、Ｔｉ膜およびＴｉＮ
膜を形成し、さらにＡｌ膜およびＴｉＮ膜を形成した
後、Ｗプラグを形成する。形成されたＡｌ膜はビアホー
ルの上部の角部の形状を緩やかにするので、その上に形
成されたＴｉＮ膜の角部には応力がかかり難く、そのた
めにＴｉＮ膜は多孔質にはならない。その結果、ＷＦ6
ガスを用いたＣＶＤ法によってＷプラグを形成するとき
にＴｉＮ膜がＷＦ6 ガスによってアタッキングを受けて
剥離することがないので、良好な層間配線を実現するこ
とができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, when forming a W plug in a via hole, first, a Ti film and a TiN
After forming a film and further forming an Al film and a TiN film, a W plug is formed. Since the formed Al film moderates the shape of the upper corner of the via hole, stress is less likely to be applied to the corner of the TiN film formed thereon, so that the TiN film does not become porous. As a result, WF 6
When the W plug is formed by the CVD method using gas, the TiN film is not attacked by the WF 6 gas and does not peel off, so that good interlayer wiring can be realized.
【００１０】[0010]
【実施例】図４を参照して本発明の実施例を説明する。
トランジスタ、ダイオードなどの素子構造が形成されて
いる半導体基板１の表面に、絶縁膜として厚さ１．０μ
ｍのＳｉＯ2 膜２を形成した。絶縁膜２の所定の位置に
一辺が０．６μｍのビアホール３を形成した。次いで、
スパッタリングによって、厚さ３００ÅのＴｉ膜４、厚
さ１０００ÅのＴｉＮ膜５を順次形成した。さらに、Ｔ
ｉＮ膜５の上に平均厚さ４０００ÅのＡｌ膜１１を形成
した。Ａｌ膜１１の形状は図４に示すように、角部にお
いて緩やかであった。ついで、Ｗとの密着性を高めるた
めに、Ａｌ膜１１の上にスパッタリングによって厚さ３
００ÅのＴｉＮ膜１２を成膜した。ＴｉＮ膜１２はＡｌ
膜１１の表面形状を忠実に再現した。次にＷＦ6 を原料
ガスとして、ＣＶＤ法によってビアホール内をＷで埋め
込むとともに、ＴｉＮ膜１２上にもＷを成膜した。次に
ビアホール部分以外のＷをエッチング除去してＷプラグ
６を作成した。最後に所定の配線形状にエッチングして
層間配線構造を作成した。ＴｉＮ膜１２には剥離を生じ
ることなく、良好な層間配線が得られた。An embodiment of the present invention will be described with reference to FIG.
A 1.0 μm thick insulating film is formed on the surface of the semiconductor substrate 1 on which element structures such as transistors and diodes are formed.
m of SiO 2 film 2 was formed. Via holes 3 each having a side of 0.6 μm were formed at predetermined positions of the insulating film 2. Then
A 300 .mu.m thick Ti film 4 and a 1000 .mu.m thick TiN film 5 were sequentially formed by sputtering. Furthermore, T
An Al film 11 having an average thickness of 4000 ° was formed on the iN film 5. As shown in FIG. 4, the shape of the Al film 11 was gentle at the corners. Then, in order to enhance the adhesion to W, a thickness of 3 is formed on the Al film 11 by sputtering.
A TiN film 12 of 00 ° was formed. TiN film 12 is made of Al
The surface shape of the film 11 was faithfully reproduced. Next, using WF 6 as a source gas, the via holes were filled with W by CVD, and W was formed on the TiN film 12. Next, W other than the via hole was removed by etching to form a W plug 6. Finally, etching was performed into a predetermined wiring shape to form an interlayer wiring structure. A good interlayer wiring was obtained on the TiN film 12 without peeling.
【００１１】下層配線、例えばＡｌ配線と上層配線との
層間配線をＷプラグを用いて行う場合も、同様の工程で
良好な層間配線構造を得ることができる。When a lower wiring, for example, an interlayer wiring between an Al wiring and an upper wiring is formed by using a W plug, a good interlayer wiring structure can be obtained by the same process.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
Ｗプラグの下地のＴｉＮ膜に剥離を生じることがない。
従って、良好なＷプラグおよび良好な層間配線構造を有
する半導体装置を実現することができる。As described above, according to the present invention,
There is no separation of the TiN film underlying the W plug.
Therefore, a semiconductor device having a good W plug and a good interlayer wiring structure can be realized.
【図１】従来の層間配線構造を示す断面図である。FIG. 1 is a cross-sectional view showing a conventional interlayer wiring structure.
【図２】従来の問題を説明するための模式図である。FIG. 2 is a schematic diagram for explaining a conventional problem.
【図３】従来の問題を説明するための模式図である。FIG. 3 is a schematic diagram for explaining a conventional problem.
【図４】本発明の層間配線構造を示す断面図である。FIG. 4 is a sectional view showing an interlayer wiring structure of the present invention.
１ 半導体基板または下層配線 ２ 絶縁膜 ３ ビアホール ４ Ｔｉ膜 ５ ＴｉＮ膜 ６ Ｗプラグ ７ Ａｌ配線 ８ ＴｉＮ保護膜 １１ Ａｌ膜 １２ ＴｉＮ膜 Reference Signs List 1 semiconductor substrate or lower wiring 2 insulating film 3 via hole 4 Ti film 5 TiN film 6 W plug 7 Al wiring 8 TiN protective film 11 Al film 12 TiN film
Claims (2)
グが形成されている半導体装置において、前記プラグ
が、底面および壁面がＴｉ、ＴｉＮ、ＡｌおよびＴｉＮ
によって順次覆われたビアホールを埋め込んだＷからな
ることを特徴とする半導体装置。1. A semiconductor device in which a plug is formed in a via hole provided in an insulating film, wherein the plug has a bottom surface and a wall surface formed of Ti, TiN, Al and TiN.
A semiconductor device comprising W in which via holes sequentially covered by W are buried.
グを形成する工程を有する半導体装置の製造方法におい
て、前記ビアホールの底面および壁面にＴｉ、ＴｉＮ、
ＡｌおよびＴｉＮを順次成膜し、さらに前記ビアホール
を埋め込んでＷを成膜してプラグを形成する工程を有す
ることを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device, comprising the step of forming a plug in a via hole provided in an insulating film, wherein Ti, TiN,
A method of manufacturing a semiconductor device, comprising the steps of sequentially forming Al and TiN, forming a W by filling the via hole, and forming a plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24684497A JPH1187264A (en) | 1997-09-11 | 1997-09-11 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24684497A JPH1187264A (en) | 1997-09-11 | 1997-09-11 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187264A true JPH1187264A (en) | 1999-03-30 |
Family
ID=17154556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24684497A Withdrawn JPH1187264A (en) | 1997-09-11 | 1997-09-11 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187264A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001006547A1 (en) * | 1999-07-14 | 2001-01-25 | Lucent Technologies Inc. | A thin film resistor device and a method of manufacture therefor |
| US6703666B1 (en) | 1999-07-14 | 2004-03-09 | Agere Systems Inc. | Thin film resistor device and a method of manufacture therefor |
-
1997
- 1997-09-11 JP JP24684497A patent/JPH1187264A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001006547A1 (en) * | 1999-07-14 | 2001-01-25 | Lucent Technologies Inc. | A thin film resistor device and a method of manufacture therefor |
| US6703666B1 (en) | 1999-07-14 | 2004-03-09 | Agere Systems Inc. | Thin film resistor device and a method of manufacture therefor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20041207 |