JPH1174271A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1174271A
JPH1174271A JP9234455A JP23445597A JPH1174271A JP H1174271 A JPH1174271 A JP H1174271A JP 9234455 A JP9234455 A JP 9234455A JP 23445597 A JP23445597 A JP 23445597A JP H1174271 A JPH1174271 A JP H1174271A
Authority
JP
Japan
Prior art keywords
bonding pad
via hole
width
electrode portion
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9234455A
Other languages
Japanese (ja)
Inventor
Yoshinari Ichihashi
由成 市橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9234455A priority Critical patent/JPH1174271A/en
Publication of JPH1174271A publication Critical patent/JPH1174271A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent etching failures and nonuniform etching due to loading effects by suppressing the generation of loading effects on a layer between a bonding pad and an electrode. SOLUTION: A via hole 1 for connecting a bonding pad 59 and an electrode 58 is formed in a slit-shape having a width of 1 μm, and the size of the via hole 1 approaches close to the size of the other via hole 60 on a same layer. Therefore, the generation of loading effects can be suppressed, and etching failures and nonuniform etching due to the loading effects are prevented. As a result, an satisfactory multilayered interconnection structure can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ボンディングパッ
ドを備えた半導体装置に関する。The present invention relates to a semiconductor device having a bonding pad.

【０００２】[0002]

【従来の技術】セラミック又は樹脂によって形成された
パッケージに半導体チップを搭載する際には、半導体チ
ップに、パッケージの外に出ているリード端子を電気的
に接続するためのボンディングパッドが設けられてい
る。図８に従来の半導体チップ５１の概略断面図を示
す。2. Description of the Related Art When a semiconductor chip is mounted on a package formed of ceramic or resin, bonding pads are provided on the semiconductor chip for electrically connecting lead terminals outside the package. I have. FIG. 8 is a schematic sectional view of a conventional semiconductor chip 51.

【０００３】半導体チップ５１は、半導体Ｓｉ基板５２
に形成された図示しないＭＯＳデバイス等の素子を有
し、更にその上に多層配線構造を有している。多層配線
構造は、層間絶縁膜５３、５４、５５、配線層５６、５
７、電極部５８、ボンディングパッド５９、ビアホール
（コンタクトホール）６０、６１、ビアホール埋め込み
プラグ６２、６３、パッシベーション膜６４から構成さ
れている。A semiconductor chip 51 includes a semiconductor Si substrate 52
And a device such as a MOS device (not shown) formed thereon, and a multilayer wiring structure thereon. The multilayer wiring structure includes interlayer insulating films 53, 54, 55, wiring layers 56, 5
7, an electrode portion 58, a bonding pad 59, via holes (contact holes) 60 and 61, via hole embedded plugs 62 and 63, and a passivation film 64.

【０００４】第１の層間絶縁膜５３は、例えばシリコン
酸化膜からなり、半導体基板５２及びＭＯＳデバイス等
の素子の上に形成されている。第１の配線層５６及び電
極部５８は層間絶縁膜５３の上に形成されている。電極
部５８は、ボンディングパッド５９とほぼ等しい大きさ
で、第１の配線層５６と同一材料により同一工程にて形
成されている。[0004] The first interlayer insulating film 53 is made of, for example, a silicon oxide film and is formed on the semiconductor substrate 52 and elements such as MOS devices. The first wiring layer 56 and the electrode unit 58 are formed on the interlayer insulating film 53. The electrode portion 58 has substantially the same size as the bonding pad 59, and is formed of the same material as the first wiring layer 56 in the same step.

【０００５】第２の層間絶縁膜５４、５５は、それぞれ
異なる条件で形成したシリコン酸化膜からなり、配線層
５６及び電極部５８の上に形成されている。第２の配線
層５７及びボンディングパッド５９は層間絶縁層５５の
上に形成されている。ボンディングパッド５９は第２の
配線層５７と同一材料により同一工程にて形成されてい
る。The second interlayer insulating films 54 and 55 are formed of silicon oxide films formed under different conditions, respectively, and are formed on the wiring layer 56 and the electrode portion 58. The second wiring layer 57 and the bonding pad 59 are formed on the interlayer insulating layer 55. The bonding pad 59 is formed of the same material as the second wiring layer 57 in the same step.

【０００６】ビアホール６０は層間絶縁膜５４、５５に
形成され、このビアホール６０内に形成されたビアホー
ル埋め込みプラグ６２を介して第１の配線層５６と第２
の配線層５７とが電気的に接続されている。ビアホール
６１はビアホール６０よりもはるかに径が大きく、ビア
ホール６０と同様層間絶縁膜５４、５５に形成されてい
る。そして、このビアホール６１を介して（一部はビア
ホール６１内に形成されたビアホール埋め込みプラグ６
３を介して）、電極部５８とボンディングパッド５９と
が電気的に接続されている。A via hole 60 is formed in the interlayer insulating films 54 and 55, and a first wiring layer 56 and a second wiring layer 56 are formed through a via hole buried plug 62 formed in the via hole 60.
Is electrically connected to the wiring layer 57. The via hole 61 is much larger in diameter than the via hole 60 and is formed in the interlayer insulating films 54 and 55 similarly to the via hole 60. Then, via the via hole 61 (partially the via hole buried plug 6 formed in the via hole 61).
3), the electrode portion 58 and the bonding pad 59 are electrically connected.

【０００７】パッシベーション膜６４は、ボンディング
パッド５９の表面中央部を除く半導体チップ５１の表面
（層間絶縁膜５５の上）に形成されている。パッシベー
ション膜６４から露出したボンディングパッド５９の表
面中央部には、ボンディングワイヤ６５が熱圧着されて
いる。このボンディングワイヤ６５は、ボンディングパ
ッド５９と図示しないパッケージのリード端子とを電気
的に接続する。The passivation film 64 is formed on the surface of the semiconductor chip 51 (on the interlayer insulating film 55) except for the center of the surface of the bonding pad 59. At the center of the surface of the bonding pad 59 exposed from the passivation film 64, a bonding wire 65 is thermocompression-bonded. The bonding wire 65 electrically connects the bonding pad 59 to a lead terminal of a package (not shown).

【０００８】[0008]

【発明が解決しようとする課題】上述したように、電極
部５８とボンディングパッド５９とは、大きなコンタク
ト部を形成して電気抵抗の低い接続状態を得るために、
ほぼ同じ大きさに形成されており、両者を接続するため
のビアホール６１も同層のビアホール６０に比べて非常
に径が大きい。As described above, the electrode portion 58 and the bonding pad 59 are connected to each other in order to form a large contact portion and obtain a connection state with low electric resistance.
The via holes 61 for connecting the two are substantially the same in size as the via holes 60 in the same layer.

【０００９】この結果、ビアホール６０とビアホール６
１とをエッチングする際、ローディング効果（被エッチ
ング面積が増加すると、ドライエッチング時のラジカル
の消費量が増加し、エッチング速度が遅くなる現象）に
よって、両者にエッチング速度の差が生じ、ビアホール
６１のエッチングが終了した時点でエッチングを止める
と、ビアホール６０ではエッチングが進み過ぎてしまう
問題が生じ、逆に、ビアホール６０のエッチングが終了
した時点でエッチングを止めると、ビアホール６１のエ
ッチングが未完の状態で終了する問題が生じる。As a result, via holes 60 and 6
In etching 1 and 2, a difference in etching speed occurs between the two due to a loading effect (a phenomenon in which the consumption of radicals in dry etching increases and the etching speed decreases when the area to be etched increases). If the etching is stopped at the time when the etching is completed, there occurs a problem that the etching proceeds too much in the via hole 60. Conversely, if the etching is stopped when the etching of the via hole 60 is completed, the etching of the via hole 61 is incomplete. There is a problem of termination.

【００１０】すなわち、上述したローディング効果によ
ってエッチング不良が生じ、均一なエッチングが行え
ず、結果、配線間の接続不良、配線自身の特性不良が発
生する危惧がある。本発明は、半導体装置の改良に関
し、係る問題点を解消せんとするものである。That is, the above-described loading effect causes an etching failure, and uniform etching cannot be performed. As a result, there is a fear that a connection failure between wirings and a characteristic failure of the wirings themselves may occur. The present invention has been made to solve such a problem with respect to improvement of a semiconductor device.

【００１１】[0011]

【課題を解決するための手段】請求項１の半導体装置
は、ボンディングパッドと電極部とを電気的に接続する
ためのコンタクトホールの幅又は径を狭く設定したもの
である。また、請求項２の半導体装置は、ボンディング
パッドと電極部とを幅の狭いスリット状のコンタクトホ
ールを介して電気的に接続したものである。According to a first aspect of the present invention, a width or a diameter of a contact hole for electrically connecting a bonding pad and an electrode portion is set to be small. According to a second aspect of the present invention, the bonding pad and the electrode portion are electrically connected to each other through a narrow slit-shaped contact hole.

【００１２】また、請求項３の半導体装置は、ボンディ
ングパッドと電極部とを、複数の幅の狭いスリット状の
コンタクトホールを介して電気的に接続したものであ
る。また、請求項４の半導体装置は、ボンディングパッ
ドと電極部とを、複数の径の小さなコンタクトホールを
介して電気的に接続したものである。また、請求項５の
半導体装置は、ボンディングパッドと電極部とを電気的
に接続するためのコンタクトホールの幅又は径を、この
コンタクトホールと同じ層に形成された他のコンタクト
ホールの幅又は径とほぼ等しく設定したものである。According to a third aspect of the present invention, the bonding pad and the electrode portion are electrically connected via a plurality of narrow slit-shaped contact holes. According to a fourth aspect of the present invention, the bonding pad and the electrode portion are electrically connected via a plurality of small-diameter contact holes. Further, according to the semiconductor device of the present invention, the width or diameter of a contact hole for electrically connecting a bonding pad and an electrode portion is set to the width or diameter of another contact hole formed in the same layer as the contact hole. It is set approximately equal to.

【００１３】また、請求項６の半導体装置は、前記コン
タクトホールの幅又は径を１μｍ以下に設定したもので
ある。すなわち、ボンディングパッドと電極部とを接続
するためのコンタクトホール（ビアホール）を例えば幅
の狭いスリット状にするなどして、その幅又は径を狭く
設定することにより、コンタクトホールの大きさが、同
じ層にある他のコンタクトホールの大きさに近くなる。Further, in the semiconductor device according to the present invention, the width or diameter of the contact hole is set to 1 μm or less. That is, by setting the width or diameter of the contact hole (via hole) for connecting the bonding pad and the electrode portion to be small, for example, by making the width or diameter of the contact hole small, the size of the contact hole is the same. It is close to the size of other contact holes in the layer.

【００１４】特に、電極部とボンディングパッドとを複
数個所で電気的接続することにより、各コンタクトホー
ルの幅又は径が小さくなっているにもかかわらず、配線
抵抗の増大を抑制できる。また、図７はコンタクトホー
ルの幅とエッチングレートとの関係を示したものであ
り、コンタクトホールの幅が１μｍ以下であると、エッ
チングレートはほとんど変化しない。そこで、コンタク
トホールの幅又は径を１μｍ以下にすることにより、ロ
ーディング効果に影響されにくいエッチングが行われ
る。In particular, by electrically connecting the electrode portion and the bonding pad at a plurality of locations, it is possible to suppress an increase in wiring resistance even though the width or diameter of each contact hole is reduced. FIG. 7 shows the relationship between the width of the contact hole and the etching rate. When the width of the contact hole is 1 μm or less, the etching rate hardly changes. Therefore, by making the width or diameter of the contact hole 1 μm or less, etching that is less affected by the loading effect is performed.

【００１５】[0015]

【発明の実施の形態】本発明を具体化した実施形態を図
面に基づいて説明する。但し、図８に示した従来例と同
等の構成部材には同じ符号を用い、その詳細な説明を省
略する。本実施形態が図８に示した従来技術と異なるの
は、図１に示すように、電極部５８とボンディングパッ
ド５９とを接続するためのビアホール（コンタクトホー
ル）１を複数設けると共に、それぞれの形状を幅（１μ
ｍ）×長さ（１０μｍ）の長方形からなるスリット状に
したことである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described with reference to the drawings. However, the same reference numerals are used for the same components as those in the conventional example shown in FIG. 8, and the detailed description is omitted. This embodiment is different from the prior art shown in FIG. 8 in that, as shown in FIG. 1, a plurality of via holes (contact holes) 1 for connecting an electrode portion 58 and a bonding pad 59 are provided, and each of the via holes (contact holes) 1 has a different shape. The width (1μ
m) × length (10 μm).

【００１６】すなわち、絶縁膜５４、５５の該当個所に
は、３行３列に配列されたビアホール１群が四方に設け
られている。以下、本実施形態における半導体装置の製
造プロセスを図２〜図４に基づいて説明する。尚、各図
において、左側がＭＯＳトランジスタを覆う部分、右側
がボンディングパッドの部分を示している。That is, a group of via holes 1 arranged in three rows and three columns are provided on all sides at corresponding portions of the insulating films 54 and 55. Hereinafter, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. In each figure, the left side shows a portion covering the MOS transistor, and the right side shows a bonding pad portion.

【００１７】工程１（図２参照）：層間絶縁膜５３によ
り基板５２上に形成されたＭＯＳトランジスタ２や下部
電極３を覆う。更に、層間絶縁膜５３に、コンタクトホ
ール４・・を形成すると共に、層間絶縁膜５３上には、
前記コンタクトホール４・・を介して前記ＭＯＳトラン
ジスタ２のソース／ドレイン部２ａ及び下部電極３と接
続される第２の配線層５６を形成する。Step 1 (see FIG. 2): The MOS transistor 2 and the lower electrode 3 formed on the substrate 52 are covered with the interlayer insulating film 53. Further, contact holes 4 are formed in the interlayer insulating film 53, and on the interlayer insulating film 53,
A second wiring layer 56 connected to the source / drain portion 2a and the lower electrode 3 of the MOS transistor 2 via the contact holes 4 is formed.

【００１８】このとき、第２配線層５６の端部には、従
来と同様、電極部５８も同時に形成される。第２配線層
５６及び電極部５８はＡｌを主成分とする合金からな
り、共に同一のリソグラフィ工程及びエッチング工程に
よりパターニングされる。 工程２（図３参照）：第２配線層５６及び電極部５８を
覆うように、プラズマＣＶＤ法を用いて層間絶縁膜（Ｓ
ｉＯ2，ＳｉＮ，ＳｉＯＦ，ＢＰＳＧ，ＰＳＧなど）５
４、５５を堆積する。At this time, an electrode portion 58 is formed at the end of the second wiring layer 56 at the same time as in the related art. The second wiring layer 56 and the electrode portion 58 are made of an alloy containing Al as a main component, and are both patterned by the same lithography step and etching step. Step 2 (see FIG. 3): An interlayer insulating film (S) is formed by using a plasma CVD method so as to cover the second wiring layer 56 and the electrode portion 58.
iO 2 , SiN, SiOF, BPSG, PSG, etc.) 5
4, 55 are deposited.

【００１９】この層間絶縁膜５５（５４）の表面をＣＭ
Ｐ法を用いて平坦化した後、表面に、前記ビアホール１
及びビアホール６０を形成するためのフォトレジストパ
ターン５を形成する。このレジストパターン５の開口部
６・・の最小寸法は、前記ビアホール１に対応するもの
も前記ビアホール６０に対応するものもほぼ同じ（すな
わち、約１μｍ）に設定されている。The surface of the interlayer insulating film 55 (54) is
After planarization using the P method, the via hole 1 is formed on the surface.
And a photoresist pattern 5 for forming a via hole 60 is formed. The minimum size of the openings 6... Of the resist pattern 5 is set to be substantially the same (that is, about 1 μm) for the one corresponding to the via hole 1 and the one corresponding to the via hole 60.

【００２０】工程３（図４参照）：レジストパターン５
をマスクとして、ＲＩＥ（ReactiveIon Echting）法を
用いた異方性エッチング（圧力：２００mTorr、ＲＦパ
ワー：８００W、使用ガス：ＣＨＦ3／ＣＦ4／Ａｒ）に
より、層間絶縁膜５４、５５にビアホール１及びビアホ
ール６０を形成する。この時、ビアホール１及びビアホ
ール６０の幅は、上述した通りどちらも約１μｍとほぼ
同じであるので、ローディング効果が生じることなく、
均一な速度でエッチングが行われる。Step 3 (see FIG. 4): resist pattern 5
Is used as a mask, anisotropic etching (pressure: 200 mTorr, RF power: 800 W, gas: CHF 3 / CF 4 / Ar) using RIE (Reactive Ion Echting) method to form via holes 1 and 55 in interlayer insulating films 54 and 55. A via hole 60 is formed. At this time, the width of the via hole 1 and the width of the via hole 60 are substantially the same as about 1 μm as described above, so that the loading effect does not occur.
Etching is performed at a uniform rate.

【００２１】その後は、層間絶縁膜５５（５４）上に、
ビアホール６０を介して第１配線層に接続される第２配
線層７を形成すると共に、ビアホール１を介して電極部
５８に接続されるボンディングパッド５９を形成する。
以上の通り、本実施形態にあっては、ボンディングパッ
ド５９と電極部５８とを接続するためのビアホールを細
分化することにより、ビアホールの最小幅（径）が同じ
層にある他のビアホールとほぼ等しくなって、ビアホー
ル形成時のローディング効果の発生が抑制される。Thereafter, on the interlayer insulating film 55 (54),
The second wiring layer 7 connected to the first wiring layer via the via hole 60 is formed, and the bonding pad 59 connected to the electrode portion 58 via the via hole 1 is formed.
As described above, in the present embodiment, the via hole for connecting the bonding pad 59 and the electrode portion 58 is subdivided, so that the minimum width (diameter) of the via hole is substantially the same as other via holes in the same layer. As a result, the generation of the loading effect at the time of forming the via hole is suppressed.

【００２２】尚、上記実施形態にあっては、幅（１μ
ｍ）の長方形からなるスリット状のビアホール１を複数
四方に配列することによりビアホール１群を形成してい
るが、図５に示すビアホール８のように、幅（１μｍ）
の環状のスリットであってもよい。また、このスリット
も、図のように正方形である必要は無く、円形や３角形
などどのような形状であっても良い。In the above embodiment, the width (1 μm)
m), a group of via holes 1 is formed by arranging a plurality of slit-shaped via holes 1 each having a rectangular shape as shown in FIG. 5, and has a width (1 μm) as shown in a via hole 8 shown in FIG.
Annular slit may be used. Also, this slit need not be square as shown in the figure, but may be any shape such as a circle or a triangle.

【００２３】更には、上記実施形態における、幅（１μ
ｍ）の長方形からなるスリット状のビアホール１の形状
を、図６に示すように１辺が１μｍの正方形にしても良
く、更には、直径が１μｍの円形にしても良い。Furthermore, in the above embodiment, the width (1 μm)
The shape of the slit-shaped via hole 1 formed of the rectangle m) may be a square having a side of 1 μm as shown in FIG. 6, or a circle having a diameter of 1 μm.

【００２４】[0024]

【発明の効果】本発明にあっては、ボンディングパッド
と電極部とを接続するためのコンタクトホール（ビアホ
ール）の幅又は径を狭く設定することにより、コンタク
トホールの大きさが、同じ層にある他のコンタクトホー
ルの大きさに近くなる。従って、ローディング効果の発
生を抑制することができ、これによるエッチング不良や
不均一なエッチングの発生を防止し、結果、良好な多層
配線構造を形成することができる。According to the present invention, by setting the width or diameter of the contact hole (via hole) for connecting the bonding pad and the electrode portion to be small, the size of the contact hole is in the same layer. It becomes closer to the size of other contact holes. Therefore, it is possible to suppress the occurrence of the loading effect, thereby preventing the occurrence of poor etching and uneven etching, and as a result, it is possible to form a good multilayer wiring structure.

【００２５】特に、電極部とボンディングパッドとを複
数個所で電気的接続することにより、各コンタクトホー
ルの幅又は径が小さくなっているにもかかわらず、配線
抵抗の増大を抑制できる。また、コンタクトホールの幅
又は径を１μｍ以下にすることにより、よりローディン
グ効果に影響されにくいエッチングを行うことができ
る。In particular, by electrically connecting the electrode portion and the bonding pad at a plurality of locations, it is possible to suppress an increase in wiring resistance even though the width or diameter of each contact hole is reduced. By setting the width or diameter of the contact hole to 1 μm or less, etching that is less affected by the loading effect can be performed.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態におけるビアホール部の平面
図。FIG. 1 is a plan view of a via hole according to an embodiment of the present invention.

【図２】本発明の実施形態における半導体装置の製造プ
ロセスを順次示す断面図。FIG. 2 is a sectional view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図３】本発明の実施形態における半導体装置の製造プ
ロセスを順次示す断面図。FIG. 3 is a sectional view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図４】本発明の実施形態における半導体装置の製造プ
ロセスを順次示す断面図。FIG. 4 is a sectional view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図５】本発明の他の実施形態におけるビアホール部の
平面図。FIG. 5 is a plan view of a via hole according to another embodiment of the present invention.

【図６】本発明の他の実施形態におけるビアホール部の
平面図。FIG. 6 is a plan view of a via hole according to another embodiment of the present invention.

【図７】本発明の実施形態を説明するための特性図。FIG. 7 is a characteristic diagram for explaining the embodiment of the present invention.

【図８】従来例における半導体装置の断面図FIG. 8 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１、８ ビアホール（コンタクトホール） ５８ 電極部 ５９ ボンディングパッド ６０ ビアホール（他のコンタクトホール） 1, 8 via hole (contact hole) 58 electrode section 59 bonding pad 60 via hole (other contact hole)

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 ボンディングパッドと電極部とを電気的
に接続するためのコンタクトホールの幅又は径を狭く設
定したことを特徴とする半導体装置。1. A semiconductor device wherein a width or a diameter of a contact hole for electrically connecting a bonding pad and an electrode portion is set to be small. 【請求項２】 ボンディングパッドと電極部とを幅の狭
いスリット状のコンタクトホールを介して電気的に接続
したことを特徴とする半導体装置。2. A semiconductor device wherein a bonding pad and an electrode portion are electrically connected via a narrow slit-shaped contact hole. 【請求項３】 ボンディングパッドと電極部とを、複数
の幅の狭いスリット状のコンタクトホールを介して電気
的に接続したことを特徴とする半導体装置。3. A semiconductor device, wherein a bonding pad and an electrode portion are electrically connected via a plurality of narrow slit-shaped contact holes. 【請求項４】 ボンディングパッドと電極部とを、複数
の径の小さなコンタクトホールを介して電気的に接続し
たことを特徴とする半導体装置。4. A semiconductor device, wherein a bonding pad and an electrode portion are electrically connected via a plurality of small-diameter contact holes. 【請求項５】 ボンディングパッドと電極部とを電気的
に接続するためのコンタクトホールの幅又は径を、この
コンタクトホールと同じ層に形成された他のコンタクト
ホールの幅又は径とほぼ等しく設定したことを特徴とす
る半導体装置。5. The width or diameter of a contact hole for electrically connecting a bonding pad and an electrode portion is set substantially equal to the width or diameter of another contact hole formed in the same layer as the contact hole. A semiconductor device characterized by the above-mentioned. 【請求項６】 前記コンタクトホールの幅又は径が１μ
ｍ以下であることを特徴とした請求項１乃至５のいずれ
か１項に記載の半導体装置。6. The contact hole has a width or diameter of 1 μm.
The semiconductor device according to claim 1, wherein m is equal to or less than m.
JP9234455A 1997-08-29 1997-08-29 Semiconductor device Pending JPH1174271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9234455A JPH1174271A (en) 1997-08-29 1997-08-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9234455A JPH1174271A (en) 1997-08-29 1997-08-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1174271A true JPH1174271A (en) 1999-03-16

Family

ID=16971277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9234455A Pending JPH1174271A (en) 1997-08-29 1997-08-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1174271A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7898084B2 (en) 2005-01-18 2011-03-01 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7898084B2 (en) 2005-01-18 2011-03-01 Kabushiki Kaisha Toshiba Semiconductor device

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