JPH1167966A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1167966A JPH1167966A JP24046997A JP24046997A JPH1167966A JP H1167966 A JPH1167966 A JP H1167966A JP 24046997 A JP24046997 A JP 24046997A JP 24046997 A JP24046997 A JP 24046997A JP H1167966 A JPH1167966 A JP H1167966A
- Authority
- JP
- Japan
- Prior art keywords
- support base
- terminal conductors
- emitting diode
- light emitting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、静電破壊防止手段
を有する発光ダイオード等の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a light emitting diode having a means for preventing electrostatic breakdown.
【０００２】[0002]
【従来の技術】図１に示すように、従来のＧａＮ（窒化
ガリウム）半導体を使用した青色発光ダイオード１は、
発光ダイオードチップ（発光素子）２と、端子導体とし
て機能する第１及び第２のリード３、４と、包囲体とし
て機能する光透過性及び絶縁性を有する樹脂封止体５と
から成る。発光ダイオードチップ２は、図２に示すよう
にサファイア基板６と、この上にエピタキシャル成長さ
れたｎ型ＧａＮ領域７及びｐ型ＧａＮ領域８から成る半
導体基体９と、ｎ型ＧａＮ領域７に接続された第１の電
極１０と、ｐ型ＧａＮ領域８に接続された第２の電極１
１とを備えている。図１の第１のリード３は、皿状支持
部（ヘッダ）１２を有し、ここに接着剤１３によって発
光ダイオードチップ２のサファイア基板６が固着されて
いる。発光ダイオードチップ２の第１の電極１０は第１
のリード細線１４によって第１のリード３の皿状支持部
１２の上面に接続され、第２の電極１１は第２のリード
４のポスト部１５に第２のリード細線１６で接続されて
いる。透明樹脂封止体５は、発光ダイオードチップ２、
皿状支持部１２、ポスト部１５、第１及び第２のリード
細線１４、１６を被覆するように形成されている。第１
及び第２のリード３、４の棒状部分は樹脂封止体５の底
面から互いに平行に導出されている。2. Description of the Related Art As shown in FIG. 1, a conventional blue light emitting diode 1 using a GaN (gallium nitride) semiconductor is:
It comprises a light emitting diode chip (light emitting element) 2, first and second leads 3, 4 functioning as terminal conductors, and a light-transmitting and insulating resin sealing body 5 functioning as an enclosure. As shown in FIG. 2, the light emitting diode chip 2 is connected to a sapphire substrate 6, a semiconductor substrate 9 composed of an n-type GaN region 7 and a p-type GaN region 8 epitaxially grown thereon, and an n-type GaN region 7. First electrode 10 and second electrode 1 connected to p-type GaN region 8
1 is provided. The first lead 3 in FIG. 1 has a dish-shaped support portion (header) 12, to which the sapphire substrate 6 of the light emitting diode chip 2 is fixed by an adhesive 13. The first electrode 10 of the light emitting diode chip 2 is
The second electrode 11 is connected to the post portion 15 of the second lead 4 by a second thin lead wire 16. The transparent resin sealing body 5 includes the light emitting diode chip 2,
It is formed so as to cover the dish-shaped support part 12, the post part 15, and the first and second fine lead wires 14, 16. First
The rod-shaped portions of the second leads 3 and 4 are led out of the bottom surface of the resin sealing body 5 in parallel with each other.
【０００３】[0003]
【発明が解決しようとする課題】ところで、人体等の帯
電している物体がリード３又は４に接触することによっ
て発光ダイオード１のチップ２が静電破壊されることが
あった。これは発光ダイオードチップ２の互いに接近配
置されかつオープンになっている第１及び第２の電極１
０、１１間に静電気の高電圧が印加され、結果として半
導体基体９のｐｎ接合に高電圧が印加されるために生じ
る。この静電気による破壊は特にＧａＮ発光ダイオード
において生じ易いが、別の半導体装置においても生じる
おそれがある。By the way, when a charged object such as a human body comes into contact with the lead 3 or 4, the chip 2 of the light emitting diode 1 may be electrostatically damaged. This means that the first and second electrodes 1 of the light-emitting diode chip 2 are arranged close to each other and are open.
This occurs because a high voltage of static electricity is applied between 0 and 11, and as a result, a high voltage is applied to the pn junction of the semiconductor substrate 9. This destruction due to static electricity is particularly likely to occur in GaN light emitting diodes, but may also occur in other semiconductor devices.
【０００４】そこで、本発明の目的は、容易に静電破壊
を防止することができる半導体装置を提供することにあ
る。An object of the present invention is to provide a semiconductor device which can easily prevent electrostatic breakdown.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、半導体チップと、前記
半導体チップに接続された少なくとも第１及び第２の端
子導体と、前記半導体チップの絶縁性包囲体とを備え、
前記第１及び第２の端子導体の少なくとも一部が前記包
囲体の外側に配置されている半導体装置において、前記
第１及び第２の端子導体を支持するための支持基体が設
けられ、前記支持基体は空気よりも抵抗率の小さい抵抗
性物質で形成され、前記第１及び第２の端子導体間にお
ける前記支持基体の抵抗値が５０ＫΩ〜５０ＭΩである
ことを特徴とする半導体装置に係わるものである。な
お、請求項２に示すように端子導体を棒状部分を有する
ものとし、この棒状部分を支持基体の溝又は孔に挿入す
ることができる。また、請求項３に示すように端子導体
を導体層とすることができる。また、請求項４に示すよ
うに第１及び第２の端子導体の棒状部分を挿入する支持
基体に抵抗体層を設け、この抵抗体層を第１及び第２の
端子導体に電気的に接続することができる。なお、本発
明における半導体チップは、発光ダイオードチップ、絶
縁ゲート電界効果トランジスタを含むチップ等の静電破
壊され易いチップを意味する。SUMMARY OF THE INVENTION In order to solve the above problems and achieve the above object, the present invention provides a semiconductor chip, at least first and second terminal conductors connected to the semiconductor chip, and a semiconductor chip. An insulating enclosure of the chip,
In a semiconductor device in which at least a part of the first and second terminal conductors is arranged outside the enclosure, a support base for supporting the first and second terminal conductors is provided, and The semiconductor device according to claim 1, wherein the base is formed of a resistive material having a lower resistivity than air, and a resistance value of the support base between the first and second terminal conductors is 50 KΩ to 50 MΩ. is there. It is to be noted that the terminal conductor has a rod-shaped portion as described in claim 2, and this rod-shaped portion can be inserted into a groove or a hole of the support base. Further, as described in claim 3, the terminal conductor can be a conductor layer. According to a fourth aspect of the present invention, a resistor layer is provided on a support base into which the rod portions of the first and second terminal conductors are inserted, and the resistor layer is electrically connected to the first and second terminal conductors. can do. Note that the semiconductor chip in the present invention means a chip which is easily damaged by electrostatic discharge such as a light emitting diode chip and a chip including an insulated gate field effect transistor.
【０００６】[0006]
【発明の効果】各請求項の発明によれば、第１及び第２
の端子導体間に静電気による電圧が印加された時に、抵
抗性の支持基体又は支持基体の抵抗体層がバイパスとし
て機能し、ここで静電気のエネルギが消費され、半導体
チップが静電気から保護される。また、第１及び第２の
端子導体間の抵抗値が５０ｋΩ〜５０ＭΩの範囲である
ので、ここを通るリーク電流が実用上問題にならない程
度となる。According to the invention of each claim, the first and the second are provided.
When a voltage due to static electricity is applied between the terminal conductors, the resistive support base or the resistor layer of the support base functions as a bypass, where the energy of the static electricity is consumed and the semiconductor chip is protected from the static electricity. Further, since the resistance value between the first and second terminal conductors is in the range of 50 kΩ to 50 MΩ, the leakage current passing therethrough is of a level that does not pose a practical problem.
【０００７】[0007]
【実施形態及び実施例】次に、本発明の実施形態及び実
施例を図３〜図６を参照して説明する。但し、第１の実
施例を示す図３及び第２、第３の実施例を示す図５、図
６において図１及び図２と実質的に同一の部分には同一
の符号を付してその説明を省略する。Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS. However, in FIGS. 3 and 2 showing the first embodiment and FIGS. 5 and 6 showing the third embodiment, substantially the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. Description is omitted.
【０００８】[0008]
【第１の実施例】図３に示す第１の実施例の発光ダイオ
ード１ａは、半導体チップとしての発光ダイオードチッ
プ２、第１及び第２の端子導体としての金属製棒状リー
ド３、４、包囲体としての光透過性樹脂封止体５、及び
第１及び第２の金属リード細線１４、１６を図１の発光
ダイオード１と同様に有する他に、本発明に従う抵抗性
支持基体１７を有している。First Embodiment A light-emitting diode 1a according to a first embodiment shown in FIG. 3 includes a light-emitting diode chip 2 as a semiconductor chip, metal rod-shaped leads 3, 4 as first and second terminal conductors, and an enclosure. In addition to the light-transmitting resin sealing body 5 as a body and the first and second thin metal lead wires 14 and 16 as in the light-emitting diode 1 of FIG. ing.
【０００９】抵抗性支持基体１７は、図４に示すように
第１及び第２の溝１８、１９を有し、ここに第１及び第
２のリード３、４が嵌合されている。また、第１及び第
２のリード３、４のフランジ状部３ａ、４ａの底面が抵
抗性支持基体１７の上面に当接し、棒状部分が支持基体
１７の溝１８、１９に挿入されている。これにより、抵
抗性支持基体１７は第１及び第２のリード３、４を機械
的に支持し、且つ第１及び第２のリード３、４間を電気
的に接続している。As shown in FIG. 4, the resistive support base 17 has first and second grooves 18 and 19 into which first and second leads 3 and 4 are fitted. Further, the bottom surfaces of the flange portions 3a, 4a of the first and second leads 3, 4 abut against the upper surface of the resistive support base 17, and the rod-shaped portions are inserted into the grooves 18, 19 of the support base 17. Accordingly, the resistive support base 17 mechanically supports the first and second leads 3 and 4 and electrically connects the first and second leads 3 and 4.
【００１０】抵抗性支持基体１７は、微細な導電性粒子
が混入されたエポキシ系の樹脂の板状体から成り、弱い
導電性を有している。この抵抗性支持基体１７の第１及
び第２のリード３、４間の抵抗値は約３ＭΩである。な
お、抵抗性支持基体１７の抵抗率は空気及び樹脂封止体
５の抵抗率よりも小さい。また、第１及び第２のリード
３、４間の抵抗性支持基体１７の抵抗値は第１及び第２
のリード３、４間の樹脂封止体５の抵抗値よりも小さ
い。The resistive support base 17 is made of a plate-like body of an epoxy resin mixed with fine conductive particles and has weak conductivity. The resistance value between the first and second leads 3 and 4 of the resistive support base 17 is about 3 MΩ. Note that the resistivity of the resistive support base 17 is lower than the resistivity of the air and the resin sealing body 5. The resistance value of the resistive support base 17 between the first and second leads 3 and 4 is equal to the first and second leads.
Is smaller than the resistance value of the resin sealing body 5 between the leads 3 and 4.
【００１１】抵抗性支持基体１７は樹脂封止体５に埋設
され、この抵抗性支持基体１７の下面を覆う樹脂封止体
５から第１及び第２のリード３、４が外部に導出されて
いる。なお、抵抗性支持基体１７の下面を樹脂封止体５
で被覆しない構造とすることもできる。The resistive support base 17 is embedded in the resin sealing body 5, and the first and second leads 3 and 4 are led out from the resin sealing body 5 covering the lower surface of the resistive support base 17. I have. Note that the lower surface of the resistive support base 17 is
It is also possible to adopt a structure that is not covered with.
【００１２】図３の発光ダイオードを製造する時には、
抵抗性支持基体１７の第１及び第２の溝１８、１９に第
１及び第２のリード３、４を挿入する。なお、第１及び
第２のリ−ド３、４は複数の発光ダイオ−ドを実質的に
同時に形成するためにリ−ドフレ−ム構成になっている
ので、このリ−ドフレ−ムにおける第１及び第２のリ−
ド３、４に支持基体１７を嵌合させる。次に、周知のダ
イボンディング方法とワイヤボンディング方法によっ
て、発光ダイオードチップ２のヘッダ１２への固着と、
リード細線１４、１６の接続を行う。続いて、この発光
ダイオード組立体を成形金型内に配置して、周知のモー
ルディング方法によって樹脂封止体５を形成して発光ダ
イオード１ａを完成させる。When manufacturing the light emitting diode of FIG. 3,
The first and second leads 3 and 4 are inserted into the first and second grooves 18 and 19 of the resistive support base 17. Since the first and second leads 3 and 4 have a lead frame structure for forming a plurality of light emitting diodes substantially simultaneously, the first and second leads 3 and 4 have the same structure. 1st and 2nd lead
The support base 17 is fitted to the hands 3 and 4. Next, the light emitting diode chip 2 is fixed to the header 12 by a known die bonding method and a wire bonding method.
The connection of the lead wires 14 and 16 is performed. Subsequently, the light emitting diode assembly is arranged in a molding die, and a resin sealing body 5 is formed by a well-known molding method to complete the light emitting diode 1a.
【００１３】第１の実施例の発光ダイオード１ａは、次
の効果を有する。 （イ） 第１及び第２のリード３、４の相互間に弱い導
電性の抵抗性支持基体１７が介在するので、第１及び第
２のリード３、４間に静電気が印加されても、その電気
エネルギが抵抗性支持基体１７にバイパスし、ダイオー
ドチップ２の電極１０、１１間にダイオードチップ２を
破壊するようなエネルギが加わらず、ダイオードチップ
２を静電気から保護できる。 （ロ） 抵抗性支持基体１７は、約３ＭΩの抵抗値を有
するので、ここを通るリーク電流は発光ダイオード１ａ
のリーク電流チェック等の特性測定上もしくは使用上に
おいて実質的に問題にならないレベルである。例えば、
３Ｖでリーク電流をチェックする場合において抵抗性支
持基体１７には３Ｖ／３ＭΩ＝１μＡの電流が流れるの
みであり、リーク電流チェックの上限値が５μＡである
とすれば、抵抗性支持基体１７の電流はさほど問題にな
らない。 （ハ） 支持基体１７を設けることによって第１及び第
２のリ−ド３、４の機械的安定性が向上する。The light emitting diode 1a of the first embodiment has the following effects. (B) Since the weak conductive resistive support base 17 is interposed between the first and second leads 3 and 4, even if static electricity is applied between the first and second leads 3 and 4, The electric energy is bypassed to the resistive support base 17 and the diode chip 2 can be protected from static electricity without applying any energy between the electrodes 10 and 11 of the diode chip 2 to destroy the diode chip 2. (B) Since the resistance supporting base 17 has a resistance value of about 3 MΩ, the leakage current passing therethrough is the light emitting diode 1a.
This is a level that does not substantially cause a problem in characteristic measurement such as a leak current check or in use. For example,
When the leakage current is checked at 3 V, only a current of 3 V / 3 MΩ = 1 μA flows through the resistive support base 17. If the upper limit of the leak current check is 5 μA, the current of the resistive support base 17 is It doesn't matter much. (C) By providing the support base 17, the mechanical stability of the first and second leads 3, 4 is improved.
【００１４】[0014]
【第２の実施例】図５に示す第２の実施例の発光ダイオ
ード１ｂは、図３の発光ダイオード１ａと同様に発光ダ
イオードチップ２、包囲体の一部として機能する光透過
性及び絶縁性樹脂封止体５、第１及び第２のリード細線
１４、１６、及び抵抗性支持基体１７ａを有する。図５
の発光ダイオード１ｂは表面実装型に形成されているの
で、抵抗性支持基体１７ａの表面に外部リードとして機
能する第１及び第２の端子導体層２１、２２が設けられ
ている。即ち、第１及び第２の端子導体層２１、２２が
抵抗性支持基体１７ａの表面側から側面を通って裏面側
に至るように設けられている。発光ダイオードチップ２
は抵抗性支持基体１７ａの上の端子導体層２１に接着剤
１３で固着され、第１及び第２のリード細線１４、１６
によって第１及び第２の電極１０、１１と第１及び第２
の端子導体層２１、２２が接続されている。光透過性樹
脂封止体５はチップ２、リード細線１４、１６及び抵抗
性支持基体１７ａの上面を被覆するように形成されてい
る。従って、抵抗性支持基体１７ａはチップ２の包囲体
の一部としても機能している。Second Embodiment A light-emitting diode 1b according to a second embodiment shown in FIG. 5 has a light-emitting diode chip 2 and a light-transmitting and insulating material functioning as a part of an enclosure like the light-emitting diode 1a in FIG. It has a resin sealing body 5, first and second fine lead wires 14, 16, and a resistive support base 17a. FIG.
Since the light emitting diode 1b is formed in a surface mounting type, the first and second terminal conductor layers 21 and 22 functioning as external leads are provided on the surface of the resistive support base 17a. That is, the first and second terminal conductor layers 21 and 22 are provided so as to extend from the front surface side of the resistive support base 17a to the rear surface side through the side surfaces. Light emitting diode chip 2
Are fixed to the terminal conductor layer 21 on the resistive support base 17a with the adhesive 13, and the first and second lead wires 14, 16
And the first and second electrodes 10, 11 and the first and second electrodes
Terminal conductor layers 21 and 22 are connected. The light-transmitting resin sealing body 5 is formed so as to cover the upper surfaces of the chip 2, the lead wires 14, 16 and the resistive support base 17a. Therefore, the resistive support base 17a also functions as a part of the surrounding body of the chip 2.
【００１５】図５の抵抗性支持基体１７ａは図３の抵抗
性支持基体１７と同一材料で形成され、第１及び第２の
端子導体層２１、２２間の抵抗値が約３ＭΩになるよう
に抵抗率及び第１及び第２の端子導体層２１、２２のパ
ターンが決定されている。従って、図５の抵抗性支持基
体１７ａによっても図３の抵抗性支持基体１７と同一の
作用効果が得られる。The resistive support base 17a of FIG. 5 is formed of the same material as the resistive support base 17 of FIG. 3 so that the resistance between the first and second terminal conductor layers 21 and 22 is about 3 MΩ. The resistivity and the pattern of the first and second terminal conductor layers 21 and 22 are determined. Therefore, the same operation and effect as the resistive support base 17 of FIG. 3 can be obtained by the resistive support base 17a of FIG.
【００１６】[0016]
【第３の実施例】図６に示す第３の実施例の発光ダイオ
−ド１ｃは、図３の発光ダイオ−ド１ａの一部を変形し
た他は図３と同一に構成したものである。図６の支持基
体１７ｂは、幾何学的形状において図３の支持基体１７
と同一であるが、導電性物質は含まず、絶縁材料である
セラミックから成る。この絶縁性支持基体１７ｂの表面
には抵抗体層２０が設けられている。この抵抗体層２０
は導電性粒子を樹脂に混入したものを塗布して形成した
ものであり、第１及び第２の３、４に電気的に接続され
ている。なお、電気的接続を確実に達成するために第１
及び第２のリ−ド３、４と抵抗体層２０とを導電性接着
剤で結合させることができる。リ−ド３、４間の抵抗体
層２０の抵抗値は約３ＭΩである。この第３の実施例に
よっても、第１の実施例と同一の効果を得ることができ
る。Third Embodiment A light emitting diode 1c according to a third embodiment shown in FIG. 6 has the same configuration as that of FIG. 3 except that a part of the light emitting diode 1a of FIG. 3 is modified. . The support base 17b of FIG. 6 is similar to the support base 17 of FIG.
, Except that it does not contain a conductive substance and is made of ceramic which is an insulating material. A resistor layer 20 is provided on the surface of the insulating support base 17b. This resistor layer 20
Is formed by applying a mixture of conductive particles to a resin, and is electrically connected to the first and second 3 and 4. In addition, in order to surely achieve the electrical connection, the first
In addition, the second leads 3 and 4 and the resistor layer 20 can be connected with a conductive adhesive. The resistance value of the resistor layer 20 between the leads 3 and 4 is about 3 MΩ. According to the third embodiment, the same effect as that of the first embodiment can be obtained.
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 第１及び第２の端子導体としての第１及び第２
のリード３、４間の抵抗性支持基体１７の抵抗値及び第
１及び第２の端子導体層２１、２２間の抵抗性支持基体
１７ａの抵抗値及び図６の第１及び第２のリ−ド３、４
間の抵抗体層２０の抵抗値を必要に応じて変えることが
できる。この抵抗値を５０ｋΩ〜５０ＭΩの範囲に入る
値にすると、静電破壊防止の効果が得られる。なお、チ
ップ２のリーク電流チェックを妨害しないようにするた
めには、上記抵抗値を１〜５ＭΩの範囲にすることが望
ましい。 （２） 図５の支持基体１７ａに貫通孔又は溝を設け、
端子導体層２１、２２を基体１７ａの表面側から裏面側
に貫通孔又は溝を介して導くことができる。 （３） ＧａＮ発光ダイオード以外の発光ダイオード又
は絶縁ゲート型電界効果トランジスタ等の別の半導体装
置にも本発明を適用することができる。 （４） 図３及び図６の支持基体１７、１７ｂの溝１
８、１９を貫通孔に変えることができる。 （５） 図３及び図５において、支持基体１７、１７ａ
を導電性（抵抗性）を有する酸化物焼結体とすることが
できる。 （６） 図３において、支持基体１７の第１及び第２の
リ−ド３、４に対する接触部分に導体層を設け、第１及
び第２のリ−ド３、４に対する電気的接続を確実に達成
することができる。 （７） 図６の抵抗体層２０の代りに断面積の小さい極
めて薄い導体層を設けることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) First and second terminals as first and second terminal conductors
The resistance value of the resistive support base 17 between the leads 3 and 4 and the resistance value of the resistive support base 17a between the first and second terminal conductor layers 21 and 22 and the first and second leads of FIG. C3, C4
The resistance value of the resistor layer 20 between them can be changed as needed. By setting the resistance to a value within the range of 50 kΩ to 50 MΩ, an effect of preventing electrostatic breakdown can be obtained. In order to prevent the leakage current check of the chip 2 from being disturbed, it is desirable that the resistance value be in a range of 1 to 5 MΩ. (2) A through hole or a groove is provided in the support base 17a of FIG.
The terminal conductor layers 21 and 22 can be guided from the front surface side of the base 17a to the rear surface side through through holes or grooves. (3) The present invention can be applied to light emitting diodes other than GaN light emitting diodes or other semiconductor devices such as insulated gate field effect transistors. (4) Groove 1 of support bases 17 and 17b in FIGS. 3 and 6
8, 19 can be changed to through holes. (5) In FIGS. 3 and 5, the support bases 17 and 17a
Can be an oxide sintered body having conductivity (resistance). (6) In FIG. 3, a conductive layer is provided at a contact portion of the support base 17 with the first and second leads 3 and 4 to ensure electrical connection to the first and second leads 3 and 4. Can be achieved. (7) An extremely thin conductor layer having a small cross-sectional area can be provided instead of the resistor layer 20 of FIG.
【図１】従来の発光ダイオードを示す断面図である。FIG. 1 is a cross-sectional view illustrating a conventional light emitting diode.
【図２】図１のダイオードチップを拡大して示す断面図
である。FIG. 2 is an enlarged sectional view showing the diode chip of FIG. 1;
【図３】本発明の第１の実施例の発光ダイオードを示す
断面図である。FIG. 3 is a sectional view showing a light emitting diode according to a first embodiment of the present invention.
【図４】図３の支持基体を示す平面図である。FIG. 4 is a plan view showing the support base of FIG. 3;
【図５】本発明の第２の実施例の発光ダイオードを示す
断面図である。FIG. 5 is a sectional view showing a light emitting diode according to a second embodiment of the present invention.
【図６】第３の実施例の発光ダイオ−ドを示す断面図で
ある。FIG. 6 is a sectional view showing a light emitting diode of a third embodiment.
２ 発光ダイオードチップ ３、４ リード ５ 光透過性樹脂封止体 １７、１７ａ 抵抗性支持基体 2 light emitting diode chip 3, 4 lead 5 light transmitting resin sealing body 17, 17a resistive support base
Claims (4)
続された少なくとも第１及び第２の端子導体と、前記半
導体チップの絶縁性包囲体とを備え、前記第１及び第２
の端子導体の少なくとも一部が前記包囲体の外側に配置
されている半導体装置において、 前記第１及び第２の端子導体を支持するための支持基体
が設けられ、 前記支持基体は空気よりも抵抗率の小さい抵抗性物質で
形成され、 前記第１及び第２の端子導体間における前記支持基体の
抵抗値が５０ｋΩ〜５０ＭΩであることを特徴とする半
導体装置。1. A semiconductor device comprising: a semiconductor chip; at least first and second terminal conductors connected to the semiconductor chip; and an insulating enclosure of the semiconductor chip.
In a semiconductor device in which at least a part of the terminal conductor is disposed outside the enclosure, a support base for supporting the first and second terminal conductors is provided, and the support base is more resistant than air. A semiconductor device formed of a resistive material having a low rate, wherein a resistance value of the support base between the first and second terminal conductors is 50 kΩ to 50 MΩ.
をそれぞれ有し、 前記支持基体は溝又は孔を有し、前記溝又は孔に前記第
１及び第２の端子導体の棒状部分が挿入されていること
を特徴とする請求項１記載の半導体装置。2. The first and second terminal conductors each have a rod-shaped portion, the support base has a groove or a hole, and the rod-shaped portion of the first and second terminal conductors is formed in the groove or the hole. 2. The semiconductor device according to claim 1, wherein the semiconductor device is inserted.
基体に設けられた導体層から成ることを特徴とする請求
項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said first and second terminal conductors are formed of a conductor layer provided on said support base.
続された少なくとも第１及び第２の端子導体と、前記半
導体チップの絶縁性包囲体とを備え、前記第１及び第２
の端子導体の少なくとも一部が前記包囲体の外側に配置
されている半導体装置において、 前記第１及び第２の端子導体を支持するための支持基体
が設けられ、 前記第１及び第２の端子導体は棒状部分をそれぞれ有
し、 前記支持基体に形成された溝又は孔に前記第１及び第２
の端子導体の棒状部分が挿入され、 前記支持基体の少なくとも一部が前記包囲体で被覆さ
れ、 前記支持基体は絶縁性物質から成り、 前記支持基体に抵抗体層が形成され、 前記抵抗体層は前記第１及び第２の端子導体に電気的に
接続され、 前記第１及び第２の端子導体間の前記抵抗体層の抵抗値
が５０ｋΩ〜５０ＭΩであることを特徴とする半導体装
置。4. A semiconductor device comprising: a semiconductor chip; at least first and second terminal conductors connected to the semiconductor chip; and an insulating enclosure of the semiconductor chip.
A semiconductor device in which at least a part of the terminal conductor is disposed outside the enclosure, a support base for supporting the first and second terminal conductors is provided, and the first and second terminals are provided. The conductor has a rod-shaped portion, and the first and second holes are formed in grooves or holes formed in the support base.
Wherein at least a part of the support base is covered with the surrounding body; the support base is made of an insulating material; a resistor layer is formed on the support base; Is electrically connected to the first and second terminal conductors, and a resistance value of the resistor layer between the first and second terminal conductors is 50 kΩ to 50 MΩ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24046997A JP2996215B2 (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24046997A JP2996215B2 (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1167966A true JPH1167966A (en) | 1999-03-09 |
| JP2996215B2 JP2996215B2 (en) | 1999-12-27 |
Family
ID=17059985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24046997A Expired - Fee Related JP2996215B2 (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2996215B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009516931A (en) * | 2005-11-22 | 2009-04-23 | ショッキング テクノロジーズ インコーポレイテッド | Light-emitting device using voltage-sensitive state transition dielectric material |
| KR100964370B1 (en) | 2008-04-10 | 2010-06-25 | 조인셋 주식회사 | Led chip package having protection device for instant high-voltage |
| US9208931B2 (en) | 2008-09-30 | 2015-12-08 | Littelfuse, Inc. | Voltage switchable dielectric material containing conductor-on-conductor core shelled particles |
-
1997
- 1997-08-20 JP JP24046997A patent/JP2996215B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009516931A (en) * | 2005-11-22 | 2009-04-23 | ショッキング テクノロジーズ インコーポレイテッド | Light-emitting device using voltage-sensitive state transition dielectric material |
| KR100964370B1 (en) | 2008-04-10 | 2010-06-25 | 조인셋 주식회사 | Led chip package having protection device for instant high-voltage |
| US9208931B2 (en) | 2008-09-30 | 2015-12-08 | Littelfuse, Inc. | Voltage switchable dielectric material containing conductor-on-conductor core shelled particles |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2996215B2 (en) | 1999-12-27 |
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