JP3613328B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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Publication number
JP3613328B2
JP3613328B2 JP2000191368A JP2000191368A JP3613328B2 JP 3613328 B2 JP3613328 B2 JP 3613328B2 JP 2000191368 A JP2000191368 A JP 2000191368A JP 2000191368 A JP2000191368 A JP 2000191368A JP 3613328 B2 JP3613328 B2 JP 3613328B2
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light emitting
emitting diode
transistor
semiconductor light
region
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JP2002009343A (en
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信夫 小林
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

【０００１】
【発明の属する技術分野】
本発明は、保護素子を内蔵した半導体発光装置に関する。
【０００２】
【従来の技術】
近年、窒化ガリウム（ＧａＮ）系半導体を用いた青色半導体発光素子即ち発光ダイオードが注目されている。この発光ダイオードは数十ボルト程度のサージ電圧で破壊するため、例えば、特開平１１−１２０３６号公報に開示されているように発光ダイオードに並列に過電圧防止用のツェナダイオード（定電圧ダイオード）が接続される。これにより、静電気等による過電圧が発光ダイオードに印加された時にツェナダイオードが導通して発光ダイオードが過電圧から保護される。
【０００３】
【発明が解決しようとする課題】
ところで、ツェナダイオード等の保護素子と発光ダイオードとの組立体を構成する時には、保護素子の上にマイクロバンプ電極等によって発光ダイオードを結合させる。このため、発光ダイオードの放熱経路に保護素子が介在し、保護素子が発光ダイオードの放熱性を低下させる。もし、保護素子を設けないで発光ダイオードに流す電流と同一の値の電流を保護素子を設けた発光ダイオードに流すと、発光ダイオードの温度がその許容範囲よりも高くなり、発光ダイオードの劣化又は破損が生じるおそれがある。今、発光ダイオードと保護素子を一体的に組み立てる場合について述べたが、保護素子が発光ダイオードの放熱を妨害しない場合であっても、発光ダイオード等の半導体発光素子の熱破壊は問題になる。
また、発光ダイオード以外の回路素子においても過電圧破壊と熱破壊との両方を防止しなければならない時がある。
【０００４】
そこで、本発明の第１の目的は、半導体発光素子の熱破壊を防ぐことができる半導体発光装置を提供することにある。
本発明の第２の目的は、半導体発光素子の熱破壊と過電圧破壊との両方を防ぐことができる半導体発光装置を提供することにある。
【０００５】
【課題を解決するための手段】
上記課題を解決し、上記目的を達成するための本発明は、半導体発光素子と、前記半導体発光素子に並列に接続され且つ前記半導体発光素子の温度が所定温度よりも高くなった時にオン状態になるか又は抵抗値が低下する特性を有している保護素子と、前記半導体発光素子に並列に接続された過電圧防止用定電圧ダイオードとを有し、前記保護素子は導通開始に要求されるベース・エミッタ間電圧が負の温度係数を有するトランジスタであり、前記トランジスタと前記定電圧ダイオードは同一の半導体基体に形成されており、前記半導体発光素子は前記半導体基体の上に配置されていることを特徴とする半導体発光装置に係わるものである。
【０００６】
なお、請求項２に示すように発光素子を保護素子の上に配置することが望ましい。
【０００７】
【発明の効果】
本発明によれば、半導体発光素子の温度が所定温度よりも高くなると、保護素子がオン又は低抵抗値になり、半導体発光素子のバイパスとして働き、半導体発光素子の電流が遮断又は抑制され、半導体発光素子の温度上昇が抑えられ、この劣化又は破壊が防止される。
また、熱破壊防止と過電圧防止との両方を達成することができる。
また、熱破壊及び過電圧破壊の両方を防ぐことができる発光装置の小型化且つ低コスト化を図ることができる
請求項２の発明によれば、保護素子を有するにも拘らず比較的小さい発光装置を提供することができる。
【０００８】
【実施形態】
次に、図１〜図８を参照して本発明の実施形態を説明する。
【０００９】
【第１の実施形態】
図１〜図５に示す第１の実施形態の半導体発光装置１は、発光素子としての窒化ガリウム（ＧａＮ）系発光ダイオード２と、トランジスタ４と定電圧ダイオード５とから成る複合保護素子３と、第１及び第２の主端子６，７と、制御端子８とを有している。
【００１０】
発光ダイオード２のアノードは第１の主端子６に接続され、カソードは第２の主端子７に接続されている。
複合保護素子３に含まれているシリコンから成るＮＰＮ型トランジスタ４は発光ダイオード２に対して並列に接続されている。即ちトランジスタ４のコレクタは第１の主端子６に接続され、このエミッタは第２の主端子７に接続され、ベースは制御端子８に接続されている。また、トランジスタ４は発光ダイオード２に熱結合されている。このトランジスタ４が導通を開始するためのベース・エミッタ間電圧ＶＢＥ即ち、ベース電流が流れ始めるために要求されるベース・エミッタ間電圧ＶＢＥは２５℃（室温）で約０．７Ｖである。また、オン開始時のベース・エミッタ間電圧ＶＢＥは約‐２ｍＶ／℃の負の温度係数を有している。本実施形態では負の温度係数を有するトランジスタ４が感熱素子として利用され、発光ダイオード２の過熱を防いでいる。
【００１１】
電子回路素子としての発光ダイオード２を駆動する時には第１の主端子６を電流制限用抵抗９を介して直流電源端子１０に接続し、第２の主端子７をグランド端子１１に接続する。また、トランジスタ４を発光ダイオード２の熱破壊防止用保護素子として使用する時には、トランジスタ４のベース即ち制御端子８にバイアス回路１２を接続する。バイアス回路１２は、直流電源端子１０とグランド端子１１との間に接続された第１及び第２の抵抗１３，１４から成り、第１及び第２の抵抗１３，１４の相互接続点が制御端子８に接続されている。本実施例においてはバイアス回路１２によってトランジスタ４のベース・エミッタ間に与える固定バイアス電圧Ｖｂは０．５５Ｖに設定されているものとする。このバイアス電圧Ｖｂ＝０．５５Ｖを得るための抵抗１３の値Ｒ１の決定は次式に従って行う。
Ｖｂ＝Ｖｃｃ Ｒ２／（Ｒ１＋Ｒ２）
Ｒ１＝Ｒ２｛（Ｖｃｃ／Ｖｂ）−１｝
なお、抵抗１４として既値の抵抗Ｒ２を使用する。
このバイアス電圧Ｖｂは、発光ダイオード２の通常の温度範囲ではトランジスタ４がオンにならないが、発光ダイオード２の温度が通常温度範囲よりも高い異常温度（本実施例では１００℃以上）になるとオンになるように決定される。この実施形態では、発光ダイオード２の保護開始温度が１００℃である。もし、発光ダイオード２及びトランジスタ４の温度が１００℃になると、トランジスタ４が導通を開始するために要求されるベース・エミッタ間電圧ＶＢＥが２５℃の時の値（０．７Ｖ）よりも０．１５Ｖ下がり、０．５５Ｖとなる。１００℃の時には、バイアス回路１２からは０．５５Ｖのバイアス電圧Ｖｂがトランジスタ４に印加されているので、トランジスタ４がオンになり、発光ダイオード２のバイパス即ち短絡回路が形成され、発光ダイオード２の電流が遮断又は抑制され、発光ダイオード２の温度上昇が制限される。即ち、トランジスタ４がオンになると、抵抗９を通る電流がトランジスタ４に分流し、発光ダイオード２の電流が低下する。トランジスタ４はシリコンから成り、ＧａＮ系発光ダイオード２よりは熱破壊しにくい。また、トランジスタ４は発光ダイオード２の許容最大電流と同一の値の電流が流れても破壊しないように形成されている。なお、好ましくは、トランジスタ４の許容最大コレクタ電流の値を発光ダイオード２の許容最大電流の２倍以上に決定する。
【００１２】
定電圧ダイオード５は、発光ダイオード２の定格電圧では導通しないが、定格電圧と破壊する可能性のある最低破壊電圧との間の所定電圧で導通し、発光ダイオード２に一定電圧以上の電圧が印加されることを防ぐように形成されている。これにより、静電気等の高いサージ電圧が第１及び第２の主端子６，７間に印加された時に定電圧ダイオード５が導通し、発光ダイオード２の両端子間電圧が制限される。
【００１３】
図２〜図５は発光装置１の各部の構成を詳しく示すものである。図２に概略的に示すように発光ダイオ−ド２は複合保護素子３の上に配置されている。発光ダイオ−ド２は図２及び図３から明らかなように、ＧａＮ系半導体発光ダイオ−ドの本体部２０とアノ−ド側のマイクロバンプ電極２１とカソ−ド側マイクロバンプ電極２２とから成るフリップチップであって、バンプ電極２１、２２によって複合保護素子３の上面に機械的及び電気的に結合されている。なお、発光ダイオ−ド２からは主として上方に光が放射される。
【００１４】
複合保護素子３は、トランジスタ４と定電圧ダイオ−ド５とを図３〜図５に示すように同一のシリコン半導体基体２３に形成したものである。図２〜図５に示すように複合保護素子３の一方の主面には第１の主電極２４と第２主電極２５の表面側部分２５ａと制御電極２６が設けられ、他方の主面に第２の主電極２５の裏面部分２５ｂが設けられている。図２に概略的に示すように第１の主電極２４はワイヤから成る第１の導体２７によって柱状リ−ドから成る第１の主端子６に接続されている。第２の主電極２５の裏面側部分２５ｂは第２の主端子７に一体的に形成された光反射凹部を有するヘッダ部７ａにＡｇペ−スト等の導電性接合材２８によって電気的及び機械的に結合されている。制御電極２６はワイヤから成る第２の導体２９によって柱状リ−ドから成る制御端子８に接続されている。発光ダイオ−ド２、複合保護素子３、端子６、７、８の一部、導体２７、２９は光透過性樹脂３０によって被覆されている。
【００１５】
発光ダイオ−ド２は複合保護素子３の上にバンプ電極２１、２２を介して結合されているので、発光ダイオ−ド２の熱は複合保護素子３の中のトランジスタ４に伝達される。従って、トランジスタ４は発光ダイオ−ド２の熱結合された状態にあり、発光ダイオ−ド２の温度変化に追従してトランジスタ４の温度も変化する。トランジスタ４を含む複合保護素子３は第２の主端子７のヘッダ部７ａに直接的に結合されているので比較的放熱性が良いが、発光ダイオ−ド２は複合保護素子３を介してヘッダ部７ａに結合されているので、ヘッダ部７ａに直接に結合する場合に比べて放熱性が悪い。しかし、この放熱性の悪さに起因する弊害がトランジスタ４によって電気回路的に除去されている。
【００１６】
複合保護素子３を構成するシリコン半導体基体２３には、図３〜図５に示すようにＰ型基板領域３１、Ｎ＋型埋め込み領域３２、Ｎ型シリコンのエピタキシヤル成長領域から成り且つ領域３２よりも低不純物濃度のＮ−型領域３３、Ｐ型ベ−ス領域３４、Ｎ型エミッタ領域３５、領域３３よりも不純物濃度が高いＮ＋型コレクタ接続領域３６、領域３４よりも不純物濃度が高いＰ＋型表裏接続領域３７が設けられている。
【００１７】
半導体基体２３のＰ型基板領域３１は基体２３の下面の全体に露出するように配置されている。Ｎ＋型埋め込み領域３２は基板領域３１とＮ−型領域３３との間に配置されている。Ｐ型ベ−ス領域３４はＮ−型領域３３の中に島状に形成されている。Ｎ型エミッタ領域３５はベ−ス領域３４の中に島状に形成されている。Ｎ＋型のコレクタ接続領域３６は埋め込み領域３２に対向するようにＮ−型領域３３の中に島状に形成されている。低抵抗の表裏接続領域３７は第２の主電極２５の表面側部分２５ａと裏面側部分２５ｂとを電気的に接続するように配置されている。
【００１８】
半導体基体２３の表面側の第１の主電極２４は、Ｎ＋型のコレクタ接続領域３６にオ−ミック接触している。第２の主電極２５の表面側部分２５ａはＰ＋型表裏接続領域３７、エミッタ領域３５の上に設けられている。制御電極２６はＰ型ベ−ス領域３４の上に配置されている。図３では省略されているが、半導体基体２３の表面には絶縁膜３８から形成され、ここに形成された開口を介して第１の主電極２５の表面側部分２５ａ及び制御電極２６が半導体基体２３の所定領域に接続されている。また、第１の主電極２４は図５に示すように絶縁膜２８の上に延在し、発光ダイオ−ド２の接続に利用されている。図３で破線で示されている発光ダイオ−ド２０は、第１の主電極２４と第２の主電極２５の表面側部分２５ａに対向配置され、図５に示すようにアノ−ド側のバンプ電極２１が第１の主電極２４に結合され、カソ−ド側のバンプ電極２２が第２の主電極２５の表面側部分２５ａに結合されている。尚、電極部分を斜線で示している。
【００１９】
図４に示すように順次に重なるように配置されているＮ型エミッタ領域３５とＰ型ベ−ス領域３４とＮ−型領域３３とＮ＋型埋め込み領域３２とによってＮＰＮ型トランジスタ４が構成され、コレクタとして機能するＮ＋型埋め込み領域３２がＮ−型領域３３及びＮ＋型領域３６を介して第１の主電極２４に接続されている。第１の主電極２４の一部はトランジスタ４のコレクタ電極として機能し、第２の主電極２５の表面部分２５ａの一部はトランジスタ４のエミッタ電極として機能し、制御電極２６はトランジスタ４のベ−ス電極として機能している。
【００２０】
Ｎ＋型領域３６の一部は、Ｐ＋型表裏接続領域３７の一部と重なっている。従って、Ｎ＋型領域３６が定電圧ダイオ−ド５のカソ−ド領域として機能し、Ｐ＋型表裏接続領域３７が定電圧ダイオ−ド５のアノ−ド領域として機能している。また、第１の主電極２４の一部は定電圧ダイオ−ド５のカソ−ド電極として機能し、第２の主電極２５の裏面側領域２５ｂは定電圧ダイオ−ド５のアノ−ド電極として機能している。
【００２１】
上述から明らかなように本実施形態は次の効果を有する。
（１） 発光ダイオ−ド２の温度が所定温度以上になると、トランジスタ４がオンになり、発光ダイオ−ド２の電流が低減又は遮断され、発光ダイオ−ド２の劣化又は熱破壊が防止される。
（２） 定電圧ダイオ−ド５を発光ダイオ−ド２に並列に接続したので、過電圧時に定電圧ダイオ−ド５が導通して発光ダイオ−ド２の電圧がクランプされ、過電圧による劣化又は破壊が防止される。
（３） 熱破壊防止用トランジスタ４と過電圧防止用定電圧ダイオ−ド５とを同一の半導体基体３に設けて複合保護素子としたので、この小型化及び低コスト化を達成することができる。
（４） トランジスタ４と定電圧ダイオ−ド５とから成る複合保護素子の上に発光ダイオ−ド２を配置したので、これ等の組立体を小型化することができる。
【００２２】
【第２の実施形態】
次に、図６及び図７を参照して第２の実施形態の発光装置１ａを説明する。但し、図６及び図７、更に後述する図８において図１〜図５と実質的に同一の部分には同一の符号を付し、その説明を省略する。
【００２３】
図６及び図７に示す発光装置１ａは、回路基板に対して表面実装方式で取り付けるための絶縁性支持基板４０を設け、この他は図２の発光装置１と実質的に同一に形成したものである。基板４０には、図２の端子６、７、８に対応する導体層から成る端子６ａ、７ａ、８ａが設けられている。図６〜図７の発光ダイオ−ド２及び複合保護素子３は図２〜図５で同一符号で示すものと同様に形成されている。図６及び図７において第２の主電極の裏面側部分２５ｂは導電性接合材２８ａによって基板４０の第２の主端子７ａに電気的及び機械的に結合されている。第１の主電極２４は導体２７によって第１の主端子６ａに接続され、制御端子２６は導体２９によって制御端子８ａに接続されている。基板４０の上面には発光ダイオード２及び複合保護素子３を覆うように光透過性樹脂３０が設けられている。
【００２４】
第２の実施形態の発光装置は、第１の実施形態と同一の効果を有し、更に表面実装できるという効果も有する。
【００２５】
【第３の実施形態】
図８に示す第３の実施形態の発光装置１ｂは、図１と同様に互いに並列に接続された発光ダイオ−ド２と定電圧ダイオ−ド５を有する他に、感熱素子４ａを有する。感熱素子４ａは発光ダイオ−ド２に熱結合されたサ−ミスタであって、例えば約１００℃以上の異常温度で抵抗値が大幅に低下するように形成されている。従って、図８の実施形態によっても発光ダイオ−ドの熱破壊及び過電圧破壊を防止することができる。
【００２６】
【変形例】
本発明は上述の実施形態に限定されるものでなく、例えば、次の変形が可能なものである。
（１） バイアス回路１２を発光ダイオ−ド２と別の電源に接続することができる。
（２） シリコン基板の上にＧａＮ系半導体層を成長させ、ＧａＮ系半導体層によって発光ダイオ−ド２を形成し、シリコン基板にトランジスタ４及び定電圧ダイオ−ド５を設けることができる。
（３） 複合保護素子３を発光ダイオ−ド２以外の電子回路素子に並列に接続し、電子回路素子の熱破壊及び過電圧破壊を防止することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態の発光装置をバイアス回路及び駆動回路を伴って示す回路図である。
【図２】図１の発光装置を概略的に示す一部切断正面図である。
【図３】図２の複合保護素子を、絶縁膜を省いて示す平面図である。
【図４】図３のＡ−Ａ線を示す断面図である。
【図５】図３のＢ−Ｂ線を示す断面図である。
【図６】第２の実施形態の発光装置を示す正面図である。
【図７】図６の発光装置を被覆樹脂を省いて示す平面図である。
【図８】第３の実施形態の発光装置を示す回路図である。
【符号の説明】
１ 発光装置
２ 発光ダイオ−ド
３ 複合保護素子
４ 過熱防止用トランジスタ
５ 過電圧防止用定電圧ダイオ−ド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor light emitting device with a built-in protection device.
[0002]
[Prior art]
In recent years, blue semiconductor light-emitting elements, that is, light-emitting diodes using gallium nitride (GaN) -based semiconductors have attracted attention. Since this light emitting diode is destroyed by a surge voltage of about several tens of volts, for example, as disclosed in Japanese Patent Laid-Open No. 11-12036, a zener diode (constant voltage diode) for preventing overvoltage is connected in parallel to the light emitting diode. Is done. Accordingly, when an overvoltage due to static electricity or the like is applied to the light emitting diode, the Zener diode is turned on to protect the light emitting diode from the overvoltage.
[0003]
[Problems to be solved by the invention]
By the way, when forming an assembly of a protection element such as a Zener diode and a light emitting diode, the light emitting diode is coupled to the protection element by a microbump electrode or the like. For this reason, a protective element is interposed in the heat dissipation path of the light emitting diode, and the protective element reduces the heat dissipation of the light emitting diode. If a current of the same value as the current flowing through the light emitting diode without a protective element is passed through the light emitting diode with the protective element, the temperature of the light emitting diode becomes higher than the allowable range, and the light emitting diode is deteriorated or damaged. May occur. Although the case where the light emitting diode and the protective element are assembled integrally has been described, the thermal destruction of the semiconductor light emitting element such as the light emitting diode becomes a problem even when the protective element does not disturb the heat dissipation of the light emitting diode.
Also, there are times when it is necessary to prevent both overvoltage breakdown and thermal breakdown in circuit elements other than light emitting diodes.
[0004]
Accordingly, a first object of the present invention is to provide a semiconductor light emitting device capable of preventing thermal destruction of a semiconductor light emitting element.
A second object of the present invention is to provide a semiconductor light-emitting device which can prevent both thermal destruction and an overvoltage breakdown of the semiconductor light emitting element.
[0005]
[Means for Solving the Problems]
In order to solve the above problems and achieve the above object, the present invention provides a semiconductor light emitting device and an ON state that is connected in parallel to the semiconductor light emitting device and the temperature of the semiconductor light emitting device is higher than a predetermined temperature. Or a protective element having a characteristic of decreasing resistance value, and an overvoltage preventing constant voltage diode connected in parallel to the semiconductor light emitting element, and the protective element is a base required to start conduction. The transistor has a negative temperature coefficient between the emitters, the transistor and the constant voltage diode are formed on the same semiconductor substrate, and the semiconductor light emitting element is disposed on the semiconductor substrate. The present invention relates to a featured semiconductor light emitting device.
[0006]
In addition, as shown in Claim 2, it is desirable to arrange | position a light emitting element on a protective element.
[0007]
【The invention's effect】
According to the onset bright, the temperature of the semiconductor light emitting element is higher than a predetermined temperature, the protective element is turned on or the low-resistance value, serves as a bypass of the semiconductor light emitting element, current of the semiconductor light-emitting element is blocked or suppressed, The temperature rise of the semiconductor light emitting element is suppressed, and this deterioration or destruction is prevented.
Moreover, both thermal destruction prevention and overvoltage prevention can be achieved.
Further , according to the invention of claim 2, the light emitting device capable of preventing both thermal breakdown and overvoltage breakdown can be reduced in size and cost. Can be provided.
[0008]
Embodiment
Next, an embodiment of the present invention will be described with reference to FIGS.
[0009]
[First Embodiment]
A semiconductor light emitting device 1 of the first embodiment shown in FIGS. 1 to 5 includes a gallium nitride (GaN) light emitting diode 2 as a light emitting element, a composite protective element 3 including a transistor 4 and a constant voltage diode 5, It has first and second main terminals 6 and 7 and a control terminal 8.
[0010]
The anode of the light emitting diode 2 is connected to the first main terminal 6, and the cathode is connected to the second main terminal 7.
The NPN transistor 4 made of silicon contained in the composite protection element 3 is connected in parallel to the light emitting diode 2. That is, the collector of the transistor 4 is connected to the first main terminal 6, the emitter is connected to the second main terminal 7, and the base is connected to the control terminal 8. Transistor 4 is thermally coupled to light emitting diode 2. The transistor 4 is the voltage V BE between the base and emitter for initiating conduction That is, the voltage V BE between the base and emitter, which is required for the base current starts to flow is about 0.7V at 25 ° C. (room temperature). Further, the base-emitter voltage V BE at the start of the on-state has a negative temperature coefficient of about −2 mV / ° C. In this embodiment, the transistor 4 having a negative temperature coefficient is used as a heat sensitive element, and the light emitting diode 2 is prevented from being overheated.
[0011]
When driving the light emitting diode 2 as an electronic circuit element, the first main terminal 6 is connected to the DC power supply terminal 10 via the current limiting resistor 9, and the second main terminal 7 is connected to the ground terminal 11. When the transistor 4 is used as a protection element for preventing thermal destruction of the light emitting diode 2, a bias circuit 12 is connected to the base of the transistor 4, that is, the control terminal 8. The bias circuit 12 includes first and second resistors 13 and 14 connected between the DC power supply terminal 10 and the ground terminal 11, and an interconnection point between the first and second resistors 13 and 14 is a control terminal. 8 is connected. In this embodiment, it is assumed that the fixed bias voltage Vb applied between the base and emitter of the transistor 4 by the bias circuit 12 is set to 0.55V. The value R1 of the resistor 13 for obtaining the bias voltage Vb = 0.55V is determined according to the following equation.
Vb = Vcc R2 / (R1 + R2)
R1 = R2 {(Vcc / Vb) -1}
As the resistor 14, an existing resistor R2 is used.
The bias voltage Vb does not turn on the transistor 4 in the normal temperature range of the light-emitting diode 2, but turns on when the temperature of the light-emitting diode 2 reaches an abnormal temperature higher than the normal temperature range (100 ° C. or higher in this embodiment). To be determined. In this embodiment, the protection start temperature of the light emitting diode 2 is 100 ° C. If the temperature of the light emitting diode 2 and the transistor 4 reaches 100 ° C., the base-emitter voltage V BE required for the transistor 4 to start conducting becomes 0 than the value (0.7 V) when the temperature is 25 ° C. .15V drop to 0.55V. At 100 ° C., a bias voltage Vb of 0.55 V is applied from the bias circuit 12 to the transistor 4, so that the transistor 4 is turned on, and a bypass or short circuit of the light emitting diode 2 is formed. The current is interrupted or suppressed, and the temperature rise of the light emitting diode 2 is limited. That is, when the transistor 4 is turned on, the current passing through the resistor 9 is shunted to the transistor 4 and the current of the light emitting diode 2 is decreased. The transistor 4 is made of silicon and is less likely to be thermally destroyed than the GaN-based light emitting diode 2. The transistor 4 is formed so as not to be destroyed even when a current having the same value as the maximum allowable current of the light emitting diode 2 flows. Preferably, the value of the maximum allowable collector current of the transistor 4 is determined to be at least twice the maximum allowable current of the light emitting diode 2.
[0012]
The constant voltage diode 5 does not conduct at the rated voltage of the light emitting diode 2, but conducts at a predetermined voltage between the rated voltage and the lowest breakdown voltage that may be destroyed, and a voltage higher than a certain voltage is applied to the light emitting diode 2. It is formed to prevent it. Thereby, when a high surge voltage such as static electricity is applied between the first and second main terminals 6 and 7, the constant voltage diode 5 becomes conductive, and the voltage between both terminals of the light emitting diode 2 is limited.
[0013]
2 to 5 show the configuration of each part of the light emitting device 1 in detail. As schematically shown in FIG. 2, the light emitting diode 2 is disposed on the composite protective element 3. As shown in FIGS. 2 and 3, the light-emitting diode 2 comprises a main body portion 20, an anode-side microbump electrode 21, and a cathode-side microbump electrode 22 of a GaN-based semiconductor light-emitting diode. The flip chip is mechanically and electrically coupled to the upper surface of the composite protective element 3 by bump electrodes 21 and 22. It should be noted that light is mainly emitted upward from the light emitting diode 2.
[0014]
The composite protective element 3 is formed by forming a transistor 4 and a constant voltage diode 5 on the same silicon semiconductor substrate 23 as shown in FIGS. As shown in FIGS. 2-5, the 1st main electrode 24, the surface side part 25a of the 2nd main electrode 25, and the control electrode 26 are provided in one main surface of the composite protective element 3, and the other main surface is provided with it. A back surface portion 25 b of the second main electrode 25 is provided. As schematically shown in FIG. 2, the first main electrode 24 is connected to the first main terminal 6 made of a columnar lead by a first conductor 27 made of a wire. The back surface portion 25b of the second main electrode 25 is electrically and mechanically connected to a header portion 7a having a light reflecting recess formed integrally with the second main terminal 7 by a conductive bonding material 28 such as Ag paste. Combined. The control electrode 26 is connected to the control terminal 8 made of a columnar lead by a second conductor 29 made of a wire. The light emitting diode 2, the composite protective element 3, a part of the terminals 6, 7, 8 and the conductors 27, 29 are covered with a light transmissive resin 30.
[0015]
Since the light emitting diode 2 is coupled to the composite protective element 3 via the bump electrodes 21 and 22, the heat of the light emitting diode 2 is transmitted to the transistor 4 in the composite protective element 3. Therefore, the transistor 4 is in a state where the light emitting diode 2 is thermally coupled, and the temperature of the transistor 4 changes following the temperature change of the light emitting diode 2. Since the composite protection element 3 including the transistor 4 is directly coupled to the header portion 7a of the second main terminal 7, the heat dissipation is relatively good. However, the light emitting diode 2 is connected to the header via the composite protection element 3. Since it is coupled to the portion 7a, heat dissipation is poor as compared with the case where it is directly coupled to the header portion 7a. However, the adverse effect due to the poor heat dissipation is eliminated by the transistor 4 in an electric circuit.
[0016]
As shown in FIGS. 3 to 5, the silicon semiconductor substrate 23 constituting the composite protective element 3 is composed of a P-type substrate region 31, an N + -type buried region 32, an N-type silicon epitaxial growth region, and from the region 32. even a low impurity concentration N - type region 33, P-type base - source region 34, N-type emitter region 35, a higher impurity concentration than region 33 N + -type collector connection region 36, impurity concentration than region 34 higher P A + -type front / back connection region 37 is provided.
[0017]
The P-type substrate region 31 of the semiconductor substrate 23 is disposed so as to be exposed on the entire lower surface of the substrate 23. The N + type buried region 32 is disposed between the substrate region 31 and the N − type region 33. The P-type base region 34 is formed in an island shape in the N − -type region 33. The N-type emitter region 35 is formed in an island shape in the base region 34. The N + -type collector connection region 36 is formed in an island shape in the N − -type region 33 so as to face the buried region 32. The low resistance front / back connection region 37 is arranged so as to electrically connect the front surface side portion 25a and the back surface side portion 25b of the second main electrode 25.
[0018]
The first main electrode 24 on the surface side of the semiconductor substrate 23 is in ohmic contact with the N + -type collector connection region 36. The surface side portion 25 a of the second main electrode 25 is provided on the P + type front / back connection region 37 and the emitter region 35. The control electrode 26 is disposed on the P-type base region 34. Although omitted in FIG. 3, an insulating film 38 is formed on the surface of the semiconductor substrate 23, and the surface side portion 25 a of the first main electrode 25 and the control electrode 26 are connected to the semiconductor substrate through the openings formed therein. It is connected to 23 predetermined areas. Further, as shown in FIG. 5, the first main electrode 24 extends on the insulating film 28 and is used for connection of the light emitting diode 2. The light-emitting diode 20 indicated by a broken line in FIG. 3 is disposed opposite to the surface side portion 25a of the first main electrode 24 and the second main electrode 25, and as shown in FIG. The bump electrode 21 is coupled to the first main electrode 24, and the cathode-side bump electrode 22 is coupled to the surface side portion 25 a of the second main electrode 25. The electrode portion is indicated by hatching.
[0019]
As shown in FIG. 4, the NPN-type transistor 4 is constituted by the N-type emitter region 35, the P-type base region 34, the N - type region 33, and the N + type buried region 32 that are arranged so as to overlap one another. The N + type buried region 32 functioning as a collector is connected to the first main electrode 24 through the N − type region 33 and the N + type region 36. A part of the first main electrode 24 functions as the collector electrode of the transistor 4, a part of the surface portion 25 a of the second main electrode 25 functions as the emitter electrode of the transistor 4, and the control electrode 26 is the base electrode of the transistor 4. -Functions as a contact electrode.
[0020]
A part of the N + type region 36 overlaps a part of the P + type front / back connection region 37. Therefore, the N + type region 36 functions as a cathode region of the constant voltage diode 5, and the P + type front / back connection region 37 functions as an anode region of the constant voltage diode 5. A part of the first main electrode 24 functions as a cathode electrode of the constant voltage diode 5, and a back surface side region 25 b of the second main electrode 25 is an anode electrode of the constant voltage diode 5. Is functioning as
[0021]
As apparent from the above, this embodiment has the following effects.
(1) When the temperature of the light emitting diode 2 exceeds a predetermined temperature, the transistor 4 is turned on, the current of the light emitting diode 2 is reduced or cut off, and the deterioration or thermal destruction of the light emitting diode 2 is prevented. The
(2) Since the constant voltage diode 5 is connected to the light emitting diode 2 in parallel, the constant voltage diode 5 becomes conductive when overvoltage occurs, and the voltage of the light emitting diode 2 is clamped, causing deterioration or destruction due to overvoltage. Is prevented.
(3) Since the thermal breakdown preventing transistor 4 and the overvoltage preventing constant voltage diode 5 are provided on the same semiconductor substrate 3 to form a composite protective element, this reduction in size and cost can be achieved.
(4) Since the light emitting diode 2 is disposed on the composite protective element composed of the transistor 4 and the constant voltage diode 5, these assemblies can be miniaturized.
[0022]
[Second Embodiment]
Next, the light emitting device 1a of the second embodiment will be described with reference to FIGS. However, in FIGS. 6 and 7, and in FIG. 8 described later, substantially the same parts as in FIGS. 1 to 5 are denoted by the same reference numerals, and the description thereof is omitted.
[0023]
The light-emitting device 1a shown in FIGS. 6 and 7 is provided with an insulating support substrate 40 for mounting on a circuit board by a surface mounting method, and the others are formed substantially the same as the light-emitting device 1 of FIG. It is. The substrate 40 is provided with terminals 6a, 7a, 8a made of a conductor layer corresponding to the terminals 6, 7, 8 in FIG. The light-emitting diode 2 and the composite protective element 3 shown in FIGS. 6 to 7 are formed in the same manner as shown by the same reference numerals in FIGS. 6 and 7, the back side portion 25b of the second main electrode is electrically and mechanically coupled to the second main terminal 7a of the substrate 40 by a conductive bonding material 28a. The first main electrode 24 is connected to the first main terminal 6 a by a conductor 27, and the control terminal 26 is connected to the control terminal 8 a by a conductor 29. A light transmissive resin 30 is provided on the upper surface of the substrate 40 so as to cover the light emitting diode 2 and the composite protective element 3.
[0024]
The light emitting device of the second embodiment has the same effect as that of the first embodiment, and also has the effect that it can be surface-mounted.
[0025]
[Third Embodiment]
A light-emitting device 1b according to the third embodiment shown in FIG. 8 includes a light-sensitive diode 4a in addition to the light-emitting diode 2 and the constant-voltage diode 5 connected in parallel to each other as in FIG. The thermosensitive element 4a is a thermistor thermally coupled to the light emitting diode 2, and is formed so that the resistance value is significantly reduced at an abnormal temperature of, for example, about 100 ° C. or more. Therefore, the embodiment of FIG. 8 can also prevent the light-emitting diode from being destroyed by heat and overvoltage.
[0026]
[Modification]
The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.
(1) The bias circuit 12 can be connected to a power source different from that of the light emitting diode 2.
(2) A GaN-based semiconductor layer is grown on a silicon substrate, the light-emitting diode 2 is formed by the GaN-based semiconductor layer, and the transistor 4 and the constant voltage diode 5 can be provided on the silicon substrate.
(3) The composite protective element 3 can be connected in parallel to an electronic circuit element other than the light emitting diode 2 to prevent thermal breakdown and overvoltage breakdown of the electronic circuit element.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a light emitting device according to a first embodiment of the present invention with a bias circuit and a drive circuit.
FIG. 2 is a partially cut front view schematically showing the light emitting device of FIG.
3 is a plan view showing the composite protective element of FIG. 2 without an insulating film.
4 is a cross-sectional view taken along line AA in FIG.
5 is a cross-sectional view taken along line BB of FIG.
FIG. 6 is a front view showing a light emitting device according to a second embodiment.
7 is a plan view showing the light emitting device of FIG. 6 with the coating resin omitted. FIG.
FIG. 8 is a circuit diagram illustrating a light emitting device according to a third embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Light-emitting device 2 Light-emitting diode 3 Composite protective element 4 Overheat prevention transistor 5 Overvoltage prevention constant voltage diode

Claims (2)

半導体発光素子と、前記半導体発光素子に並列に接続され且つ前記半導体発光素子の温度が所定温度よりも高くなった時にオン状態になるか又は抵抗値が低下する特性を有している保護素子と、前記半導体発光素子に並列に接続された過電圧防止用定電圧ダイオードとを有し、前記保護素子は導通開始に要求されるベース・エミッタ間電圧が負の温度係数を有するトランジスタであり、前記トランジスタと前記定電圧ダイオードは同一の半導体基体に形成されており、前記半導体発光素子は前記半導体基体の上に配置されていることを特徴とする半導体発光装置。A semiconductor light emitting element, and a protective element connected in parallel to the semiconductor light emitting element and having a characteristic of being turned on or having a reduced resistance value when the temperature of the semiconductor light emitting element is higher than a predetermined temperature; An overvoltage-preventing constant-voltage diode connected in parallel to the semiconductor light-emitting element, and the protection element is a transistor having a negative temperature coefficient for a base-emitter voltage required to start conduction, And the constant voltage diode are formed on the same semiconductor substrate, and the semiconductor light emitting element is disposed on the semiconductor substrate . 前記半導体発光素子は前記保護素子の上に配置されていることを特徴とする請求項１記載の半導体発光装置。The semiconductor light-emitting device according to claim 1, wherein the semiconductor light-emitting element is disposed on the protection element.
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