JPH1167775A - Formation of semiconductor chip connecting bump - Google Patents

Formation of semiconductor chip connecting bump

Info

Publication number
JPH1167775A
JPH1167775A JP9224079A JP22407997A JPH1167775A JP H1167775 A JPH1167775 A JP H1167775A JP 9224079 A JP9224079 A JP 9224079A JP 22407997 A JP22407997 A JP 22407997A JP H1167775 A JPH1167775 A JP H1167775A
Authority
JP
Japan
Prior art keywords
semiconductor chip
pad
bump
gold
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9224079A
Other languages
Japanese (ja)
Other versions
JP3335562B2 (en
Inventor
Naoki Ishikawa
直樹 石川
Hidehiko Kira
秀彦 吉良
Kenji Koyae
健二 小八重
Norio Kainuma
則夫 海沼
Satoru Emoto
哲 江本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22407997A priority Critical patent/JP3335562B2/en
Publication of JPH1167775A publication Critical patent/JPH1167775A/en
Application granted granted Critical
Publication of JP3335562B2 publication Critical patent/JP3335562B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To form a bump reliably even if there is a dent such as a probe mark on the pad, which is a component constituting a semiconductor chip, by forming a soft gold ball while adjusting radiation energy. SOLUTION: When a probe mark 24 is present on a pad 21, a bump 23 is formed by bonding to the pad 21 an initial ball that is made to be soft in advance. The soft initial ball can be prepared by adjusting the magnitude of radiating current to be applied between a gold wire and a discharge electrode, and the discharge time. By preparing the initial ball that is soft, the plasticity of the initial ball is increased, which in turn allows the initial ball to reach the bottom of the probe mark 24 on the pad 21 at the time of its bonding. As a result, the initial ball can be alloyed, and thus a reliable bump can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体チップ接続バ
ンプ形成方法に関する。詳しくは、半導体チップ部品の
電極に残るテストプローブ痕によるバンプ形成時の不具
合を防止可能とした半導体チップ接続バンプ形成方法に
関する。The present invention relates to a method for forming bumps for connecting semiconductor chips. More specifically, the present invention relates to a semiconductor chip connecting bump forming method capable of preventing a defect at the time of forming a bump due to a test probe mark remaining on an electrode of a semiconductor chip component.

【０００２】[0002]

【従来の技術】半導体チップ部品（ベアチップ）を基板
上に直接実装するＣＯＢ（ＣＨＩＰＯＮ ＢＯＡＲＤ）
技術には目的や用途に応じて種々の方式が提案されてお
り、その一つの方式としてフリップチップ実装方式があ
る。この実装方法は、半導体チップ部品と基板との間を
ワイヤを使用することなく、半導体チップ部品を直接基
板に搭載するものであり、ワイヤレスボンディング実装
方式とも呼ばれている。2. Description of the Related Art COB (CHIPON BOARD) for mounting semiconductor chip parts (bare chips) directly on a substrate
Various methods have been proposed for the technology according to the purpose and application. One of the methods is a flip-chip mounting method. This mounting method directly mounts a semiconductor chip component on a substrate without using wires between the semiconductor chip component and the substrate, and is also called a wireless bonding mounting method.

【０００３】従来のフリップチップ実装方式の実装工程
を図７および図８を用いて説明すると、先ず、図７
（ａ）に示すように、ボンディングツールのキャピラリ
１の中を通した金線（金ワイヤ）２の先端と放電用電極
３との間に高電圧を印加して放電させ、その放電エネル
ギにより図７（ｂ）の如く金線２の先端を溶融させ、そ
の表面張力により金ボール（この金ボールをイニシャル
ボールという。）４を形成する。The mounting process of the conventional flip-chip mounting method will be described with reference to FIGS. 7 and 8. First, FIG.
As shown in FIG. 1A, a high voltage is applied between a tip of a gold wire (gold wire) 2 passing through a capillary 1 of a bonding tool and a discharge electrode 3 to cause a discharge. As shown in FIG. 7B, the tip of the gold wire 2 is melted, and a gold ball (this gold ball is referred to as an initial ball) 4 is formed by the surface tension.

【０００４】次に、図７（ｃ）に示すように、半導体チ
ップ部品５の表面に形成されている電極パッド６に前記
キャピラリ１により金ボール４を押圧し、同時に超音波
振動を与えて図７（ｄ）の如く金ボール４をパッド６に
圧着する。このとき、キャピラリ１の先端内面に形成さ
れた凹型により金ボール４を塑性変形させて図７（ｅ）
に示すような大径部と小径部よりなる２段形状のバンプ
７を形成する。Next, as shown in FIG. 7 (c), the gold ball 4 is pressed by the capillary 1 against the electrode pad 6 formed on the surface of the semiconductor chip component 5, and at the same time, ultrasonic vibration is applied. The gold ball 4 is pressed against the pad 6 as shown in FIG. At this time, the gold ball 4 is plastically deformed by the concave mold formed on the inner surface of the tip of the capillary 1 and FIG.
Then, a two-stage bump 7 composed of a large diameter portion and a small diameter portion as shown in FIG.

【０００５】次いで、図７（ｅ）の如く、金線２をクラ
ンパー８によりクランプして上方に引張りバンプ７の上
方で金線２を切断する。このようにして各パッド６にバ
ンプ７を形成したのち、各バンプ７の高さにバラツキが
あるため、図７（ｆ）に示すように、半導体チップ部品
５を裏返し、平面度の良いガラス板９に押圧して各バン
プ７の先端を塑性変形させて高さを揃える。[0007] Next, as shown in FIG. 7 (e), the gold wire 2 is clamped by a clamper 8 and pulled upward to cut the gold wire 2 above the bump 7. After the bumps 7 are formed on the pads 6 in this manner, since the heights of the bumps 7 vary, as shown in FIG. 7F, the semiconductor chip component 5 is turned over and a glass plate having good flatness is obtained. 9, the tip of each bump 7 is plastically deformed to make the height uniform.

【０００６】次いで、図８（ｇ）の如く、平板上に数ミ
クロンの厚さに塗布した導電性ペースト１０にバンプ７
を押し付けて図８（ｈ）の如く、導電性ペースト１０を
バンプ７に転写する。この導電性ペースト１０は基板上
に半導体チップ部品５を実装した時に、バンプ７と基板
のパッドとの電気的な導通をより確実に行うものであ
り、エポキシ樹脂中に銀のフィラーを多数分散したもの
が使用される。Next, as shown in FIG. 8 (g), bumps 7 are applied to a conductive paste 10 applied on a flat plate to a thickness of several microns.
Is pressed to transfer the conductive paste 10 to the bumps 7 as shown in FIG. The conductive paste 10 more reliably performs electrical conduction between the bumps 7 and the pads of the substrate when the semiconductor chip component 5 is mounted on the substrate, and a number of silver fillers are dispersed in the epoxy resin. Things are used.

【０００７】次いで、この導電性ペースト１０を後工程
（樹脂接着工程）で流れ出さないように半硬化させる。
次いで、図８（ｉ）の如く、半導体チップ部品５を搭載
する基板１１の所定位置に熱硬化性の樹脂接着材１２を
盛り、基板１１の表面に形成されている配線パターンに
接続されたパッド１３に半導体チップ部品のバンプ７を
位置合わせして載置し、次いで、図８（ｊ）の如く、半
導体チップ部品５の上から加圧加熱治具１４により加圧
・加熱して樹脂接着材１２を硬化させ完成する。Next, the conductive paste 10 is semi-cured so as not to flow out in a later step (resin bonding step).
Next, as shown in FIG. 8 (i), a thermosetting resin adhesive 12 is applied to a predetermined position of the substrate 11 on which the semiconductor chip component 5 is mounted, and the pads connected to the wiring pattern formed on the surface of the substrate 11 are formed. 8, the bumps 7 of the semiconductor chip component are aligned and placed, and then, as shown in FIG. 12 is cured and completed.

【０００８】この場合、樹脂接着剤１２が半導体チップ
部品５により押し広げられた際、バンプ７に塗布されて
いる導電性ペースト１０と基板１１のパッド１３との間
に入り込まないように、樹脂接着剤１２はバンプ７に塗
布されている導電性ペースト１０が基板１１のパッド１
３に接するまではバンプ７に到達せず、その到達後に半
導体チップ部品５の端部に到達して該半導体チップ部品
５を密封するようになっている。In this case, when the resin adhesive 12 is spread out by the semiconductor chip component 5, the resin adhesive 12 is prevented from entering between the conductive paste 10 applied to the bump 7 and the pad 13 of the substrate 11. The agent 12 is a conductive paste 10 applied to the bumps 7 and the pad 1 on the substrate 11.
The bumps 7 do not reach the bumps 7 until they come into contact with the bumps 3, and then reach the ends of the semiconductor chip components 5 to seal the semiconductor chip components 5.

【０００９】[0009]

【発明が解決しようとする課題】本発明は、上記従来の
半導体チップ部品の基板上への実装方法において、半導
体チップ接続バンプの形成時に、図９（ａ）に示すよう
に、半導体チップ部品の電極であるアルミパッド１３の
表面に圧痕１５が生じていると、バンプ７を形成する
際、図９（ｂ）に示すように、圧痕１５の底部にイニシ
アルボール表面が到達せず、空隙１６を生じ金とアルミ
ニュウムの間の拡散が進行せず、合金層が形成されな
い。そのため、バンプ未着が発生するという問題があ
る。このような圧痕１５が生じる原因の１つとしては、
半導体チップ部品を単体で性能試験する際にパッド１３
にプローブが接触することによるプローブ痕が考えられ
る。The present invention relates to a method for mounting a semiconductor chip component on a substrate according to the above-described conventional method for forming a semiconductor chip connection bump, as shown in FIG. If the indentation 15 is formed on the surface of the aluminum pad 13 as an electrode, when forming the bump 7, the surface of the initial ball does not reach the bottom of the indentation 15 as shown in FIG. The diffusion between the resulting gold and aluminum does not proceed, and no alloy layer is formed. For this reason, there is a problem that bumps are not attached. One of the causes of such an indentation 15 is as follows.
When performing a performance test on a single semiconductor chip component, the pad 13
Probe traces due to contact of the probe with the probe may be considered.

【００１０】本発明は、上記従来の問題点に鑑み、半導
体チップ部品のパッドにプローブ痕等の圧痕があっても
バンプの形成が確実にできる半導体チップ接続バンプ形
成方法を実現することを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to realize a semiconductor chip connecting bump forming method capable of reliably forming a bump even when an indentation such as a probe mark is present on a pad of a semiconductor chip component. I do.

【００１１】[0011]

【課題を解決するための手段】本発明の請求項１の発明
は、金細線を放電エネルギーにより溶融して金ボールを
形成し、該金ボールを半導体チップのパッド上にボンデ
ィングしてバンプを形成する半導体チップ接続バンプ形
成方法において、前記パッド上に圧痕がある場合、前記
放電エネルギーを調節して硬さの柔らかい金ボールを形
成することを特徴とする。この構成を採ることにより金
ボールが柔らかいためプローブ痕の底部に到達し、完全
なボンディングができる。According to a first aspect of the present invention, a gold ball is formed by melting a fine gold wire by discharge energy, and the gold ball is bonded to a pad of a semiconductor chip to form a bump. In the semiconductor chip connection bump forming method described above, when there is an indentation on the pad, the discharge energy is adjusted to form a soft gold ball. With this configuration, the gold ball is soft and reaches the bottom of the probe mark, so that complete bonding can be performed.

【００１２】また、請求項２の発明は、金細線を放電エ
ネルギーにより溶融して金ボールを形成し、該金ボール
を半導体チップのパッド上にボンディングしてバンプを
形成する半導体チップ接続バンプ形成方法において、前
記パッド上に圧痕がある場合、バンプ形成位置を圧痕の
ない部分に選定することを特徴とする。この構成を採る
ことにより金ボールをプローブ痕のない部分にボンディ
ングするため、確実なボンディングができる。According to a second aspect of the present invention, there is provided a semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip. In the above, when there is an indentation on the pad, a bump formation position is selected to a portion having no indentation. With this configuration, the gold ball is bonded to a portion having no probe mark, so that reliable bonding can be performed.

【００１３】また、請求項３の発明は、金細線を放電エ
ネルギーにより溶融して金ボールを形成し、該金ボール
を半導体チップのパッド上にボンディングしてバンプを
形成する半導体チップ接続バンプ形成方法において、前
記パッド上に圧痕がある場合、前記金ボールの下面を粗
面化することを特徴とする。この構成を採ることによ
り、金ボールとパッド２１との接合面積が増え、パッド
２１にプローブ痕があっても確実なボンディングができ
る。According to a third aspect of the present invention, there is provided a semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip. Wherein the lower surface of the gold ball is roughened when there is an indentation on the pad. By employing this configuration, the bonding area between the gold ball and the pad 21 increases, and reliable bonding can be performed even if the pad 21 has a probe mark.

【００１４】また、請求項４の発明は、金細線を放電エ
ネルギーにより溶融して金ボールを形成し、該金ボール
を半導体チップのパッド上にボンディングしてバンプを
形成する半導体チップ接続バンプ形成方法において、前
記パッド上に圧痕がある場合、パッド表面を粗面化する
ことを特徴とする。この構成を採ることにより金ボール
とパッドの接合面積が増えるためパッド２１にプローブ
痕があっても確実なボンディングができる。According to a fourth aspect of the present invention, there is provided a semiconductor chip connecting bump forming method of forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip. Wherein the pad surface is roughened when there is an indentation on the pad. By employing this configuration, the bonding area between the gold ball and the pad increases, so that reliable bonding can be performed even if the pad 21 has a probe mark.

【００１５】また、請求項５の発明は、金細線を放電エ
ネルギーにより溶融して金ボールを形成し、該金ボール
を半導体チップのパッド上にボンディングしてバンプを
形成する半導体チップ接続バンプ形成方法において、前
記パッド上に圧痕がある場合、パッド表面をフラッタリ
ングツールにより平滑化することを特徴とする。この構
成を採ることによりプローブによる圧痕がなくなりバン
プの確実なボンディングができる。According to a fifth aspect of the present invention, there is provided a semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip. Wherein there is an impression on the pad, wherein the pad surface is smoothed by a fluttering tool. By adopting this configuration, there is no indentation due to the probe, and the bonding of the bump can be performed reliably.

【００１６】[0016]

【発明の実施の形態】図１は本発明の半導体チップ接続
バンプ形成方法の第１の実施の形態を説明するための図
である。同図において、２０は半導体チップ、２１は該
半導体チップの上に形成されたアルミニュウムよりなる
パッド、２２は該パッドに接続した配線パターン、２３
はバンプ、２４は性能テスト時に試験機のプローブによ
りパッド上に残されたプローブ痕である。本実施の形態
はこのプローブ痕２４のあるパッド２１にイニシャルボ
ールをボンディングしてバンプ２３を形成する時、該イ
ニシャルボールを予め柔らかく形成してパッド２１にボ
ンディングしバンプ２３を形成するのである。FIG. 1 is a view for explaining a first embodiment of a method of forming bumps for connecting semiconductor chips according to the present invention. In the figure, 20 is a semiconductor chip, 21 is a pad made of aluminum formed on the semiconductor chip, 22 is a wiring pattern connected to the pad, 23
Denotes a bump, and 24 denotes a probe mark left on a pad by a probe of a testing machine during a performance test. In the present embodiment, when an initial ball is bonded to the pad 21 having the probe mark 24 to form the bump 23, the initial ball is softened in advance and the bump 21 is bonded to the pad 21.

【００１７】なお、イニシャルボールを柔らかく形成す
るには、金線と放電電極との間に流す放電電流の大きさ
及び放電時間を調節することにより可能である。図２は
イニシャルボールの柔らかさに対する放電電流値、放電
時間依存性を示すもので、横軸に電流値と放電時間、縦
軸に柔らかさ（イニシャルボールを２０ｇで押圧したと
きの変化量）を示している。同図より、放電電流値を大
とし、放電時間を短くすることにより柔らかくなること
がわかる。本実施の形態においては、変化量が１μ以上
になる硬さが効果的である。The initial ball can be formed softly by adjusting the magnitude of the discharge current flowing between the gold wire and the discharge electrode and the discharge time. FIG. 2 shows the dependence of the discharge current value and the discharge time on the softness of the initial ball. The horizontal axis represents the current value and the discharge time, and the vertical axis represents the softness (the amount of change when the initial ball is pressed with 20 g). Is shown. It can be seen from the figure that the discharge current becomes large by increasing the discharge current value and shortening the discharge time. In the present embodiment, a hardness in which the variation is 1 μ or more is effective.

【００１８】このように構成された本実施の形態は、イ
ニシャルボールを柔らかく形成したことにより、可塑性
が大きくなり、ボンディング時には図１の如くパッド２
１のプローブ痕２４の底部に到達することができ、合金
化することができ、確実なバンプを形成することができ
る。In this embodiment having the above-described structure, the initial ball is formed softly, so that the plasticity is increased. At the time of bonding, as shown in FIG.
The bottom of one probe mark 24 can be reached, can be alloyed, and a reliable bump can be formed.

【００１９】図３は本発明の半導体チップ接続バンプ形
成方法の第２の実施の形態を説明するための図である。
同図において、２１は該半導体チップの上に形成された
アルミニュウムよりなるパッド、２３はバンプ、２４は
プローブ痕である。本実施の形態はこのプローブ痕２４
のあるパッド２１にイニシャルボールをボンディングし
てバンプ２３を形成する時、同図の如く、プローブ痕２
４を避けた位置にボンディングするのである。なおプロ
ーブ痕２４を避けるためには、例えばテレビカメラによ
る画像処理により行うことができる。FIG. 3 is a view for explaining a second embodiment of the semiconductor chip connection bump forming method according to the present invention.
In the figure, 21 is a pad made of aluminum formed on the semiconductor chip, 23 is a bump, and 24 is a probe mark. In the present embodiment, the probe mark 24
When an initial ball is bonded to a pad 21 having a bump to form a bump 23, as shown in FIG.
Bonding is performed at a position avoiding Step 4. In order to avoid the probe marks 24, for example, image processing by a television camera can be performed.

【００２０】このように構成された本実施の形態は、イ
ニシャルボールをプローブ痕のない部分にボンディング
するため、プローブ痕の影響を受けずにボンディングが
でき、確実なバンプ２３を形成することができる。In the present embodiment thus configured, since the initial ball is bonded to a portion having no probe mark, bonding can be performed without being affected by the probe mark, and a reliable bump 23 can be formed. .

【００２１】図４は本発明の半導体チップ接続バンプ形
成方法の第３の実施の形態を説明するための図である。
同図において、２０は半導体チップ、２１は該半導体チ
ップの上に形成されたパッド、２２は該パッドに接続し
た配線パターン、２３はバンプである。本実施の形態
は、プローブ痕のあるパッド２１にイニシャルボールを
ボンディングしてバンプ２３を形成する時、イニシャル
ボールをボンディングする前に、予めイニシャルボール
の下面をギザギザに粗面化しておき、この粗面化した面
をパッド２１に押圧してボンディングするのである。FIG. 4 is a view for explaining a third embodiment of the semiconductor chip connection bump forming method according to the present invention.
In the figure, 20 is a semiconductor chip, 21 is a pad formed on the semiconductor chip, 22 is a wiring pattern connected to the pad, and 23 is a bump. In the present embodiment, when bonding the initial ball to the pad 21 having the probe mark to form the bump 23, before bonding the initial ball, the lower surface of the initial ball is roughened in advance. The flattened surface is pressed against the pad 21 for bonding.

【００２２】このように構成された本実施の形態は、イ
ニシャルボールとパッド２１との接合面積が増え、パッ
ド２１にプローブ痕があっても確実なボンディングがで
きる。なお、イニシャルボールの下面をギザギザにする
には、ボンディング前に、表面をギザギザにした治具に
押圧しギザギザを転写することにより行うことができ
る。In the present embodiment configured as described above, the bonding area between the initial ball and the pad 21 increases, and even if the pad 21 has a probe mark, reliable bonding can be performed. The lower surface of the initial ball can be made jagged before bonding by pressing the jig with the jagged surface to transfer the jagged surface.

【００２３】図５は本発明の半導体チップ接続バンプ形
成方法の第４の実施の形態を説明するための図である。
同図において、２０は半導体チップ、２１は該半導体チ
ップの上に形成されたパッド、２２は該パッドに接続し
た配線パターン、２３はバンプである。本実施の形態
は、プローブ痕のあるパッド２１にイニシャルボールを
ボンディングしてバンプ２３を形成する時、ボンディン
グ前に予めパッド２１の表面をギザギザに粗面化してお
き、この粗面化した面にイニシャルボールをボンディン
グするのである。FIG. 5 is a view for explaining a fourth embodiment of the semiconductor chip connection bump forming method according to the present invention.
In the figure, 20 is a semiconductor chip, 21 is a pad formed on the semiconductor chip, 22 is a wiring pattern connected to the pad, and 23 is a bump. In the present embodiment, when the initial ball is bonded to the pad 21 having the probe mark to form the bump 23, the surface of the pad 21 is roughened in advance before the bonding, and the roughened surface is formed. The initial ball is bonded.

【００２４】このように構成された本実施の形態は、前
実施の形態と同様に、イニシャルボールとパッド２１と
の接合面積が増え、パッド２１にプローブ痕があっても
確実なボンディングができる。なお、パッド２１の表面
をギザギザ面にするには表面をギザギザにした治具を押
圧することにより可能である。In this embodiment having the above-described structure, the bonding area between the initial ball and the pad 21 is increased, as in the previous embodiment, and reliable bonding can be performed even if there is a probe mark on the pad 21. The surface of the pad 21 can be made jagged by pressing a jig having the jagged surface.

【００２５】図６は本発明の半導体チップ接続バンプ形
成方法の第５の実施の形態を説明するための図である。
同図において、２０は半導体チップ、２１は該半導体チ
ップの上に形成されたパッド、２２は該パッドに接続し
た配線パターン、２３はバンプ、２４はプローブ痕、２
５はフラッタリングツールである。本実施の形態は、
（ａ）図の如くプローブ痕のあるパッド２１にイニシャ
ルボールをボンディングしてバンプを形成する時、ボン
ディング前に予めパッド２１の表面を（ｂ）図の如く、
フラッタリングツール２５によりフラッタリングして凹
凸を平坦化した後、（ｃ）図の如くバンプ２３を形成す
るのである。FIG. 6 is a diagram for explaining a fifth embodiment of the semiconductor chip connection bump forming method according to the present invention.
In the figure, 20 is a semiconductor chip, 21 is a pad formed on the semiconductor chip, 22 is a wiring pattern connected to the pad, 23 is a bump, 24 is a probe mark, 2
5 is a fluttering tool. In this embodiment,
(A) When an initial ball is bonded to a pad 21 having a probe mark as shown in the figure and a bump is formed, the surface of the pad 21 is preliminarily bonded as shown in FIG.
After the unevenness is flattened by fluttering with the fluttering tool 25, the bumps 23 are formed as shown in FIG.

【００２６】このように構成された本実施の形態は、平
坦化したパッド２１にイニシャルボールをボンディング
できるため、確実なバンプ２３を形成することができ
る。In the present embodiment having the above-described structure, the initial ball can be bonded to the flattened pad 21, so that the reliable bump 23 can be formed.

【００２７】[0027]

【発明の効果】本発明の半導体チップ接続バンプ形成方
法に依れば、イニシアルボールを柔らかく形成したこ
と、或いはプローブ痕を避けてイニシアルボールをボン
ディングすること、或いはイニシアルボールの下面また
はパッドの表面をギザギザに粗面化すること、或いは、
パッドの表面をフラッタリングツールで平坦化すること
によりイニシアルボールをパッドに確実にボンディング
することができ、確実なバンプを形成することができ
る。According to the semiconductor chip connecting bump forming method of the present invention, the initial ball is formed softly, the initial ball is bonded so as to avoid a probe mark, or the lower surface of the initial ball or the surface of the pad is removed. Roughening the surface, or
By flattening the surface of the pad with a fluttering tool, the initial ball can be securely bonded to the pad, and a reliable bump can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体チップ接続バンプ形成方法の第
１の実施の形態を説明するための図である。FIG. 1 is a view for explaining a first embodiment of a semiconductor chip connection bump forming method of the present invention.

【図２】イニシャルボールの柔らかさに対する放電電流
値、放電時間依存性を示す図である。FIG. 2 is a diagram showing a discharge current value and a discharge time dependency with respect to the softness of an initial ball.

【図３】本発明の半導体チップ接続バンプ形成方法の第
２の実施の形態を説明するための図である。FIG. 3 is a view for explaining a second embodiment of the method for forming a semiconductor chip connection bump according to the present invention.

【図４】本発明の半導体チップ接続バンプ形成方法の第
３の実施の形態を説明するための図である。FIG. 4 is a view for explaining a third embodiment of the semiconductor chip connection bump forming method of the present invention.

【図５】本発明の半導体チップ接続バンプ形成方法の第
４の実施の形態を説明するための図である。FIG. 5 is a view for explaining a fourth embodiment of the semiconductor chip connection bump forming method of the present invention.

【図６】本発明の半導体チップ接続バンプ形成方法の第
５の実施の形態を説明するための図である。FIG. 6 is a view for explaining a fifth embodiment of the semiconductor chip connection bump forming method of the present invention.

【図７】従来のフリップチップ実装方式の実装工程を説
明するための図である。FIG. 7 is a view for explaining a mounting process of a conventional flip-chip mounting method.

【図８】従来のフリップチップ実装方式の実装工程を説
明するための図である。FIG. 8 is a diagram for explaining a mounting process of a conventional flip-chip mounting method.

【図９】発明が解決しようとする課題を説明するための
図である。FIG. 9 is a diagram for explaining a problem to be solved by the invention.

【符号の説明】[Explanation of symbols]

２０…半導体チップ部品 ２１…パッド ２２…配線パターン ２３…バンプ ２４…プローブ痕 ２５…フラッタリングツール Reference Signs List 20 semiconductor chip component 21 pad 22 wiring pattern 23 bump 24 probe mark 25 fluttering tool

フロントページの続き (72)発明者 小八重 健二 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 海沼 則夫 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 江本 哲 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内Continued on the front page (72) Inventor Kenji Koyae 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Norio Kainuma 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Tetsu Emoto 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 金細線を放電エネルギーにより溶融して
金ボールを形成し、該金ボールを半導体チップのパッド
上にボンディングしてバンプを形成する半導体チップ接
続バンプ形成方法において、 前記パッド上に圧痕がある場合、前記放電エネルギーを
調節して硬さの柔らかい金ボールを形成することを特徴
とする半導体チップ接続バンプ形成方法。1. A semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip to form a bump. A method of forming bumps for connecting semiconductor chips, the method comprising: adjusting the discharge energy to form a soft gold ball. 【請求項２】 金細線を放電エネルギーにより溶融して
金ボールを形成し、該金ボールを半導体チップのパッド
上にボンディングしてバンプを形成する半導体チップ接
続バンプ形成方法において、 前記パッド上に圧痕がある場合、バンプ形成位置を圧痕
のない部分に選定することを特徴とする半導体チップ接
続バンプ形成方法。2. A semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip to form a bump. A method for forming a bump for forming a semiconductor chip connection, wherein a bump forming position is selected in a portion having no indentation. 【請求項３】 金細線を放電エネルギーにより溶融して
金ボールを形成し、該金ボールを半導体チップのパッド
上にボンディングしてバンプを形成する半導体チップ接
続バンプ形成方法において、 前記パッド上に圧痕がある場合、前記金ボールの下面を
粗面化することを特徴とする半導体チップ接続バンプ形
成方法。3. A semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball to a pad of a semiconductor chip to form a bump. Wherein there is a roughening of the lower surface of the gold ball. 【請求項４】 金細線を放電エネルギーにより溶融して
金ボールを形成し、該金ボールを半導体チップのパッド
上にボンディングしてバンプを形成する半導体チップ接
続バンプ形成方法において、 前記パッド上に圧痕がある場合、パッド表面を粗面化す
ることを特徴とする半導体チップ接続バンプ形成方法。4. A method for forming bumps on a semiconductor chip by melting gold wires by discharge energy to form gold balls and bonding the gold balls on pads of a semiconductor chip to form bumps. A method for forming bumps on a semiconductor chip, wherein the surface of the pad is roughened, if any. 【請求項５】 金細線を放電エネルギーにより溶融して
金ボールを形成し、該金ボールを半導体チップのパッド
上にボンディングしてバンプを形成する半導体チップ接
続バンプ形成方法において、 前記パッド上に圧痕がある場合、パッド表面をフラッタ
リングツールにより平滑化することを特徴とする半導体
チップ接続バンプ形成方法。5. A semiconductor chip connecting bump forming method for forming a gold ball by melting a fine gold wire by discharge energy and bonding the gold ball on a pad of a semiconductor chip to form a bump. A method of forming bumps on a semiconductor chip, wherein the surface of the pad is smoothed by a fluttering tool.
JP22407997A 1997-08-20 1997-08-20 Semiconductor chip connection bump forming method Expired - Fee Related JP3335562B2 (en)

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Application Number Priority Date Filing Date Title
JP22407997A JP3335562B2 (en) 1997-08-20 1997-08-20 Semiconductor chip connection bump forming method

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JPH1167775A true JPH1167775A (en) 1999-03-09
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001839A1 (en) * 2002-06-21 2003-12-31 Fujitsu Limited Semiconductor device and its producing method
JP2007134418A (en) * 2005-11-09 2007-05-31 Matsushita Electric Ind Co Ltd Semiconductor mounting method
KR100724714B1 (en) 2006-03-31 2007-06-04 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method thereof
US7465653B2 (en) * 2001-02-15 2008-12-16 Megica Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465653B2 (en) * 2001-02-15 2008-12-16 Megica Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
WO2004001839A1 (en) * 2002-06-21 2003-12-31 Fujitsu Limited Semiconductor device and its producing method
US7095045B2 (en) 2002-06-21 2006-08-22 Fujitsu Limited Semiconductor device and manufacturing method thereof
CN100382262C (en) * 2002-06-21 2008-04-16 富士通株式会社 Semiconductor device and its producing method
JP2007134418A (en) * 2005-11-09 2007-05-31 Matsushita Electric Ind Co Ltd Semiconductor mounting method
KR100724714B1 (en) 2006-03-31 2007-06-04 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method thereof

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