JPH1154765A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1154765A JPH1154765A JP9225720A JP22572097A JPH1154765A JP H1154765 A JPH1154765 A JP H1154765A JP 9225720 A JP9225720 A JP 9225720A JP 22572097 A JP22572097 A JP 22572097A JP H1154765 A JPH1154765 A JP H1154765A
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- Japan
- Prior art keywords
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- region
- semiconductor
- voltage
- semiconductor region
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パルス電圧が印加
される半導体装置に関し、特に高電圧のパルス電圧が印
加されるメサ型ダイオード構造等の半導体装置に関す
る。The present invention relates to a semiconductor device to which a pulse voltage is applied, and more particularly to a semiconductor device such as a mesa diode structure to which a high-voltage pulse voltage is applied.
【０００２】[0002]
【従来の技術】レーダーシステムでは１つのアンテナを
送信用、受信用に共用しており、発振器から放射された
大電力のマイクロ波が高感度の受信部に入り込んで受信
部のミクサダイオード等を破損する危険があるため、ダ
イオードリミッタを結合させて受信部を保護している。
ダイオードリミッタは、大電力のマイクロ波が入るとイ
ンピーダンスが変化して所定のレベル以上のマイクロ波
を透過させないように動作する。具体的には、ＰＩＮダ
イオードの両端が導波管に直流的に短絡されていて、Ｐ
ＩＮダイオードに大電力のマイクロ波が印加すると、Ｐ
ＩＮダイオードのインピーダンスが小さくなる。その結
果、マイクロ波の反射面を形成することになり、リミッ
ティングが行われる。2. Description of the Related Art In a radar system, a single antenna is used for both transmission and reception, and high-power microwaves radiated from an oscillator enter a high-sensitivity receiving section and damage a mixer diode or the like in the receiving section. Therefore, the receiving unit is protected by coupling a diode limiter.
When a high-power microwave enters, the diode limiter changes its impedance and operates so as not to transmit a microwave of a predetermined level or more. Specifically, both ends of the PIN diode are short-circuited DC to the waveguide,
When a high-power microwave is applied to the IN diode, P
The impedance of the IN diode decreases. As a result, a microwave reflecting surface is formed, and limiting is performed.
【０００３】ダイオードリミッタを構成するメサ型ＰＩ
Ｎダイオードの断面図を図６に示す。図において、１は
不純物濃度の高いＰ型領域、２は不純物が添加されてい
ないＩ層領域、３は不純物濃度の高いＮ型領域、４はＰ
型領域１にオーム性接触する金属電極、５はＮ型領域３
にオーム性接触する金属電極である。[0003] Mesa PI constituting a diode limiter
FIG. 6 shows a cross-sectional view of the N diode. In the figure, 1 is a P-type region with a high impurity concentration, 2 is an I-layer region where impurities are not added, 3 is an N-type region with a high impurity concentration, and 4 is a P-type region.
A metal electrode in ohmic contact with the mold region 1;
Is a metal electrode that makes ohmic contact with the metal electrode.
【０００４】図に示すように、メサ型ＰＩＮダイオード
は、メサ部側面にＰ型領域１とＩ層領域２の接合面、及
びＮ型領域３とＩ層領域２の接合面が露出した形状とな
っている。このような構造のＰＩＮダイオードに数ＫＷ
から１０ＫＷ程度の高電力のマイクロ波パルスが印加さ
れると、露出する界面で放電が起こり、バルクの絶縁破
壊限界以下で素子が破壊してしまう。As shown in FIG. 1, the mesa PIN diode has a shape in which a junction surface between a P-type region 1 and an I-layer region 2 and a junction surface between an N-type region 3 and an I-layer region 2 are exposed on a side surface of a mesa portion. Has become. Several KW is applied to the PIN diode having such a structure.
When a high-power microwave pulse of about 10 KW to about 10 KW is applied, discharge occurs at the exposed interface, and the element is broken below the dielectric breakdown limit of the bulk.
【０００５】このような現象は、マイクロ波電力を印加
する場合に限らず、図７に示すような不純物濃度の高い
Ｐ型領域１、不純物濃度の低いＩ層領域２、不純物濃度
の高いＮ型領域３を積層し、金属電極４及び５間に高電
圧を印加すると同時に、接合面側面にレーザー光パルス
を照射し、素子を導通させるフォトコンダクティブスイ
ッチにおいても生じる。即ち、Ｐ型領域１とＮ型領域３
間に高電圧が印加することにより、素子表面で、フラッ
シュオーバーと呼ばれる放電に類似した電流が流れ、バ
ルクの絶縁破壊限界以下で素子が破壊してしまう。[0005] Such a phenomenon is not limited to the case where microwave power is applied, but includes a P-type region 1 having a high impurity concentration, an I-layer region 2 having a low impurity concentration, and an N-type region having a high impurity concentration as shown in FIG. The region 3 is laminated, and a high voltage is applied between the metal electrodes 4 and 5, and at the same time, a laser light pulse is applied to the side surface of the bonding surface to generate a photoconductive switch for conducting the element. That is, the P-type region 1 and the N-type region 3
When a high voltage is applied in between, a current similar to a discharge called flashover flows on the element surface, and the element is broken below the dielectric breakdown limit of the bulk.
【０００６】[0006]
【発明が解決しようとする課題】このように、不純物濃
度の高い２つの半導体領域間に不純物濃度の低い半導体
領域が積層された構造の素子にパルス状の電圧を印加し
て使用する半導体装置において、印加される電圧が大き
くなると、その接合面で放電が発生し、素子破壊が起こ
るという問題があった。本発明は、上記問題点を解消
し、高耐圧の半導体装置を提供することを目的とする。As described above, in a semiconductor device which is used by applying a pulse-like voltage to an element having a structure in which a semiconductor region having a low impurity concentration is stacked between two semiconductor regions having a high impurity concentration. When the applied voltage is increased, a discharge occurs at the joint surface, and there is a problem that the element is destroyed. An object of the present invention is to solve the above problems and to provide a semiconductor device with a high breakdown voltage.
【０００７】[0007]
【課題を解決するための手段】本発明は上記目的を達成
するため、不純物濃度の高い第１の半導体領域及び第２
の半導体領域の間に積層された不純物濃度の低い第３の
半導体領域を有し、該第３の半導体領域と前記第１及び
第２の半導体領域との接合面を外部に露出する側面を有
する半導体装置において、少なくとも前記接合面を外部
に露出する側面を被覆する膜を備え、該膜は、ダイアモ
ンド、ダイアモンド状カーボン、炭化シリコン、窒化ア
ルミニウム、窒化ガリウム、インジウム窒化ガリウムと
いった耐電圧の大きい材料の少なくとも一つを含み、前
記第１及び第２の半導体領域間に電圧が印加されると
き、前記第３の半導体領域が主電流経路となり、前記膜
は主電流経路とならないように構成したことを特徴とす
るものである。According to the present invention, there is provided a semiconductor device comprising: a first semiconductor region having a high impurity concentration;
A third semiconductor region having a low impurity concentration laminated between the first and second semiconductor regions, and a side surface exposing a joint surface between the third semiconductor region and the first and second semiconductor regions to the outside. In a semiconductor device, the semiconductor device includes a film that covers at least a side surface that exposes the bonding surface to the outside, and the film is made of a material having a high withstand voltage such as diamond, diamond-like carbon, silicon carbide, aluminum nitride, gallium nitride, and indium gallium nitride. At least one, wherein when a voltage is applied between the first and second semiconductor regions, the third semiconductor region serves as a main current path, and the film does not serve as a main current path. It is a feature.
【０００８】[0008]
【発明の実施の形態】以下、本発明の第１の実施の形態
について、ＰＩＮダイオードを例に取り説明する。シリ
コン半導体からなる１０19〜１０20ａｔｏｍ／ｃｍ3オ
ーダーに不純物が添加され、厚さ２ミクロン程度のＰ型
領域１、不純物を添加しない厚さ２５ミクロン程度のＩ
層領域２及び１０19ａｔｏｍ／ｃｍ3オーダーに不純物
が添加され、厚さ１５０ミクロン程度のＮ型領域３が積
層された半導体基板を用意する。Ｐ型領域１表面に窒化
膜６を堆積させ、通常のホトリソグラフ法により、直径
が１８０ミクロン程度の円形パターンを形成する（図
１）。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to a PIN diode as an example. An impurity is added to the order of 10 @ 19 to 10 @ 20 atom / cm @ 3 made of a silicon semiconductor, and a P-type region 1 having a thickness of about 2 .mu.
A semiconductor substrate is prepared in which an impurity is added to the layer region 2 and an order of 1019 atoms / cm3 and an N-type region 3 having a thickness of about 150 microns is laminated. A nitride film 6 is deposited on the surface of the P-type region 1, and a circular pattern having a diameter of about 180 microns is formed by a usual photolithography method (FIG. 1).
【０００９】窒化膜６をマスクに、Ｎ型領域３が露出す
るまで、Ｐ型領域１及びＩ層領域２をフッ酸、硝酸、酢
酸の混合液を使ってエッチングし、メサ部を形成する
（図２）。次に、ダイアモンド、ダイアモンド状カーボ
ン、炭化シリコン、窒化アルミニウム、窒化ガリウムあ
るいはインジウム窒化ガリウムのいずれか１つを含む薄
膜７を全面に形成する（図３）。Using the nitride film 6 as a mask, the P-type region 1 and the I-layer region 2 are etched using a mixed solution of hydrofluoric acid, nitric acid and acetic acid until the N-type region 3 is exposed, thereby forming a mesa portion ( (Fig. 2). Next, a thin film 7 containing any one of diamond, diamond-like carbon, silicon carbide, aluminum nitride, gallium nitride or indium gallium nitride is formed on the entire surface (FIG. 3).
【００１０】ここで、薄膜は、通常の製造方法により形
成され、例えば、ダイアモンド、ダイアモンド状カーボ
ンはＣＶＤ法により、炭化シリコン、窒化アルミニウ
ム、窒化ガリウム、インジウム窒化ガリウムはスパッタ
法、ＭＯＣＶＤ法により形成することができる。Here, the thin film is formed by an ordinary manufacturing method. For example, diamond and diamond-like carbon are formed by CVD, and silicon carbide, aluminum nitride, gallium nitride, and indium gallium nitride are formed by sputtering and MOCVD. be able to.
【００１１】なお、ダイアモンド状カーボンとは、分解
温度よりはるかに低い温度で形成されるほぼダイアモン
ドに近いカーボンを意味している。The term "diamond-like carbon" means carbon that is formed at a temperature much lower than the decomposition temperature and is substantially similar to diamond.
【００１２】これらの薄膜は、その抵抗率に応じて、金
属電極４、５間にパルス状の電圧が印加されたとき、Ｉ
層領域２が電流経路となり、薄膜７が電流経路とならな
い厚さに設定される。即ち、その抵抗率が低いときに
は、その厚さを薄くし、薄膜の抵抗が大きくなるように
設定する。抵抗率が高いときには、適宜厚さを厚く設定
することができる。When a pulse-like voltage is applied between the metal electrodes 4 and 5 according to their resistivity, these thin films are
The layer region 2 is set to a current path, and the thin film 7 is set to a thickness not to be a current path. That is, when the resistivity is low, the thickness is set to be thin and the resistance of the thin film is set to be large. When the resistivity is high, the thickness can be set appropriately thick.
【００１３】以下、通常のＰＩＮダイオード形成方法に
従い、Ｐ型領域１表面に金属電極４を形成し、Ｎ型領域
３表面に金属電極５を形成した後、素子を分離し、ＰＩ
Ｎダイオードを完成する（図４）。Thereafter, a metal electrode 4 is formed on the surface of the P-type region 1 and a metal electrode 5 is formed on the surface of the N-type region 3 according to a normal PIN diode forming method.
The N diode is completed (FIG. 4).
【００１４】本発明により形成した薄膜７は、耐電圧の
大きい材料で構成されているため、沿面放電が発生して
も、半導体領域は高耐電圧の材料で覆われており、接合
面の放電破壊を防止することができる。Since the thin film 7 formed according to the present invention is made of a material having a high withstand voltage, even if a creeping discharge occurs, the semiconductor region is covered with the material having a high withstand voltage, and the discharge of the junction surface is prevented. Destruction can be prevented.
【００１５】図５に上記方法により薄膜を備えたＰＩＮ
ダイオード（本願構造）と薄膜の無いＰＩＮダイオード
（従来構造）を装着したダイオードリミッタの耐電力試
験結果を示す。○印は素子の破損が無い場合、×印は素
子が破損した場合を示す。試験は、ＰＩＮダイオードの
両端が導波管に直流的に短絡した構造のダイオードリミ
ッタに、周波数９．４ＧＨｚ、５ｋＷ、８ｋＷのマイク
ロ波を導入して行った。図に示すように、従来構造のＰ
ＩＮダイオードでは、５ｋＷでは２０％、８ｋＷでは５
０％の素子が破損するのに対し、本願構造のＰＩＮダイ
オードでは、破損が見られず、本願発明の効果の大きい
ことが確認された。FIG. 5 shows a PIN provided with a thin film by the above method.
The power-proof test result of the diode limiter which mounted the diode (structure of this application) and the PIN diode without the thin film (conventional structure) is shown. A mark indicates that the element was not damaged, and a mark indicates that the element was damaged. The test was performed by introducing microwaves having a frequency of 9.4 GHz, 5 kW, and 8 kW into a diode limiter having a structure in which both ends of a PIN diode were short-circuited to the waveguide in a DC manner. As shown in FIG.
For an IN diode, 20% at 5 kW, 5% at 8 kW
While 0% of the elements were damaged, no damage was observed in the PIN diode having the structure of the present invention, and it was confirmed that the effect of the present invention was great.
【００１６】以上、メサ構造のＰＩＮダイオードを例に
説明を行ったが、本発明は、この構造に限定されるもの
ではなく、種々変更することができる。例えば、Ｐ型領
域の代わりにＮ型領域を、Ｎ型領域の代わりにＰ型領域
を形成しても良い。即ち、ＰＩＮ型構造の代わりに、Ｐ
ＩＰ型、ＮＩＮ型構造であっても良い。また、Ｉ層領域
は、意図的に不純物を添加しないで形成した半導体領域
を示したが、現実には微小の不純物が混入し、Ｎ型ある
いはＰ型の導電型を示すことになる。従って、不純物濃
度が非常に小さい範囲であれば、いずれかの導電型を示
すものであっても良い。As described above, the PIN diode having the mesa structure has been described as an example. However, the present invention is not limited to this structure and can be variously modified. For example, an N-type region may be formed instead of the P-type region, and a P-type region may be formed instead of the N-type region. That is, instead of the PIN type structure, P
It may have an IP type or NIN type structure. Further, although the I-layer region is a semiconductor region formed without intentionally adding an impurity, in reality, a minute impurity is mixed therein, so that the I-layer region shows N-type or P-type conductivity. Therefore, any type of conductivity may be used as long as the impurity concentration is in a very low range.
【００１７】また、マイクロ波用に用いられるダイオー
ドに限らず、フォトコンダクティブスイッチ素子のよう
な高濃度に不純物が添加された２つの領域の間に不純物
濃度の低い領域が積層された構造を有し、高濃度に不純
物が添加された領域間に、パルス状の高電圧が印加され
る構造の素子に対する素子破壊を防止する手段としても
効果的である。The present invention is not limited to a diode used for microwaves, but has a structure in which a region with a low impurity concentration is laminated between two regions with a high concentration of impurities, such as a photoconductive switch element. It is also effective as a means for preventing element destruction in an element having a structure in which a pulsed high voltage is applied between regions where impurities are added at a high concentration.
【００１８】[0018]
【発明の効果】以上説明したように本発明によれば、素
子動作に影響を与えることなく、放電等による素子破壊
を防止することができる。本発明の半導体装置は、通常
の半導体装置の製造手法により、簡便に形成することが
でき、再現性や歩留まり良く形成することができる。As described above, according to the present invention, device destruction due to discharge or the like can be prevented without affecting the device operation. The semiconductor device of the present invention can be easily formed by a normal semiconductor device manufacturing method, and can be formed with good reproducibility and yield.
【図１】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 1 is a cross-sectional view for describing a method for manufacturing a semiconductor device according to the present invention.
【図２】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.
【図３】本発明の半導体装置の製造方法を説明するため
に断面図である。FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention;
【図４】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 4 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.
【図５】本発明の半導体装置と従来の半導体装置の耐電
力性を比較する表である。FIG. 5 is a table comparing the power durability of a semiconductor device of the present invention and a conventional semiconductor device.
【図６】従来のＰＩＮ型ダイオードの断面図である。FIG. 6 is a sectional view of a conventional PIN diode.
【図７】従来のフォトコンダクティブスイッチ素子の斜
視図である。FIG. 7 is a perspective view of a conventional photoconductive switch element.
１ Ｐ型領域 ２ Ｉ層領域 ３ Ｎ型領域 ４、５ 金属電極 ６ 窒化膜 ７ 薄膜 REFERENCE SIGNS LIST 1 P type region 2 I layer region 3 N type region 4, 5 metal electrode 6 nitride film 7 thin film
Claims (1)
第２の半導体領域の間に積層された不純物濃度の低い第
３の半導体領域を有し、該第３の半導体領域と前記第１
及び第２の半導体領域との接合面を外部に露出する側面
を有する半導体装置において、 少なくとも前記接合面を外部に露出する側面を被覆する
膜を備え、該膜は、ダイアモンド、ダイアモンド状カー
ボン、炭化シリコン、窒化アルミニウム、窒化ガリウ
ム、インジウム窒化ガリウムの少なくとも一つを含み、
前記第１及び第２の半導体領域間に電圧が印加されると
き、前記第３の半導体領域が主電流経路となり、前記膜
は主電流経路とならないことを特徴とする半導体装置。A first semiconductor region having a high impurity concentration and a third semiconductor region having a low impurity concentration stacked between the first semiconductor region and the second semiconductor region, wherein the third semiconductor region and the first semiconductor region have a low impurity concentration.
A semiconductor device having a side surface exposing a bonding surface with the second semiconductor region to the outside, comprising: a film covering at least a side surface exposing the bonding surface to the outside, the film comprising diamond, diamond-like carbon, Including at least one of silicon, aluminum nitride, gallium nitride, indium gallium nitride,
When a voltage is applied between the first and second semiconductor regions, the third semiconductor region serves as a main current path, and the film does not serve as a main current path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9225720A JPH1154765A (en) | 1997-08-07 | 1997-08-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9225720A JPH1154765A (en) | 1997-08-07 | 1997-08-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1154765A true JPH1154765A (en) | 1999-02-26 |
Family
ID=16833766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9225720A Pending JPH1154765A (en) | 1997-08-07 | 1997-08-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1154765A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095958A (en) * | 2002-09-02 | 2004-03-25 | National Institute For Materials Science | Deep ultraviolet sensor |
| JP2005340484A (en) * | 2004-05-27 | 2005-12-08 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| CN110838438A (en) * | 2019-10-31 | 2020-02-25 | 中国电子科技集团公司第五十五研究所 | Method for integrating diamond and gallium nitride |
-
1997
- 1997-08-07 JP JP9225720A patent/JPH1154765A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095958A (en) * | 2002-09-02 | 2004-03-25 | National Institute For Materials Science | Deep ultraviolet sensor |
| JP2005340484A (en) * | 2004-05-27 | 2005-12-08 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| CN110838438A (en) * | 2019-10-31 | 2020-02-25 | 中国电子科技集团公司第五十五研究所 | Method for integrating diamond and gallium nitride |
| CN110838438B (en) * | 2019-10-31 | 2022-07-01 | 中国电子科技集团公司第五十五研究所 | Method for integrating diamond and gallium nitride |
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