JPH1154655A - Bag semiconductor device - Google Patents

Bag semiconductor device

Info

Publication number
JPH1154655A
JPH1154655A JP9220681A JP22068197A JPH1154655A JP H1154655 A JPH1154655 A JP H1154655A JP 9220681 A JP9220681 A JP 9220681A JP 22068197 A JP22068197 A JP 22068197A JP H1154655 A JPH1154655 A JP H1154655A
Authority
JP
Japan
Prior art keywords
wiring pattern
elastomer
semiconductor device
intermediate layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9220681A
Other languages
Japanese (ja)
Inventor
Hideshi Hanada
英志 花田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP9220681A priority Critical patent/JPH1154655A/en
Publication of JPH1154655A publication Critical patent/JPH1154655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent peeling of the interface between a wiring pattern and an elastomer by providing an elastomer on the surface of the wiring pattern directly or through an intermediate layer. SOLUTION: A Cu foil 2 applied to the surface of an insulating film 1 is patterned and subjected to Au plating 3 to form a wiring pattern 4. A via hole 5 is made through the insulating film 1 and a solder ball 6 is connected with the wiring pattern 4 exposed through the via hole 5 thus forming an external electrode. Subsequently, an intermediate layer 7 of polyimide resin or Pa plating is formed on the surface of the wiring pattern 4 and an insulating elastomer 8 is provided on the intermediate layer 7 by screen printing. Finally, a semiconductor chip 9 is mounted fixedly such that the functional surface side comes on the elastomer 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＢＧＡ型半導体装
置に関する。The present invention relates to a BGA type semiconductor device.

【０００２】[0002]

【従来の技術】近年、エレクトロニクス機器の高性能
化、多機能化に伴う半導体素子の微細化と半導体装置の
小型化に対応するため、半田ボールを下面側にエリアア
レイ状に配置して高密度表面実装を行うボールグリッド
アレイ（ＢＧＡ）と指称される半導体装置が提案されて
いる。2. Description of the Related Art In recent years, in order to cope with miniaturization of semiconductor elements and miniaturization of semiconductor devices accompanying higher performance and multi-functionality of electronic equipment, solder balls are arranged in an area array on the lower surface side to achieve high density. A semiconductor device called a ball grid array (BGA) for performing surface mounting has been proposed.

【０００３】この一例として、ポリイミドからなる絶縁
性フィルムに、Ｃｕ箔にＡｕメッキを施して配線パター
ンを形成し、さらにこの配線パターン表面に印刷したエ
ラストマを介して半導体チップを固着載置し、この半導
体チップのボンディングパッドと前記配線パターンとを
接続を、配線パターンの先端部であってＣｕ箔をエッチ
ングしたＡｕのみからなる配線リードにて行い、この配
線リード部分を外部との不要な電気的接触を防止するた
め、絶縁性のコーティング材で被覆し、前記絶縁性フィ
ルムの裏面側に複数の半田ボールをエリアアレイ状に配
置したＢＧＡ型半導体装置（μＢＧＡ）がある。As an example of this, a wiring pattern is formed by applying Au plating to a Cu foil on an insulating film made of polyimide, and a semiconductor chip is fixedly mounted via an elastomer printed on the surface of the wiring pattern. The connection between the bonding pad of the semiconductor chip and the wiring pattern is made by a wiring lead made of only Au having a Cu foil etched at the tip of the wiring pattern, and this wiring lead portion is provided with unnecessary electrical contact with the outside. To prevent this, there is a BGA type semiconductor device (μBGA) in which a plurality of solder balls are arranged in an area array on the back side of the insulating film, which is covered with an insulating coating material.

【０００４】この半導体装置（μＢＧＡ）の特徴は、絶
縁性の弾性体であるエラストマと、Ｓ字状に形成された
配線リードとによって、半導体装置に係る熱応力の吸
収、緩和機能を有している点にある。A feature of this semiconductor device (μBGA) is that it has a function of absorbing and relaxing thermal stress relating to the semiconductor device by an elastomer which is an insulating elastic body and wiring leads formed in an S-shape. There is in the point.

【０００５】[0005]

【発明が解決しようとする課題】ところが、この半導体
装置では前述のように、配線パターンの表面がＡｕメッ
キ面であるため、この上に印刷されるエラストマとの密
着性が悪く、後に加熱加圧を受けるうちに配線パターン
とエラストマとの界面が剥離することがあり、半導体装
置の信頼性を著しく低下させている。However, in this semiconductor device, as described above, since the surface of the wiring pattern is an Au-plated surface, the adhesiveness to the elastomer printed thereon is poor, and the semiconductor device is subsequently heated and pressed. In some cases, the interface between the wiring pattern and the elastomer may be peeled off during the process, which significantly reduces the reliability of the semiconductor device.

【０００６】また、前記配線パターンにおいては、実際
にＡｕを必要とするのは先端部の配線リード部分のみに
もかかわらず、製造上の容易性から配線パターンの全面
をＡｕメッキでトレースしているため、結果としてＡｕ
の使用量も多くなり、製造コストの低減を妨げている。[0006] In the above wiring pattern, Au is actually traced by Au plating on the whole surface of the wiring pattern from the viewpoint of easiness in manufacturing, though only the wiring lead portion at the tip end is actually required. Therefore, as a result Au
Is also increasing, which hinders a reduction in manufacturing costs.

【０００７】本発明は、前記実情に鑑みてなされたもの
で、信頼性が高く、また、製造コストを低減することの
できるＢＧＡ型半導体装置を提供することを目的とす
る。The present invention has been made in view of the above circumstances, and has as its object to provide a BGA type semiconductor device which has high reliability and can reduce the manufacturing cost.

【０００８】[0008]

【課題を解決するための手段】上記目的を達成する本発
明の要旨は、周縁部に複数のボンディングパッドを有す
る半導体チップと、配線パターンを具備するとともに、
前記配線パターンに接続され、突出して外部との電気的
接続を行う複数の半田ボールを具備してなる絶縁性フィ
ルムとで構成され、前記配線パターン表面に形成された
エラストマを介して半導体チップの機能面側を貼着する
とともに、前記複数のボンディングパッドに前記配線パ
ターンより延在する配線リードを接続し、前記半導体チ
ップと前記配線リードとの接続部をコーティング材で被
覆したＢＧＡ型半導体装置において、前記配線パターン
の表面に直接または中間層を介在してエラストマが設け
られていることを特徴とするＢＧＡ型半導体装置であ
る。The gist of the present invention to achieve the above object is to provide a semiconductor chip having a plurality of bonding pads on a peripheral portion, a wiring pattern,
An insulating film comprising a plurality of solder balls connected to the wiring pattern and projecting and electrically connecting to the outside, the function of the semiconductor chip via an elastomer formed on the surface of the wiring pattern; A BGA type semiconductor device in which a surface side is attached and a wiring lead extending from the wiring pattern is connected to the plurality of bonding pads, and a connection portion between the semiconductor chip and the wiring lead is covered with a coating material. The BGA type semiconductor device is characterized in that an elastomer is provided on the surface of the wiring pattern directly or with an intermediate layer interposed.

【０００９】前記中間層はポリイミド樹脂あるいはＰｄ
で形成され、配線パターンおよびエラストマそれぞれと
の密着性が高いため、配線パターン界面ならびにエラス
トマ界面に剥離を生じさせることがない。The intermediate layer is made of polyimide resin or Pd.
And the adhesiveness between the wiring pattern and the elastomer is high, so that no separation occurs at the wiring pattern interface and the elastomer interface.

【００１０】また、本発明では前記配線パターンを表面
にＡｕメッキを施さない、Ｃｕ、Ｃｕ合金またはＮｉ、
Ｎｉ合金からなる導電性材料で形成してもよく、この場
合、配線パターンの表面に直接エラストマを設けること
ができる。[0010] In the present invention, the wiring pattern is not plated with Au, and Cu, Cu alloy or Ni,
It may be formed of a conductive material made of a Ni alloy. In this case, the elastomer can be provided directly on the surface of the wiring pattern.

【００１１】このとき、Ａｕメッキは前記配線リード部
の半導体チップ側のみに施されており、Ａｕの使用量が
僅かで済むことから、製造コスト低減を図ることができ
る。At this time, the Au plating is applied only to the semiconductor chip side of the wiring lead portion, and the amount of Au used is small, so that the manufacturing cost can be reduced.

【００１２】[0012]

【発明の実施の形態】以下、本発明による一実施例につ
いて図面を参照しつつ詳細に説明する。図１乃至図３は
本発明によるＢＧＡ型半導体装置の断面図である。な
お、同一部分には同一符号を付してある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. 1 to 3 are sectional views of a BGA type semiconductor device according to the present invention. The same parts are denoted by the same reference numerals.

【００１３】図１は、本発明の第一の実施例を示すもの
であって、例えば厚さ５０μｍ、幅３５ｍｍのポリイミ
ドフィルムからなる絶縁性フィルム１の表面に貼着した
厚さ１０μｍのＣｕ箔２をパターニングし、形成された
Ｃｕパターンに厚さ２５μｍのＡｕメッキ３を施して配
線パターン４が形成され、配線基板を完成している。FIG. 1 shows a first embodiment of the present invention. For example, a 10 μm-thick Cu foil adhered to the surface of an insulating film 1 made of a polyimide film having a thickness of 50 μm and a width of 35 mm, for example. 2 is patterned, and the formed Cu pattern is plated with Au having a thickness of 25 μm to form a wiring pattern 4, thereby completing a wiring substrate.

【００１４】絶縁性フィルム１にはビアホール５が形成
され、このビアホ−ル５を通じて露出する前記配線パタ
ーン４に例えばＰｄ１０％、Ｓｎ９０％の半田からなる
直径０．３ｍｍの半田ボール６を接続して外部電極を形
成している。半田ボール６は、絶縁性フィルム１の裏面
側において格子状をなすようにその全面に形成されてい
る。A via hole 5 is formed in the insulating film 1, and a solder ball 6 having a diameter of 0.3 mm made of, for example, 10% Pd and 90% Sn solder is connected to the wiring pattern 4 exposed through the via hole 5. External electrodes are formed. The solder balls 6 are formed on the entire back surface of the insulating film 1 so as to form a lattice.

【００１５】配線パターン４の表面には、ポリイミド樹
脂あるいはＰｄメッキからなる中間層７が形成され、こ
の中間層７上にスクリーン印刷法によって厚さ１００μ
ｍの絶縁性のエラストマ８が設けられ、このエラストマ
８上に半導体チップ９の機能面側が来るように固着搭載
されている。An intermediate layer 7 made of a polyimide resin or Pd plating is formed on the surface of the wiring pattern 4, and a thickness of 100 μm is formed on the intermediate layer 7 by screen printing.
Insulating elastomer 8 of m is provided, and is fixedly mounted on the elastomer 8 so that the functional surface side of the semiconductor chip 9 comes on the elastomer 8.

【００１６】そして、半導体チップ９の周縁部に形成さ
れたボンディングパッドと、配線パターン４の先端に位
置する配線リード１０とが接続され、配線パターン４と
半導体チップ９との電気的接続を行っている。半導体チ
ップ９の裏面はベア状態となっている。Then, the bonding pads formed on the periphery of the semiconductor chip 9 are connected to the wiring leads 10 located at the tip of the wiring pattern 4, and the wiring pattern 4 and the semiconductor chip 9 are electrically connected. I have. The back surface of the semiconductor chip 9 is in a bare state.

【００１７】配線リード１０はＣｕ箔２を除去したＡｕ
のみによって構成され、Ｓ字状の形態を有している。The wiring lead 10 is made of Au from which the Cu foil 2 has been removed.
And has an S-shape.

【００１８】配線リード１０と半導体チップ９の接続部
はシリコーン系樹脂からなる絶縁性のコーティング材１
1 にて被覆されている。The connection between the wiring lead 10 and the semiconductor chip 9 is made of an insulating coating material 1 made of a silicone resin.
Coated with 1.

【００１９】この実施例の特徴は、配線パターン４とエ
ラストマ８との間に中間層７を介在させている点にあ
り、配線パターン４ならびにエラストマ８の双方とも密
着性の良好な中間層７によって、Ａｕメッキ面を表面と
する配線パターン４にエラストマ８が直接印刷されない
ことから、配線パターン４界面ならびにエラストマ８界
面での剥離を防止することができる。The feature of this embodiment resides in that an intermediate layer 7 is interposed between the wiring pattern 4 and the elastomer 8, and both the wiring pattern 4 and the elastomer 8 have good adhesion. Since the elastomer 8 is not directly printed on the wiring pattern 4 having the Au plating surface as a surface, peeling at the wiring pattern 4 interface and the interface of the elastomer 8 can be prevented.

【００２０】次に図２は、本発明の第二の実施例を示す
ものであり、配線パターン４がＣｕ、Ｃｕ合金またはＮ
ｉ、Ｎｉ合金からなる導電性材料で形成され、この配線
パターン４に表面にエラストマ８が直接設けられてい
る。FIG. 2 shows a second embodiment of the present invention, in which the wiring pattern 4 is made of Cu, Cu alloy or N.
The wiring pattern 4 is made of a conductive material made of i, Ni alloy, and an elastomer 8 is directly provided on the surface thereof.

【００２１】この実施例の特徴は、配線パターン表面の
エラストマ印刷領域にＡｕメッキが施されていないた
め、配線パターン４表面にエラストマ８を直接設けるこ
とができることである。The feature of this embodiment is that the elastomer 8 can be directly provided on the surface of the wiring pattern 4 because Au plating is not applied to the elastomer printing area on the surface of the wiring pattern.

【００２２】また、配線パターン４のエラストマ印刷領
域にはＡｕメッキは施されないが、ボンディング性を考
慮して配線リード１０の半導体チップ９側のみに厚さ１
μｍのＡｕメッキ３が施されていることである。The plating area of the elastomer of the wiring pattern 4 is not plated with Au.
μm Au plating 3 is applied.

【００２３】なお、この実施例では配線パターン４表面
に直接エラストマ８を設けているが、例えば図３に示す
ように、配線パターン４表面に第一の実施例同様にポリ
イミド樹脂あるいはＰｄメッキからなる中間層７を形成
し、この中間層７上にエラストマ８を設るようにしても
よい。In this embodiment, the elastomer 8 is provided directly on the surface of the wiring pattern 4. For example, as shown in FIG. 3, the surface of the wiring pattern 4 is made of polyimide resin or Pd plating as in the first embodiment. The intermediate layer 7 may be formed, and the elastomer 8 may be provided on the intermediate layer 7.

【００２４】[0024]

【発明の効果】本発明は前述でも説明したとおり、配線
パターンとエラストマ界面の剥離を防止しすることによ
って半導体装置の信頼性を高めることができ、また、半
導体装置の製造コスト低減を図ることができる。According to the present invention, as described above, the reliability of a semiconductor device can be improved by preventing separation of an interface between a wiring pattern and an elastomer, and the manufacturing cost of the semiconductor device can be reduced. it can.

【００２５】[0025]

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】本発明の第二の実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図３】本発明の第三の実施例を示す断面図。FIG. 3 is a sectional view showing a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１、絶縁性フィルム ２、Ｃｕ箔 ３、Ａｕメッキ ４、配線パターン ５、ビアホール ６、半田ボール ７、中間層 ８、エラストマ ９、半導体チップ １０、配線リード 1, insulating film 2, Cu foil 3, Au plating 4, wiring pattern 5, via hole 6, solder ball 7, intermediate layer 8, elastomer 9, semiconductor chip 10, wiring lead

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 周縁部に複数のボンディングパッドを有
する半導体チップと、 配線パターンを具備するとともに、前記配線パターンに
接続され、突出して外部との電気的接続を行う複数の半
田ボールを具備してなる絶縁性フィルムとで構成され、
前記配線パターン表面に形成されたエラストマを介して
半導体チップの機能面側を貼着するとともに、前記複数
のボンディングパッドに前記配線パターンより延在する
配線リードを接続し、前記半導体チップと前記配線リー
ドとの接続部をコーティング材で被覆したＢＧＡ型半導
体装置において、 前記配線パターンの表面に直接または中間層を介在して
エラストマが設けられていることを特徴とするＢＧＡ型
半導体装置。A semiconductor chip having a plurality of bonding pads on a peripheral edge thereof; and a plurality of solder balls connected to the wiring pattern and protruding and electrically connected to the outside. Composed of an insulating film,
A function surface side of the semiconductor chip is adhered via an elastomer formed on the surface of the wiring pattern, and a wiring lead extending from the wiring pattern is connected to the plurality of bonding pads. A BGA type semiconductor device in which a connection portion with a coating material is covered with a coating material, wherein an elastomer is provided directly on the surface of the wiring pattern or via an intermediate layer. 【請求項２】 前記配線パターンの表面にポリイミド樹
脂よりなる中間層を形成し、この中間層を介在してエラ
ストマが設られていることを特徴とする請求項１記載の
ＢＧＡ型半導体装置。2. The BGA type semiconductor device according to claim 1, wherein an intermediate layer made of a polyimide resin is formed on the surface of the wiring pattern, and an elastomer is provided with the intermediate layer interposed. 【請求項３】 前記中間層がＰｄよりなる請求項１、ま
たは２記載のＢＧＡ型半導体装置。3. The BGA type semiconductor device according to claim 1, wherein said intermediate layer is made of Pd. 【請求項４】 前記配線パターンはＣｕ、Ｃｕ合金また
はＮｉ、Ｎｉ合金からなる導電性材料で形成され、この
配線パターンの表面に直接エラストマが設けられてお
り、前記配線リード部分にのみＡｕメッキが施されてい
ることを特徴とする請求項１記載のＢＧＡ型半導体装
置。4. The wiring pattern is formed of a conductive material made of Cu, Cu alloy or Ni, Ni alloy, an elastomer is directly provided on the surface of the wiring pattern, and only the wiring lead portion is plated with Au. 2. The BGA type semiconductor device according to claim 1, wherein said BGA type semiconductor device is provided.
JP9220681A 1997-07-31 1997-07-31 Bag semiconductor device Pending JPH1154655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9220681A JPH1154655A (en) 1997-07-31 1997-07-31 Bag semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9220681A JPH1154655A (en) 1997-07-31 1997-07-31 Bag semiconductor device

Publications (1)

Publication Number Publication Date
JPH1154655A true JPH1154655A (en) 1999-02-26

Family

ID=16754811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9220681A Pending JPH1154655A (en) 1997-07-31 1997-07-31 Bag semiconductor device

Country Status (1)

Country Link
JP (1) JPH1154655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309470B1 (en) * 1999-10-07 2001-11-02 김영환 Micro ball grid array package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309470B1 (en) * 1999-10-07 2001-11-02 김영환 Micro ball grid array package and manufacturing method thereof

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