JPH1140767A - Dielectric element and its manufacture - Google Patents
Dielectric element and its manufactureInfo
- Publication number
- JPH1140767A JPH1140767A JP9191416A JP19141697A JPH1140767A JP H1140767 A JPH1140767 A JP H1140767A JP 9191416 A JP9191416 A JP 9191416A JP 19141697 A JP19141697 A JP 19141697A JP H1140767 A JPH1140767 A JP H1140767A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- thin film
- electrode
- dielectric element
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
- G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，誘電体素子及びそ
の製造方法に係り，例えば金属酸化物強誘電体を用いた
強誘電体キャパシタ等において生じる分極率低下を抑制
することのできる誘電体素子及びその製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric element and a method of manufacturing the same, and more particularly to a dielectric element capable of suppressing a decrease in polarizability occurring in a ferroelectric capacitor using a metal oxide ferroelectric. And a method of manufacturing the same.
【０００２】[0002]
【従来の技術】高集積化が図られる例えば半導体メモリ
等においては，電荷蓄積を行うキャパシタについても面
積を極小化したうえで必要容量を確保しなければならな
い。このため，上記キャパシタでは金属酸化物等の強誘
電体層を用いて電荷蓄積を行う場合が多い。ここに，図
５は強誘電体層にいわゆるＰＺＴ（Ｐｂ（ＺｒX Ｔｉ1-
X ）Ｏ3 ）を用いた強誘電体キャパシタの断面構造の一
例を示す図である。2. Description of the Related Art For example, in a semiconductor memory or the like in which high integration is to be achieved, a capacitor for storing electric charges must secure the required capacity after minimizing the area. For this reason, in the above capacitor, charge accumulation is often performed using a ferroelectric layer such as a metal oxide. Here, FIG. 5 shows that the so-called PZT (Pb (Zr x Ti 1-
FIG. 3 is a diagram showing an example of a cross-sectional structure of a ferroelectric capacitor using X ) O 3 ).
【０００３】図５に示すように，上記強誘電体キャパシ
タ５０では，例えばシリコン基板５１上に，下地層とな
るＳｉＯ2 膜５２，白金を用いた下部電極５３，上記Ｐ
ＺＴを用いた強誘電体層５４，白金を用いた上部電極５
５がこの順番に形成される。上記強誘電体キャパシタ５
０の容量は周知の如く強誘電体層５４の分極量によって
変化する。この例で，強誘電体層５４に用いられている
ＰＺＴは，比誘電率が８００〜１０００と非常に高く，
容量容積比も高くなる。尚，強誘電体層５４には，上記
したＰＺＴのほかペロブスカイト構造を有した例えばＢ
ａＴｉＯ3 系の強誘電体等が多く用いられる。As shown in FIG. 5, in the ferroelectric capacitor 50, for example, an SiO 2 film 52 serving as a base layer, a lower electrode 53 using platinum,
Ferroelectric layer 54 using ZT, upper electrode 5 using platinum
5 are formed in this order. The ferroelectric capacitor 5
As is well known, the capacitance of 0 changes depending on the amount of polarization of the ferroelectric layer 54. In this example, the PZT used for the ferroelectric layer 54 has a very high relative dielectric constant of 800 to 1000,
The capacity / volume ratio also increases. The ferroelectric layer 54 includes, for example, BZ having a perovskite structure in addition to PZT described above.
aTiO 3 -based ferroelectrics and the like are often used.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら，上記の
ようなＰｔ／ＰＺＴ／Ｐｔの積層構造を有するキャパシ
タ５０では，例えば適用メモリの読み取りあるいは書き
込み動作の繰り返しにより，印加電圧の反転が繰り返さ
れると，強誘電体層５４の分極率が低下して特性が劣化
する。However, in the capacitor 50 having the stacked structure of Pt / PZT / Pt as described above, when the applied voltage is repeatedly inverted by, for example, repeating the reading or writing operation of the applicable memory, The polarizability of the ferroelectric layer 54 decreases and the characteristics deteriorate.
【０００５】これは，通常，白金電極（即ち，下部電極
５３及び上部電極５５）が柱状結晶の集合体を有する多
結晶薄膜に形成され，分極反転が繰り返されると，酸化
物であるＰＺＴ層（強誘電体層５４）から白金電極５
３，５５へ酸素等が拡散し，界面に劣化層が形成されて
しまうためである。即ち，白金電極５３，５５と強誘電
体層５４との界面に劣化層が形成されることによって，
強誘電体層５４の分極率は低下し，キャパシタ特性が劣
化する。従って，上記誘電体素子をＭＯＳトランジスタ
等と組み合わせて例えば不揮発メモリに使用した場合に
は，このような特性劣化がメモリの誤動作となって現れ
る。[0005] Generally, when a platinum electrode (that is, a lower electrode 53 and an upper electrode 55) is formed in a polycrystalline thin film having an aggregate of columnar crystals, and the domain reversal is repeated, a PZT layer (oxide) is formed. From the ferroelectric layer 54) to the platinum electrode 5
This is because oxygen and the like diffuse into 3,55, and a deteriorated layer is formed at the interface. That is, the deterioration layer is formed at the interface between the platinum electrodes 53 and 55 and the ferroelectric layer 54,
The polarizability of the ferroelectric layer 54 decreases, and the capacitor characteristics deteriorate. Therefore, when the dielectric element is used in combination with a MOS transistor or the like, for example, in a non-volatile memory, such characteristic deterioration appears as a malfunction of the memory.
【０００６】上記の特性劣化を防止することを目的とし
た技術は，例えば特開平５−３４３６１６号公報等に開
示されている。上記参考文献に記載された誘電体素子で
は，電極の誘電体膜と接する部分に酸素を含有する領域
を形成することによって，強誘電体層から電極への酸素
の拡散を抑制している。しかし，この方法では，界面に
おける酸素空乏の発生（劣化層の形成）を防止するため
に余計に酸素注入を行う必要が生じ手間やコストが余分
にかかることになってしまう。A technique aimed at preventing the above characteristic deterioration is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 5-343616. In the dielectric element described in the above reference, diffusion of oxygen from the ferroelectric layer to the electrode is suppressed by forming an oxygen-containing region in a portion of the electrode that contacts the dielectric film. However, in this method, it is necessary to perform extra oxygen injection in order to prevent the generation of oxygen depletion at the interface (formation of a degraded layer), resulting in additional labor and cost.
【０００７】本発明は，このような従来の技術における
課題を解決するために，分極率低下による特性劣化を防
止することのできる誘電体素子及びその製造方法を提供
することを目的とするものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a dielectric element and a method of manufacturing the same, which can prevent the characteristic deterioration due to the decrease in the polarizability in order to solve the problems in the conventional technology. is there.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に第１の発明は，誘電体薄膜にダングリングボンドが実
質的にない非晶質物質を含む電極を接触させた構造を有
する誘電体素子として構成されている。上記誘電体素子
においては，ダングリングボンドが実質的にない，即ち
ファンデアワールス力を主結合とする不活性な非晶質物
質が電極に用いられるため，誘電体薄膜からの拡散が起
こり難く，分極率の低下を抑制して，長期間に渡って良
好な特性を維持することができる。ここで，上記電極に
用いられるのは，例えばＣ60等のフラーレンや高配向グ
ラファイト等の炭素同素体である。Ｃ60分子は，その外
殻がπ電子で覆われており，その表面には切れた結合手
であるダングリングボンドが存在せず，化学的に安定し
ている。In order to achieve the above object, a first aspect of the present invention is a dielectric having a structure in which an electrode containing an amorphous substance substantially free of dangling bonds is brought into contact with a dielectric thin film. It is configured as an element. In the above-mentioned dielectric element, since there is substantially no dangling bond, that is, an inert amorphous material having a Van der Waals force as a main bond is used for the electrode, diffusion from the dielectric thin film hardly occurs. Good characteristics can be maintained over a long period of time by suppressing a decrease in polarizability. Here, for use in the electrode is, for example, a carbon allotrope, such as fullerenes or highly oriented graphite C 60 or the like. C 60 molecules, the outer shell is covered with π electrons, there is no dangling bonds are bonds that expired on the surface thereof is chemically stable.
【０００９】また，上記誘電体素子においては，上記誘
電体薄膜を層状構造とするのが好適である。層状構造を
有する材料は，一般に層内での結合が強く，層間での結
合は主にファンデアワールス力により行われる弱い結合
であるため，層に対して垂直な方向への拡散が生じにく
い。このため，例えば不活性なＣ60を含む電極をビスマ
ス系層状強誘電体薄膜に接触させた場合には，界面にお
いての反応性が乏しいうえに，拡散自体が起こり難く，
誘電体薄膜の分極率の低下がさらに抑制される。In the above-mentioned dielectric element, it is preferable that the dielectric thin film has a layered structure. In general, a material having a layered structure has a strong bond in a layer and a weak bond mainly formed by Van der Waals force between layers, so that diffusion in a direction perpendicular to the layer hardly occurs. Thus, for example, when an electrode comprising an inert C 60 is brought into contact with the bismuth-based layered ferroelectric thin film is on top poor reactivity at the interface, hardly occurs diffusion itself,
A decrease in the polarizability of the dielectric thin film is further suppressed.
【００１０】従って，上記誘電体素子においては，上記
誘電体薄膜に金属酸化物誘電体を用いた場合でも，金属
酸化物誘電体から電極への酸素の拡散を簡便に抑制する
ことができる。上記誘電体素子について，より詳しくい
えば，上記電極には上記非晶質物質に金属的電導特性を
生じさせるためのアルカリ金属が含まれる。このアルカ
リ金属は例えばＣｓ等であり，Ｃ60とともにＣｓ3 Ｃ60
薄膜を形成し，電極としての金属電導特性を確保する。Therefore, in the dielectric element, even when a metal oxide dielectric is used for the dielectric thin film, diffusion of oxygen from the metal oxide dielectric to the electrode can be easily suppressed. More specifically, in the dielectric element, the electrode includes an alkali metal for causing the amorphous material to have metallic conductivity. The alkali metal is, for example, Cs and the like, Cs 3 C 60 with C 60
A thin film is formed to secure metal conductivity as an electrode.
【００１１】また，上記誘電体素子は，例えば強誘電体
キャパシタやＦＥＴのゲート電極等に適用が可能であ
る。さらに，その際の上記誘電体素子の構造は多様であ
り，例えば半導体基板上に，絶縁膜，上記非晶質物質を
含む下部電極，上記誘電体薄膜，上記非晶質物質を含む
上部電極がこの順番に形成されたＭＦＭＩＳ構造を有す
るものがある。その他，例えば半導体基板上に，上記誘
電体薄膜，上記非晶質物質を含む上部電極がこの順番に
形成されたＭＦＳ構造を有するものや，半導体基板上
に，絶縁膜，上記誘電体薄膜，上記非晶質物質を含む上
部電極がこの順番に形成されたＭＦＩＳ構造を有するも
の，さらには，半導体基板上に，上記非晶質物質を含む
下部電極，上記誘電体薄膜，上記非晶質物質を含む上部
電極がこの順番に形成されたＭＦＭＳ構造を有するもの
がある。尚，これらの誘電体素子は，半導体基板自身だ
けでなく，半導体基板に形成された半導体層上等に設け
られる場合もある。The above-mentioned dielectric element can be applied to, for example, a ferroelectric capacitor, a gate electrode of an FET, and the like. Further, the structure of the dielectric element at that time is various, and for example, an insulating film, a lower electrode containing the amorphous material, a dielectric thin film, and an upper electrode containing the amorphous material are formed on a semiconductor substrate. Some have an MFMIS structure formed in this order. In addition, for example, one having an MFS structure in which the dielectric thin film and the upper electrode containing the amorphous material are formed in this order on a semiconductor substrate, an insulating film, the dielectric thin film, An upper electrode having an MFIS structure in which an upper electrode containing an amorphous material is formed in this order. Further, a lower electrode containing the amorphous material, the dielectric thin film, and the amorphous material are formed on a semiconductor substrate. In some cases, the upper electrode includes an MFMS structure formed in this order. Note that these dielectric elements may be provided not only on the semiconductor substrate itself but also on a semiconductor layer formed on the semiconductor substrate.
【００１２】また，第２の発明は，上記第１の発明に係
る誘電体素子を好適に製造するための方法であって，ダ
ングリングボンドが実質的にない非晶質物質を含む電極
を形成する工程と，層状構造を有する誘電体薄膜を形成
する工程とを具備してなる誘電体素子の製造方法として
構成されている。According to a second aspect of the present invention, there is provided a method for suitably manufacturing the dielectric element according to the first aspect, wherein the method comprises forming an electrode containing an amorphous substance substantially free of dangling bonds. And a step of forming a dielectric thin film having a layered structure.
【００１３】[0013]
【発明の実施の形態】以下，添付図面を参照して，本発
明の一実施の形態につき説明し，本発明の理解に供す
る。尚，以下の実施の形態は，本発明の具体的な一例で
あって，本発明の技術的範囲を限定する性格のものでは
ない。ここに，図１は本発明の一実施の形態に係る誘電
体素子の断面構造を示す図である。An embodiment of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention. The following embodiment is a specific example of the present invention and does not limit the technical scope of the present invention. FIG. 1 is a diagram showing a cross-sectional structure of a dielectric element according to one embodiment of the present invention.
【００１４】図１に示すように，本発明の一実施の形態
に係る誘電体素子は，シリコン基板１上に，ＳｉＯ2 等
の絶縁膜２，ダングリングボンドのない非晶質物質を含
む下部電極３，層状構造を有した誘電体薄膜４，上記非
晶質物質を含む上部電極５がこの順番に形成されたＭＦ
ＭＩＳ( Metal Ferroelectric Metal Insulator Semico
nductor ) 構造を有し，強誘電体キャパシタ６を構成す
る。As shown in FIG. 1, a dielectric device according to an embodiment of the present invention comprises an insulating film 2 such as SiO 2 on a silicon substrate 1 and a lower portion containing an amorphous material without dangling bonds. An MF in which an electrode 3, a dielectric thin film having a layered structure 4, and an upper electrode 5 containing the above amorphous material are formed in this order
MIS (Metal Ferroelectric Metal Insulator Semico
The ferroelectric capacitor 6 has a structure.
【００１５】より具体的には，上記誘電体素子の下部電
極３及び上部電極５には，Ｃ60，Ｃ 70若しくはカーボン
ナノチューブ等のアモルファス状フラーレン等が用いら
れる。このＣ60分子は，図２に示すような構造を有して
おり，その表面には切れた結合手であるダングリングボ
ンドは存在しない。即ち，その表面において共有結合の
ような強い結合はなく，弱いエネルギーで結合する物理
吸着が起きる程度であり，化学的に安定である。また，
上記下部電極３及び上部電極５においては，上記Ｃ60等
に対してＣｓ等のアルカリ金属がインターカレートされ
ており，金属的電導特性が確保されている。More specifically, the lower electrode of the dielectric element is
The pole 3 and the upper electrode 5 have C60, C 70Or carbon
Amorphous fullerenes such as nanotubes are used.
It is. This C60The molecule has the structure shown in Figure 2.
On its surface, a dangling bob
Does not exist. That is, a covalent bond on the surface
Physics that does not have such a strong bond, but bonds with weak energy
To the extent that adsorption occurs, it is chemically stable. Also,
In the lower electrode 3 and the upper electrode 5, the C60etc
Alkali metal such as Cs is intercalated
The metallic conductivity is ensured.
【００１６】また，電荷蓄積層である上記誘電体薄膜４
には，例えばＢｉ系層状強誘電体薄膜等が用いられる。
層状構造を有する酸化物では，層内での結合は強いが，
層間での結合は主にファンデアワールス力により行われ
ており，劈開を起こす程に弱いことが知られている。以
下，上記誘電体素子を用いた強誘電体キャパシタ６の製
造方法について説明する。The dielectric thin film 4 serving as a charge storage layer
For example, a Bi-based layered ferroelectric thin film or the like is used.
For oxides with a layered structure, the bonds within the layer are strong,
It is known that the bonding between the layers is mainly performed by van der Waals force, and is weak enough to cause cleavage. Hereinafter, a method of manufacturing the ferroelectric capacitor 6 using the dielectric element will be described.
【００１７】まず，通常のシリコンプロセスにも用いら
れるような例えばＣＶＤ法等により，シリコン基板１上
にＳｉＯ2 の絶縁膜２が形成される。次に，真空中で，
るつぼ加熱を行ってＣ60を蒸発させることにより，上記
絶縁膜２上にＣ60薄膜が形成される。尚，基板温度は約
２５０℃程度に設定される。また，このときには，Ｃｓ
等のアルカリ金属も蒸着されており，結局，絶縁膜２上
にはＣｓ3 Ｃ60の薄膜からなる下部電極３が形成され
る。[0017] First, by a conventional silicon process, for example, CVD method or the like, such as also used, the insulating film 2 of SiO 2 is formed on the silicon substrate 1. Next, in a vacuum,
Evaporation of the C 60 performs crucible heating, C 60 thin film is formed on the insulating film 2. The substrate temperature is set to about 250 ° C. In this case, Cs
Thus, the lower electrode 3 made of a Cs 3 C 60 thin film is formed on the insulating film 2.
【００１８】その後，活性酸素ビーム分子線エピタキシ
ー法を用いて，上記下部電極３上に層状構造の誘電体薄
膜４が形成される。この誘電体薄膜４の形成にあたって
は，まず，基板が２５０℃程度まで加熱され，面方向の
成長速度が大きいＢｉ2 ＶＯ 5.5 が１０分子層程度形成
される。このとき，原料（Ｂｉ2 Ｏ3 ，Ｖ）は，結晶構
造の重なりの順番に従って堆積する。即ち，１分子層で
は，Ｂｉ−（−Ｂｉ−Ｖ−Ｂｉ−）−Ｂｉ−となる。ま
た，急峻な界面を形成するためには，はじめに活性酸素
を基板に供給せず原料を堆積させ，その後基板に活性酸
素を供給し，先に堆積した上記原料を酸化させるという
プロセスを経て，各Ｂｉ2 ＶＯ5.5 層を形成することが
重要である。After that, active oxygen beam molecular beam epitaxy
The dielectric thin film having a layered structure is formed on the lower electrode 3 by using the
A film 4 is formed. In forming this dielectric thin film 4
First, the substrate is heated to about 250 ° C,
Bi with high growth rateTwoVO 5.5Formed about 10 molecular layers
Is done. At this time, the raw material (BiTwoOThree, V) are crystal structures
They are deposited according to the order of the structure. That is, with one molecular layer
Becomes Bi-(-Bi-V-Bi-)-Bi-. Ma
To form a steep interface, first use active oxygen
The raw material is deposited without supplying the substrate to the substrate.
Supply oxygen and oxidize the previously deposited material
Through the process, each BiTwoVO5.5Forming a layer
is important.
【００１９】次に，基板温度が４５０℃から５５０℃程
度に昇温され，連続してＢｉ2 ＳｒＴａＯ9 層が形成さ
れる。Ｂｉ2 ＳｒＴａＯ9 層の形成においても，原料
（Ｂｉ 2 Ｏ3 ，Ｔａ，Ｓｒ）は，結晶構造の重なりの順
番に従って堆積する。即ち，１分子層では，Ｂｉ−（−
Ｂｉ−Ｔａ−Ｓｒ−Ｔａ−Ｂｉ−）−Ｂｉ−となる。こ
の場合，活性酸素は原料堆積時に同時に供給して原料を
十分酸化させながら，厚み１００ｎｍから２５０ｎｍま
で成長させる。Next, the substrate temperature is about 450 ° C. to 550 ° C.
Temperature is increased, and BiTwoSrTaO9Layer formed
It is. BiTwoSrTaO9In forming the layer,
(Bi TwoOThree, Ta, Sr) are the order of crystal structure overlap.
Deposit according to turn. That is, in one molecular layer, Bi-(-
Bi-Ta-Sr-Ta-Bi-)-Bi-. This
In the case of, the active oxygen is supplied at the same time as the
While sufficiently oxidizing, reduce the thickness from 100 nm to 250 nm.
Grow with.
【００２０】その後，さらにＢｉ2 ＶＯ5.5 強誘電体薄
膜が上記と同様に１０分子層程度形成され層状構造の誘
電体薄膜４が形成される。尚，誘電体薄膜４では，上記
のような層状構造を１ユニットとして積層を行うことも
可能である。そして，下部電極３と同様に，誘電体薄膜
４上に上部電極５となるＣｓ3 Ｃ60薄膜が形成される。
このときの基板温度も２５０℃程度である。また，原料
堆積時には，化学量論比に合うようにＣ60分子とアルカ
リ金属の堆積率を調整して原料が供給される。尚，上部
電極５，下部電極３の膜厚は１００〜２００ｎｍ程度で
ある。Thereafter, about 10 molecular layers of a Bi 2 VO 5.5 ferroelectric thin film are formed in the same manner as described above, and a dielectric thin film 4 having a layered structure is formed. In the dielectric thin film 4, it is also possible to laminate the above-mentioned layered structure as one unit. Then, similarly to the lower electrode 3, a Cs 3 C 60 thin film serving as the upper electrode 5 is formed on the dielectric thin film 4.
The substrate temperature at this time is also about 250 ° C. Further, when the raw material deposition material by adjusting the C 60 molecule and alkali metal deposition rate is supplied to match the stoichiometric ratio. The thickness of the upper electrode 5 and the lower electrode 3 is about 100 to 200 nm.
【００２１】上述のようにして１００μｍ×１００μｍ
程度のキャパシタ６を形成し，該キャパシタ６に対して
分極反転を繰り返したときの強誘電体キャパシタ６の分
極量の変化を図３に示す。図３に示すファティーグ特性
のように，本実施の形態に係る強誘電体キャパシタ６
（図中，黒丸で示す）では，１０10回以上に渡って印加
電圧の反転を繰り返した場合でも，分極量の低下は１０
パーセント以内に抑えられており，従来のキャパシタ
（図中，白丸で示す）と比較して明確な特性向上が得ら
れている。これは，下部電極３及び上部電極５に不活性
なＣｓ3 Ｃ60が用いられているうえに，層状構造によっ
て誘電体薄膜４からの酸素等の拡散自体が抑えられてい
るためである。従って，このキャパシタ６を例えばＭＯ
Ｓトランジスタと組み合わせて不揮発性メモリに用いた
場合，比較的長期間に渡って安定な動作状態を確保する
ことができる。As described above, 100 μm × 100 μm
FIG. 3 shows a change in the amount of polarization of the ferroelectric capacitor 6 when the capacitor 6 of about the same size is formed and the polarization inversion is repeated for the capacitor 6. As shown in FIG. 3, the ferroelectric capacitor 6 according to the present embodiment
(Shown by black circles), the even if the repeated reversal of the applied voltage for more than 10 10 times, a decrease in the polarization amount 10
It is suppressed to within the percentage, and the characteristic is clearly improved as compared with the conventional capacitor (shown by a white circle in the figure). This is because inactive Cs 3 C 60 is used for the lower electrode 3 and the upper electrode 5 and the diffusion of oxygen and the like from the dielectric thin film 4 itself is suppressed by the layered structure. Therefore, this capacitor 6 can be
When used in a nonvolatile memory in combination with an S transistor, a stable operation state can be ensured for a relatively long period.
【００２２】このように，本実施の形態に係る誘電体素
子によれば，分極反転の繰り返しに伴う分極疲労が起こ
り難い強誘電体キャパシタ６を形成することが可能であ
る。As described above, according to the dielectric element of the present embodiment, it is possible to form the ferroelectric capacitor 6 in which the polarization fatigue due to the repetition of the polarization inversion hardly occurs.
【００２３】[0023]
【実施例】上記実施の形態では，上部電極５及び下部電
極３の材料にＣ60等のアモルファス状フラーレンを用い
たが，タングリングボンドを表面に有さず不活性な例え
ば高配向グラファイト（ＨＯＰＧ）等の他の非晶質物質
を用いてもよい。また，上記実施の形態では，ＭＦＭＩ
Ｓ構造の誘電体素子を用いて強誘電体キャパシタ６を構
成したが，強誘電体キャパシタ６に限らず，例えばＭＦ
ＭＩＳ構造を有したＦＥＴ（ＭＦＭＩＳ−ＦＥＴ）等に
本発明における誘電体素子を適用することも可能であ
る。ここで，図４はゲート電極ＧＰにＭＦＭＩＳ構造の
誘電体素子を有するＭＦＭＩＳ−ＦＥＴ４０の断面構造
の一例を示す図である。尚，４１はソース・ドレイン領
域である。また，このＦＥＴを利用して１トランジスタ
でメモリ動作を実現することも可能である。さらに，上
記したＭＦＭＩＳ構造に限らず，半導体基板上に絶縁
膜，誘電体薄膜がこの順番に形成されたＭＦＳ構造(Met
al Ferroelectric Semiconductor )や，半導体基板上に
絶縁膜，誘電体薄膜，電極がこの順番に形成されたＭＦ
ＩＳ構造( Metal Ferroelectric Insulator Semiconduc
tor ) や，半導体基板上に電極，誘電体薄膜，電極がこ
の順番に形成されたＭＦＭＳ構造( Metal Ferroelectri
c Metal Semiconductor ) 等についても本発明に係る誘
電体素子を適用することが可能である。さらに，上記実
施の形態では，半導体基板１上に直接強誘電体キャパシ
タ６を設けたが，もちろん半導体基板１上に形成した半
導体層上等に設けてもよい。EXAMPLES In the embodiment described above, but using an amorphous-like fullerenes such as C 60 to the material of the upper electrode 5 and the lower electrode 3, inert example highly oriented graphite having no dangling bonds on a surface (HOPG ) May be used. In the above embodiment, the MFMI
Although the ferroelectric capacitor 6 is formed using the S-structure dielectric element, the ferroelectric capacitor 6 is not limited to the ferroelectric capacitor 6 and may be, for example,
The dielectric element according to the present invention can be applied to an FET having a MIS structure (MFMIS-FET) or the like. Here, FIG. 4 is a diagram showing an example of a cross-sectional structure of an MFMIS-FET 40 having a dielectric element having an MFMIS structure in a gate electrode GP. Incidentally, 41 is a source / drain region. It is also possible to realize a memory operation with one transistor using this FET. Further, the present invention is not limited to the above-described MFMIS structure, and an MFS structure (Met structure) in which an insulating film and a dielectric thin film are formed in this order on a semiconductor substrate.
al Ferroelectric Semiconductor) or an MF in which an insulating film, a dielectric thin film, and electrodes are formed in this order on a semiconductor substrate
IS structure (Metal Ferroelectric Insulator Semiconduc
tor) or an MFMS structure (Metal Ferroelectri) in which an electrode, a dielectric thin film, and an electrode are formed in this order on a semiconductor substrate.
c Metal Semiconductor) and the like, the dielectric element according to the present invention can be applied. Further, in the above embodiment, the ferroelectric capacitor 6 is provided directly on the semiconductor substrate 1, but may be provided on a semiconductor layer formed on the semiconductor substrate 1 or the like.
【００２４】さらに，本発明に係る誘電体素子は，集積
化された半導体メモリだけでなく，例えば磁気ディスク
装置のようにディスクの表面に誘電体を塗布しヘッドで
部分的に分極状態を変化させて情報を記憶する記憶装置
等にも利用可能である。また，上記実施の形態では，よ
りファティーグ特性を良好にするために，酸素等の拡散
が生じ難い層状構造の誘電体薄膜４を用いたが，その他
の強誘電体構造を用いてもよい。Further, in the dielectric element according to the present invention, not only an integrated semiconductor memory but also a dielectric material is applied to the surface of a disk such as a magnetic disk device, and the polarization state is partially changed by a head. It can also be used as a storage device for storing information. In the above-described embodiment, the dielectric thin film 4 having a layered structure in which diffusion of oxygen and the like hardly occurs is used in order to further improve the fatigue characteristics. However, another ferroelectric structure may be used.
【００２５】[0025]
【発明の効果】上記のように請求項１から６のいずれか
１項に記載した第１の発明によれば，分極率の低下を抑
制して，長期間に渡って良好なファティーグ特性を維持
することが可能な誘電体素子を提供することができる。
特に，誘電体薄膜が層状構造を有する場合には，界面に
おいての反応性が乏しいうえに，酸素等の拡散自体が起
こり難く，誘電体薄膜の分極率の低下がさらに抑制され
る。このため上記誘電体薄膜に金属酸化物誘電体を用い
た場合でも，金属酸化物誘電体から電極への酸素等の拡
散を簡便に抑制することができる。As described above, according to the first aspect of the present invention, a decrease in polarizability is suppressed, and a good fating characteristic is maintained over a long period of time. A dielectric element capable of performing the above-described operations.
In particular, when the dielectric thin film has a layered structure, the reactivity at the interface is poor, diffusion of oxygen and the like is unlikely to occur, and the decrease in the polarizability of the dielectric thin film is further suppressed. Therefore, even when a metal oxide dielectric is used for the dielectric thin film, diffusion of oxygen and the like from the metal oxide dielectric to the electrode can be easily suppressed.
【００２６】また，請求項７に記載した第２の発明によ
れば，簡単な工程だけで分極率の低下を抑制して，長期
間に渡って良好なファティーグ特性を維持することが可
能な誘電体素子の製造方法を提供することができる。According to the second aspect of the present invention, it is possible to suppress a decrease in polarizability only by a simple process and maintain a good fating characteristic for a long period of time. A method for manufacturing a body element can be provided.
【図１】 本発明の一実施の形態に係る強誘電体キャパ
シタの断面構造を示す図。FIG. 1 is a diagram showing a cross-sectional structure of a ferroelectric capacitor according to one embodiment of the present invention.
【図２】 Ｃ60の構造を説明するための図。Figure 2 is a diagram illustrating the structure of C 60.
【図３】 上記強誘電体キャパシタのファティーグ特性
を示す図。FIG. 3 is a view showing a fatiging characteristic of the ferroelectric capacitor.
【図４】 本発明に係る誘電体素子を適用したＭＦＭＩ
Ｓ−ＦＥＴの断面構造の一例を示す図。FIG. 4 is an MFMI to which the dielectric element according to the present invention is applied.
FIG. 2 is a diagram illustrating an example of a cross-sectional structure of an S-FET.
【図５】 従来の強誘電体キャパシタの断面構造の一例
を示す図。FIG. 5 is a diagram showing an example of a cross-sectional structure of a conventional ferroelectric capacitor.
１…半導体基板 ２…絶縁膜 ３…下部電極 ４…誘電体薄膜 ５…上部電極 REFERENCE SIGNS LIST 1 semiconductor substrate 2 insulating film 3 lower electrode 4 dielectric thin film 5 upper electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｂ 3/02 Ｈ０１Ｌ 27/10 ４５１ Ｈ０１Ｇ 4/10 Ｈ０１Ｇ 4/10 Ｈ０１Ｌ 27/10 ４５１ Ｈ０１Ｌ 29/78 ３７１ 21/8247 29/788 29/792 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code FI H01B 3/02 H01L 27/10 451 H01G 4/10 H01G 4/10 H01L 27/10 451 H01L 29/78 371 21/8247 29 / 788 29/792
Claims (7)
的にない非晶質物質を含む電極を接触させた構造を有す
る誘電体素子。1. A dielectric element having a structure in which an electrode containing an amorphous substance substantially free of dangling bonds is brought into contact with a dielectric thin film.
項１記載の誘電体素子。2. The dielectric device according to claim 1, wherein said amorphous substance is fullerene.
項１又は２記載の誘電体素子。3. The dielectric device according to claim 1, wherein said dielectric thin film has a layered structure.
れてなる請求項１，２，又は３に記載の誘電体素子。4. The dielectric element according to claim 1, wherein a ferroelectric material is used for said dielectric thin film.
いられてなる請求項１，２，３，又は４に記載の誘電体
素子。5. The dielectric device according to claim 1, wherein a metal oxide dielectric is used for the dielectric thin film.
導特性を生じさせるアルカリ金属を含んでなる請求項
１，２，３，４，又は５に記載の誘電体素子。6. The dielectric element according to claim 1, wherein said electrode comprises an alkali metal which causes said amorphous substance to have metallic conductive properties.
質物質を含む電極を形成する工程と，層状構造を有する
誘電体薄膜を形成する工程とを具備し，上記電極と上記
誘電体薄膜とが接触してなる誘電体素子の製造方法。7. A method comprising: forming an electrode containing an amorphous substance substantially free of dangling bonds; and forming a dielectric thin film having a layered structure. And a method for manufacturing a dielectric element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9191416A JPH1140767A (en) | 1997-07-16 | 1997-07-16 | Dielectric element and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9191416A JPH1140767A (en) | 1997-07-16 | 1997-07-16 | Dielectric element and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1140767A true JPH1140767A (en) | 1999-02-12 |
Family
ID=16274256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9191416A Pending JPH1140767A (en) | 1997-07-16 | 1997-07-16 | Dielectric element and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1140767A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1059266A2 (en) * | 1999-06-11 | 2000-12-13 | Iljin Nanotech Co., Ltd. | Mass synthesis method of high purity carbon nanotubes vertically aligned over large-size substrate using thermal chemical vapor deposition |
| KR100489800B1 (en) * | 2002-11-26 | 2005-05-16 | 한국전자통신연구원 | Capacitor and method for manufacturing the same |
| JP2007158344A (en) * | 2005-12-02 | 2007-06-21 | Samsung Electronics Co Ltd | Storage node with metal layer-insulating layer-metal layer structure, unvolatile memory element therewith, and method of operating same |
| JP2007288171A (en) * | 2006-03-20 | 2007-11-01 | National Institute For Materials Science | Solid-state device structure, and electric/electronic device and electric/electronic appliance using it |
| JP2008141193A (en) * | 2006-11-21 | 2008-06-19 | Samsung Electronics Co Ltd | Nonvolatile memory element and its manufacturing method |
| KR100866314B1 (en) | 2006-12-13 | 2008-11-03 | 서울시립대학교 산학협력단 | MFMS FET and ferroelectric memory device |
| WO2009044963A1 (en) * | 2007-10-01 | 2009-04-09 | Industry-University Cooperation Foundation, Hanyang University | Memory device using carbon nanotube and method of fabricating the same |
| US11908918B2 (en) | 2018-09-18 | 2024-02-20 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
-
1997
- 1997-07-16 JP JP9191416A patent/JPH1140767A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1059266A2 (en) * | 1999-06-11 | 2000-12-13 | Iljin Nanotech Co., Ltd. | Mass synthesis method of high purity carbon nanotubes vertically aligned over large-size substrate using thermal chemical vapor deposition |
| EP1059266A3 (en) * | 1999-06-11 | 2000-12-20 | Iljin Nanotech Co., Ltd. | Mass synthesis method of high purity carbon nanotubes vertically aligned over large-size substrate using thermal chemical vapor deposition |
| US6350488B1 (en) | 1999-06-11 | 2002-02-26 | Iljin Nanotech Co., Ltd. | Mass synthesis method of high purity carbon nanotubes vertically aligned over large-size substrate using thermal chemical vapor deposition |
| KR100489800B1 (en) * | 2002-11-26 | 2005-05-16 | 한국전자통신연구원 | Capacitor and method for manufacturing the same |
| JP2007158344A (en) * | 2005-12-02 | 2007-06-21 | Samsung Electronics Co Ltd | Storage node with metal layer-insulating layer-metal layer structure, unvolatile memory element therewith, and method of operating same |
| JP2007288171A (en) * | 2006-03-20 | 2007-11-01 | National Institute For Materials Science | Solid-state device structure, and electric/electronic device and electric/electronic appliance using it |
| JP2008141193A (en) * | 2006-11-21 | 2008-06-19 | Samsung Electronics Co Ltd | Nonvolatile memory element and its manufacturing method |
| KR100866314B1 (en) | 2006-12-13 | 2008-11-03 | 서울시립대학교 산학협력단 | MFMS FET and ferroelectric memory device |
| WO2009044963A1 (en) * | 2007-10-01 | 2009-04-09 | Industry-University Cooperation Foundation, Hanyang University | Memory device using carbon nanotube and method of fabricating the same |
| KR100911380B1 (en) | 2007-10-01 | 2009-08-10 | 한양대학교 산학협력단 | Memory device using carbon nanotube and method of fabricating the same |
| US11908918B2 (en) | 2018-09-18 | 2024-02-20 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
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