JPH11337981A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
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- JPH11337981A JPH11337981A JP14635798A JP14635798A JPH11337981A JP H11337981 A JPH11337981 A JP H11337981A JP 14635798 A JP14635798 A JP 14635798A JP 14635798 A JP14635798 A JP 14635798A JP H11337981 A JPH11337981 A JP H11337981A
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- liquid crystal
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- electrode
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は液晶表示装置に関
し、特に、それに用いられる液晶素子の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a structure of a liquid crystal element used for the same.
【０００２】[0002]
【背景技術】近年、液晶素子は特に表示装置として、低
消費電力で軽量なディスプレイデバイスとして、テレ
ビ、電子手帳、パーソナルコンピュータ、携帯電話等の
電子機器に広く利用されている。そして、ＭＩＭ素子、
バック・ツウー・バック・ダイオード素子、ダイオード
・リング素子、バリスタ素子等の非線形抵抗素子をスイ
ッチ素子として用いた２端子型アクティブマトリクス液
晶素子や薄膜トランジスタをスイッチ素子として用いた
３端子型アクティブマトリクス液晶素子が、その高い性
能（高コントラスト、高速応答）により脚光を浴びてお
り、特に２端子型アクティブマトリクス液晶素子はスイ
ッチ素子の構造が簡単な為に液晶素子を安い製造コスト
で提供することが可能である。2. Description of the Related Art In recent years, liquid crystal elements have been widely used as electronic devices such as televisions, electronic organizers, personal computers, and mobile phones, especially as display devices, and as low power consumption and lightweight display devices. And a MIM element,
A two-terminal active matrix liquid crystal element using a non-linear resistance element such as a back-to-back diode element, a diode ring element, and a varistor element as a switching element and a three-terminal active matrix liquid crystal element using a thin film transistor as a switching element are known. The high performance (high contrast, high-speed response) has been spotlighted. In particular, a two-terminal type active matrix liquid crystal element can provide a liquid crystal element at a low manufacturing cost because of a simple structure of a switch element. .
【０００３】ここで、２端子型アクティブマトリクス液
晶素子は、液晶層を狭持する一対の基板の一方の基板に
複数の走査電極が形成され、他方の基板に複数の信号電
極が走査電極の電極と平面的に交差するように形成さ
れ、走査電極と信号電極が平面的に交差する部分毎に非
線形抵抗素子及び画素電極が形成されている。Here, in a two-terminal active matrix liquid crystal element, a plurality of scanning electrodes are formed on one of a pair of substrates sandwiching a liquid crystal layer, and a plurality of signal electrodes are provided on the other substrate as scanning electrode electrodes. , A non-linear resistance element and a pixel electrode are formed at each portion where the scanning electrode and the signal electrode intersect in a plane.
【０００４】そして、走査電極を所定の選択期間づつ順
次選択し選択電圧を与え、これに同期して表示パターン
に応じて電圧変調された信号電圧を各信号電極に与える
駆動を行なっている。[0006] Then, the scanning electrodes are sequentially selected for a predetermined selection period, a selection voltage is applied, and a signal voltage modulated in accordance with a display pattern is applied to each signal electrode in synchronization with the selection voltage.
【０００５】[0005]
【発明が解決しようとする課題】ところで、これらのア
クティブマトリクス液晶素子において、好まざる表示む
らが発生する。In these active matrix liquid crystal elements, undesirable display unevenness occurs.
【０００６】例えば、縦棒を表示した際に縦方向に発生
する表示むら（以後縦クロストークと言う）について
は、Journal of the SID,2/2,1994 p75〜80に２端子型
アクティブマトリクス液晶素子を例にして、その発生機
構の説明と対策が提言されている。これによると、信号
電極とこれに対向している画素電極が作る画素容量（以
後、Ｃpと言う）と非線形素子の寄生容量（以後、Ｃsと
言う）が存在する為に、信号電極に印加する電圧がΔＶ
変化すると、画素容量に印加される電圧（以後、画素電
圧と言う）がΔＶ・Ｃs／（Ｃs＋Ｃp）変化する。従っ
て、表示パターンに応じて各信号電極に印加する電圧波
形が異なると、画素電圧、ひいては実効電圧に差異が生
じて縦クロストークをが発生するとしている。そして、
各選択期間の一部の期間に電圧変調された信号電圧を与
え残りの期間では信号電圧の中心電圧を総ての信号電極
に与えることにより縦クロストークを軽減させる方法が
提言されている。For example, display unevenness that occurs in the vertical direction when a vertical bar is displayed (hereinafter referred to as vertical crosstalk) is described in Journal of the SID, 2/2, 1994, p. Taking an element as an example, a description of its generating mechanism and a countermeasure have been proposed. According to this, since there is a pixel capacitance (hereinafter referred to as Cp) formed by a signal electrode and a pixel electrode opposed thereto and a parasitic capacitance (hereinafter referred to as Cs) of a non-linear element, the voltage is applied to the signal electrode. Voltage is ΔV
When the voltage changes, the voltage applied to the pixel capacitance (hereinafter referred to as pixel voltage) changes by ΔV · Cs / (Cs + Cp). Therefore, if the voltage waveform applied to each signal electrode differs according to the display pattern, a difference occurs in the pixel voltage and the effective voltage, and vertical crosstalk occurs. And
It has been proposed to reduce the vertical crosstalk by applying a voltage-modulated signal voltage to a part of each selection period and applying the center voltage of the signal voltage to all the signal electrodes in the remaining period.
【０００７】しかしながら、これらの対策だけでは完全
には縦クロストークを解消するに至っていない。However, these measures alone have not completely eliminated vertical crosstalk.
【０００８】そこで本発明者が鋭意研究調査した所、次
のような原因も縦クロストークの発生原因の１つである
ことが解った。The present inventors have conducted intensive research and found that the following causes are also one of the causes of vertical crosstalk.
【０００９】図４は、従来技術の２端子型アクティブマ
トリクス液晶素子の構造を示す概略図である。FIG. 4 is a schematic diagram showing the structure of a conventional two-terminal type active matrix liquid crystal element.
【００１０】図４において、１１は２端子型アクティブ
マトリクス液晶素子で、１、２は液晶層（図示せず）を
挟む一対の基板で、Ｙ１〜Ｙ５は基板１上に設けられた
複数の走査電極、Ｘ１〜Ｘ５は基板２上に設けられた信
号電極である。In FIG. 4, reference numeral 11 denotes a two-terminal type active matrix liquid crystal element, reference numerals 1 and 2 denote a pair of substrates sandwiching a liquid crystal layer (not shown), and Y1 to Y5 denote a plurality of scans provided on the substrate 1. The electrodes X1 to X5 are signal electrodes provided on the substrate 2.
【００１１】Ｓは非線形抵抗素子で、図では１箇所のみ
代表して記号を付してあるが、基板１上に走査電極Ｙ１
〜Ｙ５に接続されるように設けられている。非線形抵抗
素子Ｓとして、ここでは金属間に薄い絶縁膜を形成した
ＭＩＭ素子を用いているが、双方向性ダイオード特性を
持つ他の素子でも構わない。S is a non-linear resistance element, which is represented by a symbol at only one place in FIG.
To Y5. As the nonlinear resistance element S, an MIM element in which a thin insulating film is formed between metals is used here, but another element having bidirectional diode characteristics may be used.
【００１２】Ｐは画素電極で、図では１箇所のみ代表し
て記号を付してあるが、基板１上に、走査電極Ｙ１〜Ｙ
５に対して非線形抵抗素子Ｓを介して設けられている。P is a pixel electrode, which is denoted by a symbol at only one place in the figure.
5 is provided via a non-linear resistance element S.
【００１３】ここでは走査電極Ｙ１〜Ｙ５と信号電極Ｘ
１〜Ｘ５ともに５本と少ないが、これは図及び説明を簡
略化する為で、実際の液晶パネルでは通常それぞれ数百
本以上の数で構成されている。Here, scanning electrodes Y1 to Y5 and signal electrodes X
Each of the liquid crystal panels 1 to X5 has a small number of five, but this is for simplifying the drawing and the explanation, and an actual liquid crystal panel is usually composed of several hundreds or more.
【００１４】図５は図４の液晶素子１１のある走査電極
（ここではＹ１で代表している）に関する電気等価回路
を示す図で、Ｃpは画素電極Ｐが信号電極Ｘ１〜５の各
々と対向している部分とで形成する画素容量で、液晶層
が誘電体となっている。Ｃsは非線形抵抗素子Ｓに寄生
する容量である。そして、Ｃppは、画素電極間の容量で
ある。図では、画素容量Ｃp、寄生容量Ｃs、画素間容量
Ｃppは、代表して１箇所のみにその符号を付けてある。FIG. 5 is a diagram showing an electric equivalent circuit relating to a certain scanning electrode (represented here by Y1) of the liquid crystal element 11 of FIG. 4, and Cp denotes a pixel electrode P opposed to each of the signal electrodes X1 to X5. The liquid crystal layer is a dielectric formed by the pixel capacitance formed by the above-described portion. Cs is a capacitance parasitic on the nonlinear resistance element S. Cpp is the capacitance between the pixel electrodes. In the figure, the pixel capacitance Cp, the parasitic capacitance Cs, and the inter-pixel capacitance Cpp are represented at only one location by reference.
【００１５】各容量の大きさは無論、液晶素子１１の各
部の大きさに依存するが、例えば、ある液晶素子では、
Ｃp＝７５ｆＦ、Ｃs＝２０〜４０ｆＦ、Ｃpp＝６〜１０
ｆＦ程度であった。即ち、画素間容量Ｃppは画素容量Ｃ
pの１０％前後であった。The size of each capacitor depends, of course, on the size of each part of the liquid crystal element 11. For example, in a certain liquid crystal element,
Cp = 75 fF, Cs = 20-40 fF, Cpp = 6-10
It was about fF. That is, the inter-pixel capacitance Cpp is equal to the pixel capacitance Cpp.
It was around 10% of p.
【００１６】ここで、ある信号電極に印加する電圧がΔ
Ｖ変化すると、これに対向する画素電極の電圧は、ΔＶ
・Ｃp／（Ｃs＋Ｃp＋２・Ｃpp）だけ変化する。Here, the voltage applied to a certain signal electrode is Δ
When the voltage V changes, the voltage of the pixel electrode opposed thereto changes by ΔV
• Changes by Cp / (Cs + Cp + 2 · Cpp).
【００１７】更に、この画素電極の電圧変化によって隣
接する画素電極の電圧は、ΔＶ・Ｃp・Ｃpp／｛（Ｃs＋
Ｃp）（Ｃs＋Ｃp＋３・Ｃpp）｝だけ変化する。Further, the voltage of the adjacent pixel electrode is changed by the voltage change of the pixel electrode to ΔV · Cp · Cpp / ｛(Cs +
Cp) (Cs + Cp + 3 · Cpp)｝.
【００１８】これに先の具体的な数値を代入すると０.
０５・ΔＶ程度になる。よって、信号電極の電圧変化Δ
Ｖが数ボルトであることを考えると、隣接する画素電
極、言い換えるとこの画素電極が作る画素電圧に約百ｍ
Ｖの電圧の変化が発生することになり、縦クロストーク
を発生させる原因となる。By substituting the above specific values into this, it is assumed that
It becomes about 05 · ΔV. Therefore, the voltage change Δ of the signal electrode
Considering that V is several volts, the pixel voltage generated by the adjacent pixel electrode, in other words, the pixel electrode
A change in the voltage of V occurs, which causes vertical crosstalk.
【００１９】本発明は上のような課題に鑑みてなされた
もので、その目的は縦クロストークのない表示を行う液
晶素子を提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal device which performs display without vertical crosstalk.
【００２０】[0020]
【課題を解決するための手段】本発明の液晶素子は、液
晶層を狭持する一対の基板を有し、一方の前記基板上に
複数の第１の電極が形成され、他方の前記基板上に複数
の第２の電極が前記複数の第１の電極と平面的に交差す
るように形成され、前記第２の電極の各々に複数の非線
形抵抗素子が接続され、前記非線形素子を介して前記第
２の電極に接続される複数の画素電極が形成された液晶
素子において、前記他方の基板上に、隣り合う前記画素
電極の間に配置されるとともに前記第２の電極と平面的
に交差してなる複数の第３の電極が形成され、前記複数
の第３の電極は、互いに接続されてなることを特徴とす
る。A liquid crystal device according to the present invention has a pair of substrates sandwiching a liquid crystal layer, a plurality of first electrodes are formed on one of the substrates, and the other is formed on the other substrate. A plurality of second electrodes are formed so as to intersect the plurality of first electrodes in a plane, a plurality of non-linear resistance elements are connected to each of the second electrodes, and the In a liquid crystal element in which a plurality of pixel electrodes connected to a second electrode are formed, the liquid crystal element is disposed between the adjacent pixel electrodes on the other substrate and crosses the second electrode in a plane. A plurality of third electrodes are formed, and the plurality of third electrodes are connected to each other.
【００２１】[0021]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２２】〔第１の実施形態〕図１は本発明の液晶素
子の第１の実施形態を示す図、図２は、図１の液晶素子
１０を構成する基板１の構成を示す図、図３は図１の液
晶素子１０のある走査電極に関する電気等価回路を示す
図である。[First Embodiment] FIG. 1 is a diagram showing a first embodiment of a liquid crystal device of the present invention, and FIG. 2 is a diagram showing a configuration of a substrate 1 constituting a liquid crystal device 10 of FIG. FIG. 3 is a diagram showing an electric equivalent circuit relating to a certain scanning electrode of the liquid crystal element 10 of FIG.
【００２３】図１で、１０は２端子型アクティブマトリ
クス液晶素子であり、１、２は液晶層（図示せず）を挟
む一対の基板で、Ｙ１〜Ｙ５は基板１上に設けられた複
数の電極、Ｘ１〜Ｘ５は基板２上に設けられた電極であ
る。そして、Ｚ１〜Ｚ４は基板１上に設けられ、画素電
極Ｐの間に形成された電極である。In FIG. 1, reference numeral 10 denotes a two-terminal active matrix liquid crystal element, reference numerals 1 and 2 denote a pair of substrates sandwiching a liquid crystal layer (not shown), and Y1 to Y5 denote a plurality of substrates provided on the substrate 1. The electrodes X1 to X5 are electrodes provided on the substrate 2. Z1 to Z4 are electrodes provided on the substrate 1 and formed between the pixel electrodes P.
【００２４】Ｓは非線形抵抗素子で、図では１箇所のみ
代表して記号を付してあるが、基板１上に、電極Ｙ１〜
Ｙ５に接続するように設けられている。非線形抵抗素子
Ｓとして、本実施形態では金属間に薄い絶縁膜を形成し
たＭＩＭ素子を用いているが、双方向性ダイオード特性
を有する素子であれば何でも良い。Ｐは画素電極で、図
では１箇所のみ代表して記号を付してあるが、非線形抵
抗素子Ｓを介して電極Ｙ１〜Ｙ５に各々接続されて設け
られている。S is a non-linear resistance element, which is represented by a symbol at only one place in FIG.
It is provided to connect to Y5. In this embodiment, as the nonlinear resistance element S, an MIM element in which a thin insulating film is formed between metals is used, but any element having bidirectional diode characteristics may be used. P denotes a pixel electrode, which is represented by a symbol at only one place in the figure, but is provided to be connected to the electrodes Y1 to Y5 via the non-linear resistance element S.
【００２５】ここでは電極Ｙ１〜Ｙ５と電極Ｘ１〜Ｘ５
及びＺ１〜Ｚ４ともに４〜５本と少ないが、これは図及
び説明を簡略化する為で、実際の液晶パネルでは通常そ
れぞれ数百本以上の数で構成されている。Here, electrodes Y1 to Y5 and electrodes X1 to X5
And each of Z1 to Z4 is as small as 4 to 5, but this is for simplifying the drawing and the explanation, and the actual liquid crystal panel is usually composed of several hundreds or more.
【００２６】このような液晶素子において、図示しない
駆動回路から、これらの電極Ｙ１〜Ｙ５を所定の選択期
間づつ順次選択する選択電圧が供給され、これに同期し
て表示パターンに応じて電圧変調された信号電圧が電極
Ｘ１〜Ｘ５の各電極に供給される駆動が行われている。In such a liquid crystal element, a selection voltage for sequentially selecting these electrodes Y1 to Y5 for a predetermined selection period is supplied from a drive circuit (not shown), and the voltage is modulated in accordance with the display pattern in synchronization with the selection voltage. The driving is performed in which the applied signal voltage is supplied to each of the electrodes X1 to X5.
【００２７】図２は、見易いように図１の基板１の構成
のみを示す図で、符号の説明は図１と同じである。FIG. 2 shows only the structure of the substrate 1 of FIG. 1 for easy viewing, and the description of reference numerals is the same as that of FIG.
【００２８】ここで、電極Ｚ１〜Ｚ４の形状は、各画素
電極Ｐの間に入り込むように形成してある。言い換える
と、各画素電極Ｐの間に電極Ｚ１〜Ｚ４が必ず存在する
ように形成されている。なお、電極Ｙ１〜Ｙ５と電極Ｚ
１〜Ｚ４は絶縁されており、また電極Ｚ１〜Ｚ４は少な
くとも１箇所で総て導通がなされており、図１、２では
下端で導通がなされている。Here, the shapes of the electrodes Z1 to Z4 are formed so as to enter between the pixel electrodes P. In other words, the electrodes Z1 to Z4 are formed between the pixel electrodes P so as to be always present. The electrodes Y1 to Y5 and the electrode Z
The electrodes 1 to Z4 are insulated, and the electrodes Z1 to Z4 are all electrically connected at at least one place. In FIGS.
【００２９】以上の構成となっているので、図１の液晶
素子１０のある走査電極（ここではＹ１で代表してい
る）に関する電気等価回路は、図３に示すように、画素
電極Ｐが信号電極Ｘ１〜５の各々と対向している部分に
おいて、液晶層を誘電体とする画素容量Ｃpが形成さ
れ、非線形抵抗素子Ｓの寄生容量によるＣsが形成され
ている。そして、電極Ｚ１〜Ｚ４と画素電極Ｐ間にも容
量が形成され、これをＣpcとし、これを図に代表してそ
れぞれ１箇所に符号を付してある。With the above configuration, an electric equivalent circuit relating to a certain scanning electrode (represented here by Y1) of the liquid crystal element 10 in FIG. 1 is, as shown in FIG. At a portion facing each of the electrodes X1 to X5, a pixel capacitance Cp having a liquid crystal layer as a dielectric is formed, and Cs due to a parasitic capacitance of the nonlinear resistance element S is formed. A capacitance is also formed between the electrodes Z1 to Z4 and the pixel electrode P, which is designated as Cpc.
【００３０】この等価回路で示す容量Ｃpcの存在によっ
て、ある画素電極の電圧変化が隣接する画素電極に与え
る電圧変化の度合を軽減することができる。言い換えれ
ば、この電極Ｚ１〜Ｚ４が静電シールドとして働く。従
って、隣接する画素電極の電圧変化、ひいてはこの隣接
する画素電極が構成する画素容量の実効電圧変化が小さ
くなる。従って縦クロストークを著しく低減することが
出来る。The presence of the capacitance Cpc represented by the equivalent circuit can reduce the degree of the voltage change applied to an adjacent pixel electrode due to a voltage change of one pixel electrode. In other words, these electrodes Z1 to Z4 function as an electrostatic shield. Therefore, a change in voltage of an adjacent pixel electrode and a change in effective voltage of a pixel capacitor formed by the adjacent pixel electrode are reduced. Therefore, vertical crosstalk can be significantly reduced.
【００３１】なお、図１では電極Ｚ１〜Ｚ４と画素間に
隙間がある場合を示しているが、この隙間の必要は無
く、例えば電極Ｚ１〜Ｚ４上が絶縁されていれば重なっ
ても良い。Although FIG. 1 shows a case where there is a gap between the electrodes Z1 to Z4 and the pixel, there is no need for this gap.
【００３２】また、電極Ｚ１〜Ｚ４の部材として酸化イ
ンジウムや酸化錫等の透明な導電部材で形成することに
よって、液晶素子が暗くなるのを防ぐことが出来る。Further, by forming the electrodes Z1 to Z4 from a transparent conductive member such as indium oxide or tin oxide, the liquid crystal element can be prevented from becoming dark.
【００３３】更に、図１、２では電極Ｚ１〜Ｚ４が電極
Ｙ１〜Ｙ５の上に形成してある場合を示しているが、電
極Ｙ１〜Ｙ５の下層になるように形成しても良い。Further, FIGS. 1 and 2 show the case where the electrodes Z1 to Z4 are formed on the electrodes Y1 to Y5, but they may be formed below the electrodes Y1 to Y5.
【図１】本発明の液晶表示装置を構成する液晶素子の第
１の実施形態を示す図。FIG. 1 is a diagram showing a first embodiment of a liquid crystal element constituting a liquid crystal display device of the present invention.
【図２】本発明の第１の実施形態における基板１の構成
を示す図。FIG. 2 is a diagram showing a configuration of a substrate 1 according to the first embodiment of the present invention.
【図３】図１の液晶素子１０の電気等価回路を示す図。FIG. 3 is a diagram showing an electric equivalent circuit of the liquid crystal element 10 of FIG.
【図４】従来技術の液晶素子の一構成例を示す図。FIG. 4 is a diagram showing a configuration example of a conventional liquid crystal element.
【図５】従来技術の液晶素子の電気等価回路を示す図。FIG. 5 is a diagram showing an electric equivalent circuit of a conventional liquid crystal element.
１・・・基板 ２・・・基板 １０・・・液晶素子 Ｘ１〜Ｘ５・・・基板２上の電極 Ｙ１〜Ｙ５・・・基板１上の電極 Ｚ１〜Ｚ４・・・基板１上の電極 Ｓ・・・非線形抵抗素子 Ｐ・・・画素電極 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Substrate 10 ... Liquid crystal element X1-X5 ... Electrode on substrate 2 Y1-Y5 ... Electrode on substrate 1 Z1-Z4 ... Electrode on substrate 1 S ... Non-linear resistance element P ... Pixel electrode
Claims (1)
の前記基板上に複数の第１の電極が形成され、他方の前
記基板上に複数の第２の電極が前記複数の第１の電極と
平面的に交差するように形成され、前記第２の電極の各
々に複数の非線形抵抗素子が接続され、前記非線形素子
を介して前記第２の電極に接続される複数の画素電極が
形成された液晶表示装置において、前記他方の基板上
に、隣り合う前記画素電極の間に配置されるとともに前
記第２の電極と平面的に交差してなる複数の第３の電極
が形成され、前記複数の第３の電極は、互いに接続され
てなることを特徴とする液晶表示装置。A plurality of first electrodes formed on one of the substrates, and a plurality of second electrodes formed on the other one of the substrates. A plurality of pixels formed so as to intersect the first electrode in a plane, a plurality of non-linear resistance elements being connected to each of the second electrodes, and a plurality of pixels being connected to the second electrode via the non-linear elements; In a liquid crystal display device having electrodes formed thereon, a plurality of third electrodes which are arranged between the adjacent pixel electrodes and intersect with the second electrodes in a plane are formed on the other substrate. The liquid crystal display device, wherein the plurality of third electrodes are connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14635798A JP3744203B2 (en) | 1998-05-27 | 1998-05-27 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14635798A JP3744203B2 (en) | 1998-05-27 | 1998-05-27 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11337981A true JPH11337981A (en) | 1999-12-10 |
| JP3744203B2 JP3744203B2 (en) | 2006-02-08 |
Family
ID=15405897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14635798A Expired - Fee Related JP3744203B2 (en) | 1998-05-27 | 1998-05-27 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3744203B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6850307B2 (en) | 2000-02-18 | 2005-02-01 | Seiko Epson Corporation | Display device substrate, method for manufacturing the display device substrate, liquid-crystal display device, and electronic equipment |
| JP2006259244A (en) * | 2005-03-17 | 2006-09-28 | Seiko Epson Corp | Liquid crystal display device, manufacturing method for liquid crystal display device, and electronic equipment |
-
1998
- 1998-05-27 JP JP14635798A patent/JP3744203B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6850307B2 (en) | 2000-02-18 | 2005-02-01 | Seiko Epson Corporation | Display device substrate, method for manufacturing the display device substrate, liquid-crystal display device, and electronic equipment |
| US6922225B2 (en) | 2000-02-18 | 2005-07-26 | Seiko Epson Corporation | Display device substrate, method for manufacturing the display device substrate, liquid-crystal device, and electronic equipment |
| US6924867B2 (en) | 2000-02-18 | 2005-08-02 | Seiko Epson Corporation | Display device substrate, method for manufacturing the display device substrate, liquid-crystal device, and electronic equipment |
| JP2006259244A (en) * | 2005-03-17 | 2006-09-28 | Seiko Epson Corp | Liquid crystal display device, manufacturing method for liquid crystal display device, and electronic equipment |
| JP4665571B2 (en) * | 2005-03-17 | 2011-04-06 | セイコーエプソン株式会社 | Liquid crystal device, method for manufacturing liquid crystal device, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3744203B2 (en) | 2006-02-08 |
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