JPH11220089A - Chip module - Google Patents
Chip moduleInfo
- Publication number
- JPH11220089A JPH11220089A JP3212698A JP3212698A JPH11220089A JP H11220089 A JPH11220089 A JP H11220089A JP 3212698 A JP3212698 A JP 3212698A JP 3212698 A JP3212698 A JP 3212698A JP H11220089 A JPH11220089 A JP H11220089A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- module
- electrode
- semiconductor
- passive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体と受動部品か
ら成る回路モジュールにおいて、モジュールの小型化が
可能で、なおかつ実装端子などによる高周波特性の劣化
のないチップモジュールに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit module comprising a semiconductor and passive components, and more particularly to a chip module which can be downsized and whose high-frequency characteristics are not deteriorated by mounting terminals and the like.
【０００２】[0002]
【従来の技術】電子機器の小型化に伴い、ＬＳＩなどで
はワイヤーボンディングやフリップチップ実装などによ
る省スペース化が進んでいるが、個別半導体（トランジ
スタ、ダイオードなど）の場合はそれ以外の受動部品
（抵抗、コンデンサ、インダクタ）と組み合わせて回路
を構成するため省スペース化の効果が小さく、またベア
チップ実装と半田実装との混在による品質上の問題があ
り行われていなかった。2. Description of the Related Art Along with the miniaturization of electronic equipment, space saving has been progressed by wire bonding and flip-chip mounting in LSIs and the like. (Circuit, resistor, inductor, inductor)), so that the effect of space saving is small, and there is no quality problem due to the mixture of bare chip mounting and solder mounting.
【０００３】受動部品に薄膜などによるワイヤーボンデ
ィング対応の部品を用い、ベアチップ実装ハイブリッド
ＩＣ化する方法があるが、マザーボードと接続するため
の端子などによって高周波特性が劣化するという問題が
ある。There is a method of forming a hybrid IC mounted on a bare chip by using a component compatible with wire bonding using a thin film or the like as a passive component. However, there is a problem that high frequency characteristics are deteriorated by a terminal for connecting to a motherboard.
【０００４】ＩＣの場合フリップチップ実装により省ス
ペース化だけではなく高周波特性の改善が可能である
が、個別半導体はチップ裏面の電極と周辺の受動部品と
の接続が必要であるためフリップチップ実装が不可能で
ある。[0004] In the case of an IC, flip-chip mounting not only saves space but also improves high-frequency characteristics. However, flip-chip mounting is required because individual semiconductors require connection between electrodes on the back of the chip and peripheral passive components. Impossible.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、半導体と受
動部品からなる回路モジュールの上記のような問題を改
善するためになされたもので、回路モジュールの小型化
を図るとともに高周波特性の劣化のないモジュールを提
供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of a circuit module comprising a semiconductor and a passive component. Try to provide no modules.
【０００６】[0006]
【課題を解決するための手段】半導体と受動部品から成
る回路モジュールのフリップチップ実装を可能にする方
法として、モジュールの基材上にベアチップ半導体およ
びチップ上面にボンディング対応の電極を有する薄膜受
動素子チップを実装し、個別半導体チップ上面と周辺の
受動部品の電極を同一平面上に配置することにより、各
部品のマザーボードへのバンプによる接続が可能とな
る。As a method for enabling a flip-chip mounting of a circuit module comprising a semiconductor and a passive component, a thin-film passive element chip having a bare chip semiconductor on a base material of the module and electrodes for bonding on the upper surface of the chip is provided. By mounting the individual semiconductor chip upper surface and the electrodes of the peripheral passive components on the same plane, it is possible to connect each component to the motherboard by bumps.
【０００７】個別半導体のように半導体裏面の電極とマ
ザーボードとの接続を行なう必要がある場合、半導体裏
面が接続されているモジュール基材のパターン上に導電
性を有する金属チップを実装し、該金属チップを介して
マザーボードとのバンプ接続を行なう。When it is necessary to connect the electrode on the backside of the semiconductor and the motherboard like an individual semiconductor, a conductive metal chip is mounted on the pattern of the module base to which the backside of the semiconductor is connected, and the metal The bump connection with the motherboard is made via the chip.
【０００８】[0008]
【作用および効果】半導体と受動部品から成るチップモ
ジュールをフリップチップ実装することにより、モジュ
ールとマザーボードを接続するための実装端子が不要と
なり省スペース化が可能となるだけでなく、モジュール
内部で行なっていたワイヤー配線がマザーボード上で行
なえることによりモジュール基材上のボンディングパッ
ドも不要となり、より省スペース化が可能となる。[Function and Effect] By mounting a chip module including a semiconductor and a passive component by flip-chip mounting, mounting terminals for connecting the module and the motherboard are not required, so that space can be saved, and the chip module is mounted inside the module. Since the wired wiring can be performed on the motherboard, the bonding pads on the module base material are not required, and the space can be further reduced.
【０００９】チップモジュールとマザーボードはバンプ
により接続されるため、従来のモジュールのワイヤー配
線や接続端子による高周波特性の劣化がない。Since the chip module and the motherboard are connected by bumps, there is no deterioration in high-frequency characteristics due to wire wiring and connection terminals of the conventional module.
【００１０】[0010]
【発明の実施の形態】次に本発明の実施例について図面
を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.
【００１１】[0011]
【実施例１】図１に本発明によるチップモジュールの例
を示す。このチップモジュールはモジュールの基材１、
基材上に設けられた配線パターン２、ベアチップ半導体
３、ボンディング対応電極４を有する受動部品チップ５
から構成される。受動部品５の電極がベアチップ半導体
３のチップ上面電極と同一平面になるよう受動部品５の
チップの高さが決定されている。これらのチップ部品の
電極を金または半田などのバンプ６を介して図２に示す
ようにマザーボード７にフリップチップ実装される。Embodiment 1 FIG. 1 shows an example of a chip module according to the present invention. This chip module is a substrate 1 of the module,
Passive component chip 5 having wiring pattern 2, bare chip semiconductor 3, and bonding-compatible electrode 4 provided on base material
Consists of The chip height of the passive component 5 is determined so that the electrode of the passive component 5 is flush with the chip upper surface electrode of the bare chip semiconductor 3. The electrodes of these chip components are flip-chip mounted on a motherboard 7 via bumps 6 such as gold or solder as shown in FIG.
【００１２】図３では受動部品チップ５ａはチップ基材
の上面にコンデンサおよび抵抗を形成した薄膜複合部品
で、受動部品チップ５ｂは高誘電体基材の両面に電極を
形成した単板式コンデンサである。このように実装する
受動部品はチップモジュールを構成する上で配線が最も
しやすいように複合化や種類の選択を行なうことができ
る。In FIG. 3, the passive component chip 5a is a thin film composite component having a capacitor and a resistor formed on the upper surface of a chip base material, and the passive component chip 5b is a single plate type capacitor having electrodes formed on both surfaces of a high dielectric base material. . The passive components mounted in this manner can be combined and selected in a type so that wiring is most easily performed in configuring a chip module.
【００１３】[0013]
【実施例２】半導体の裏面電極から受動部品を介さず直
接マザーボードに接続する場合の実施例を図４に示す。
半導体３の裏面電極が接続されている配線パターン２の
上に導電性を有する金属チップ８を実装し該金属チップ
を介してマザーボード７と電気的に接続される。Embodiment 2 FIG. 4 shows an embodiment in the case where a connection is made directly from the back electrode of the semiconductor to the motherboard without using a passive component.
A conductive metal chip 8 is mounted on the wiring pattern 2 to which the back electrode of the semiconductor 3 is connected, and is electrically connected to the motherboard 7 via the metal chip.
【００１４】[0014]
【実施例３】モジュール基材１にグランドパターン９を
形成し該グランドパターンを金属チップ８を介してマザ
ーボード７のグランドパターン１０に接続することによ
りモジュールにシールド効果を持たせた実施例を図５に
示す。発振回路やフィルタのようにノイズに対して敏感
な回路に適しているだけでなく、モジュール基材１上に
グランド層があるため、マイクロストリップラインによ
る高周波回路の形成が可能となる。Embodiment 3 An embodiment in which a ground effect is formed on a module by forming a ground pattern 9 on the module substrate 1 and connecting the ground pattern to a ground pattern 10 of the motherboard 7 via a metal chip 8 is shown in FIG. Shown in Not only is it suitable for a circuit that is sensitive to noise such as an oscillation circuit and a filter, but also because a ground layer is provided on the module substrate 1, a high-frequency circuit can be formed by a microstrip line.
【００１５】[0015]
【発明の効果】本発明のチップモジュールによれば、個
別半導体と受動部品から成る回路ブロックのフリップチ
ップ実装が可能となり、省スペース化を図るとともに良
好な高周波特性を得ることが出来る。According to the chip module of the present invention, it is possible to mount a circuit block composed of individual semiconductors and passive components by flip-chip mounting, thereby saving space and obtaining good high-frequency characteristics.
【図１】実施例１のチップモジュールの斜視図FIG. 1 is a perspective view of a chip module according to a first embodiment.
【図２】チップモジュールの実装状態FIG. 2 is a mounting state of a chip module.
【図３】チップモジュールに使用する受動部品チップの
例FIG. 3 shows an example of a passive component chip used in a chip module.
【図４】実施例２のチップモジュールFIG. 4 is a chip module according to a second embodiment.
【図５】実施例３のチップモジュールFIG. 5 is a chip module according to a third embodiment;
１ モジュール基材 ２ 基材上の配線パターン ３ ベアチップ半導体 ４ ボンディング対応電極 ５ 受動部品 ６ バンプ ７ マザーボード ８ 金属チップ ９ 基材上のグランドパターン １０ マザーボード上のグランドパターン DESCRIPTION OF SYMBOLS 1 Module base material 2 Wiring pattern on base material 3 Bare chip semiconductor 4 Bonding electrode 5 Passive component 6 Bump 7 Motherboard 8 Metal chip 9 Ground pattern on base material 10 Ground pattern on motherboard
Claims (2)
ジュールにおいて、モジュール基材上にベアチップ半導
体とボンディング対応の電極を有する受動部品を実装す
ることによりチップモジュールを構成し、実装された各
チップ部品の電極上に形成したバンプによってマザーボ
ードに電気的に接続することを特徴とするチップモジュ
ール。In a circuit module comprising a semiconductor element and a passive component, a chip module is formed by mounting a passive component having a bare chip semiconductor and an electrode corresponding to bonding on a module base material, and a chip module of each mounted chip component is formed. A chip module electrically connected to a motherboard by bumps formed on electrodes.
に接続する電極があるチップモジュールにおいて、モジ
ュール基材の電極上に導電性の金属チップを実装し、該
金属チップ上に形成したバンプにより、マザーボードと
の電気的接続を行なうことを特徴とするチップモジュー
ル。2. A chip module having electrodes electrically connected to a motherboard on a module substrate, wherein a conductive metal chip is mounted on the electrodes of the module substrate, and a bump formed on the metal chip is A chip module for making an electrical connection to a motherboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3212698A JPH11220089A (en) | 1998-01-29 | 1998-01-29 | Chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3212698A JPH11220089A (en) | 1998-01-29 | 1998-01-29 | Chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11220089A true JPH11220089A (en) | 1999-08-10 |
Family
ID=12350203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3212698A Pending JPH11220089A (en) | 1998-01-29 | 1998-01-29 | Chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11220089A (en) |
-
1998
- 1998-01-29 JP JP3212698A patent/JPH11220089A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040618 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051216 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051222 |
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| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060912 |