JPH05211279A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH05211279A
JPH05211279A JP3303671A JP30367191A JPH05211279A JP H05211279 A JPH05211279 A JP H05211279A JP 3303671 A JP3303671 A JP 3303671A JP 30367191 A JP30367191 A JP 30367191A JP H05211279 A JPH05211279 A JP H05211279A
Authority
JP
Japan
Prior art keywords
thin film
pellet
integrated circuit
board
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3303671A
Other languages
Japanese (ja)
Inventor
Shingo Kawashima
進吾 川島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3303671A priority Critical patent/JPH05211279A/en
Publication of JPH05211279A publication Critical patent/JPH05211279A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To perform a high frequency operation and to achieve high density mounting by fixing a semiconductor pellet to a thin film board in a shape in which an active element is opposed to a passive element. CONSTITUTION:The hybrid integrated circuit comprises a semiconductor pellet 1 having an active element such as a transistor, etc., on a thick film board 3, and a thin film board 2 having a passive element fixed to a solder bump 4 on the pellet 1. The pellet 1 is electrically connected to the board 3 by bonding a gold wire 5. The passive element such as a resistor, a capacitor, etc., which affects high frequency characteristics of electric functions of the pellet 1 is fundamentally formed of a thin film pattern coping with a high frequency on the board 2, and the board 2 is so connected to the pellet 1 by the bump 4 so that the passive element is opposed to the active element. Thus, it can be connected without parasitic element such as unnecessary inductance, etc., between the active elements.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は混成集積回路に関し、特
に、高周波動作且つ高密度実装の必要な混成集積回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit that requires high frequency operation and high density packaging.

【０００２】[0002]

【従来の技術】従来の混成集積回路で、高密度実装が必
要なものについては、厚膜多層基板（多層セラミック基
板または多層有機基板）を用いて実装密度をたかめてい
る。また高周波動作の必要なものについては、導体や抵
抗等の受動素子が表面に形成された薄膜基板により対応
しているのが一般的である。2. Description of the Related Art For a conventional hybrid integrated circuit that requires high density mounting, a thick film multilayer substrate (multilayer ceramic substrate or multilayer organic substrate) is used to increase the packaging density. For high-frequency operation, a thin film substrate on the surface of which passive elements such as conductors and resistors are formed is generally used.

【０００３】このように従来の混成集積回路では、高密
度化への対応基板技術としては、多層厚膜基板が主に用
いられており、また、高周波化に対する基板としては、
薄膜基板が用いられているが、高密度化及び高周波数化
の両者を同時に満たそうとすると、厚膜多層基板では、
配線抵抗が高くなりすぎ高周波動作が難しくなってしま
い、一方薄膜基板では集積度を上げようとすると、実用
的な価格の上限をこえてしまう。As described above, in the conventional hybrid integrated circuit, a multilayer thick film substrate is mainly used as a substrate technology for high density, and as a substrate for high frequency,
Although a thin film substrate is used, when trying to satisfy both high density and high frequency at the same time, in a thick film multilayer substrate,
The wiring resistance becomes too high, making it difficult to operate at high frequencies. On the other hand, if the degree of integration is to be increased in a thin film substrate, the practical upper limit of the price will be exceeded.

【０００４】従来から、このように点を改良することを
目的として、図３に示すように、厚膜多層基板３上に薄
膜基板２を半導体ペレット１と共に部品として搭載し、
両者の特長を引きだそうとした構造の製品が作られてい
る。Conventionally, for the purpose of improving the above point, as shown in FIG. 3, a thin film substrate 2 is mounted on a thick film multilayer substrate 3 together with a semiconductor pellet 1 as a component,
Products with structures designed to bring out the features of both are made.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、図３に
示した従来の混成集積回路では、厚膜多層基板３と薄膜
基板２の接続のためには、金ワイヤ５やフェースダウン
による半田７により接続を行なっているが、高周波特性
上最も重要な半導体ペレット１との接続には、どうして
も厚膜多層基板３上に形成された厚膜導体８を経由する
ことになり、周波数帯域が１００ＭＨｚをこえる高周波
においては、表皮効果により抵抗値が上るため、要求特
性を満たせなくなることがしばしば発生している。特に
ワイヤボンディングについては、その金ワイヤの形状自
体が特性に大きな影響を与えてしまい、製品の特性がば
らつき、混成集積回路の信頼性や歩留りを低下させると
いう問題点がある。However, in the conventional hybrid integrated circuit shown in FIG. 3, in order to connect the thick film multilayer substrate 3 and the thin film substrate 2, the gold wire 5 and the face down solder 7 are used for connection. However, the connection with the semiconductor pellet 1, which is most important in terms of high frequency characteristics, must be via the thick film conductor 8 formed on the thick film multilayer substrate 3, and the high frequency band exceeding 100 MHz. In the above, since the resistance value increases due to the skin effect, it often happens that the required characteristics cannot be satisfied. Particularly in the case of wire bonding, there is a problem that the shape itself of the gold wire greatly affects the characteristics, the characteristics of the product are varied, and the reliability and yield of the hybrid integrated circuit are reduced.

【０００６】本発明の目的は、高周波動作が可能で且
つ、高密度実装ができる混成集積回路を提供することに
ある。An object of the present invention is to provide a hybrid integrated circuit capable of high frequency operation and high density packaging.

【０００７】[0007]

【課題を解決するための手段】第１の発明の混成集積回
路は、厚膜多層基板上に固着された少くとも能動素子を
有する半導体ペレットと、この半導体ペレット上に固着
された受動素子を有する薄膜基板とを含むものである。A hybrid integrated circuit according to a first aspect of the present invention includes a semiconductor pellet having at least an active element fixed on a thick film multilayer substrate, and a passive element fixed on the semiconductor pellet. It includes a thin film substrate.

【０００８】第２の発明の混成集積回路は、厚膜多層基
板上に固着された受動素子を有する薄膜基板と、この薄
膜基板上に固着された少くとも能動素子を有する半導体
ペレットとを含むものである。The hybrid integrated circuit of the second invention includes a thin film substrate having a passive element fixed on a thick film multilayer substrate and a semiconductor pellet having at least an active element fixed on the thin film substrate. ..

【０００９】[0009]

【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の第１の実施例の断面図である。The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the first embodiment of the present invention.

【００１０】図１において混成集積回路は、厚膜多層基
板３上に半田等により固着された少くともトランジスタ
等の能動素子を有する半導体ペレット１と、この半導体
ペレット１の上に半田バンプ４により固着された受動素
子を有する薄膜基板２とから主に構成されている。半導
体ペレット１は金ワイヤ５のボンディングによって厚膜
多層基板３上に電気的に接続をされている。薄膜基板２
には半導体ペレット１の電気的機能のうち特に高周波特
性を左右するような抵抗やコンデンサ等の受動素子を基
本的に高周波対応の薄膜パターンで形成してあり、この
薄膜基板２を受動素子が能動素子に向い合うように半田
バンプ４により半導体ペレット１に接続する。このこと
により、機能素子間に不要なインダクタンス等の寄生素
子の生じることなく接続することができる。In FIG. 1, the hybrid integrated circuit has a semiconductor pellet 1 having at least active elements such as transistors fixed on a thick film multilayer substrate 3 by solder or the like, and fixed on the semiconductor pellet 1 by solder bumps 4. And a thin film substrate 2 having a passive element formed therein. The semiconductor pellet 1 is electrically connected to the thick film multilayer substrate 3 by bonding a gold wire 5. Thin film substrate 2
Among the electrical functions of the semiconductor pellet 1, passive elements such as resistors and capacitors which influence the high frequency characteristics are formed basically in a thin film pattern corresponding to high frequencies, and the thin film substrate 2 is used as an active element. It is connected to the semiconductor pellet 1 by a solder bump 4 so as to face the element. As a result, the functional elements can be connected without generating parasitic elements such as unnecessary inductance.

【００１１】このように高周波特性の重要な部分につい
て回路構成のできた状態で、半導体ペレット１を厚膜多
層基板３に金ワイヤ５でボンディングにより接続する。
この際、半導体ペレット１の接続を金ワイヤのボンディ
ングでおこなえるのは、重要な高周波特性については既
に薄膜基板２との間で完了しているので、ここでは金ワ
イヤの長さを１ｍｍを越えるようなボンディングを行な
っても特性に影響を与えることはない。また、厚膜多層
基板３として、セラミックの多層基板を用いることによ
り、全体としての高集積化を実現する事が可能となる。In this manner, the semiconductor pellet 1 is connected to the thick film multilayer substrate 3 by the gold wire 5 by bonding in a state where the circuit configuration is completed for the important part of the high frequency characteristic.
At this time, the semiconductor pellet 1 can be connected by gold wire bonding because the important high-frequency characteristics have already been completed with the thin film substrate 2, so the length of the gold wire is set to exceed 1 mm. Bonding does not affect the characteristics. Further, by using a ceramic multilayer substrate as the thick film multilayer substrate 3, it is possible to realize high integration as a whole.

【００１２】図２は本発明の第２の実施例の断面図であ
る。薄膜基板２Ａの上に半田バンプ４による接続で半導
体ペレット１Ａを搭載し、薄膜基板２Ａはさらに薄膜基
板内部に形成したスルーホール６をかいして半田７によ
って厚膜多層基板３上に電気的に接続されている。FIG. 2 is a sectional view of the second embodiment of the present invention. The semiconductor pellet 1A is mounted on the thin film substrate 2A by connection with the solder bumps 4, and the thin film substrate 2A is electrically connected to the thick film multilayer substrate 3 by solder 7 through the through holes 6 formed inside the thin film substrate. It is connected.

【００１３】この第２の実施例は、半導体ペレット１Ａ
の接続は全て薄膜基板２Ａをかいしておこなわれること
になる。従って第１の実施例に比べ、金ワイヤのボンデ
ィングに要する領域だけ厚膜多層基板の面積を少くでき
るため、集積度を向上させることができる。The second embodiment is a semiconductor pellet 1A.
All of the connections will be made through the thin film substrate 2A. Therefore, as compared with the first embodiment, the area of the thick film multilayer substrate can be reduced only in the region required for bonding the gold wire, so that the degree of integration can be improved.

【００１４】[0014]

【発明の効果】以上説明したように本発明は、薄膜基板
と半導体ペレットを半田バンプにより接続した後に、厚
膜多層基板に搭載する構造としたので、高価な薄膜基板
の使用量を少なくできるとともに、半田バンプ接続で高
周波特性の改善を図っているため、従来の薄膜基板のみ
を用いた場合と同等の高周波特性に選ぐれ、かつ厚膜多
層基板をも使用する事によって、高集積化を比較的低価
格で実現する事ができるという効果を有する。従って混
成集積回路の信頼性及び歩留りは向上する。As described above, according to the present invention, since the thin film substrate and the semiconductor pellet are connected by the solder bumps and then mounted on the thick film multilayer substrate, the amount of the expensive thin film substrate used can be reduced. Since the high frequency characteristics are improved by solder bump connection, the high frequency characteristics are selected to be equivalent to the case where only the conventional thin film substrate is used, and the high integration is compared by using the thick film multilayer substrate. It has the effect that it can be realized at a relatively low price. Therefore, the reliability and yield of the hybrid integrated circuit are improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図２】本発明の第２の実施例の断面図。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図３】従来の混成集積回路の一例の断面図。FIG. 3 is a sectional view of an example of a conventional hybrid integrated circuit.

【符号の説明】[Explanation of symbols]

１，１Ａ 半導体ペレット ２，２Ａ 薄膜基板 ３ 厚膜多層基板 ４ 半田バンプ ５ 金ワイヤ ６ スルーホール ７ 半田 1,1A Semiconductor pellet 2,2A Thin film substrate 3 Thick film multilayer substrate 4 Solder bump 5 Gold wire 6 Through hole 7 Solder

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 厚膜多層基板上に固着された少くとも能
動素子を有する半導体ペレットと、この半導体ペレット
上に固着された受動素子を有する薄膜基板とを含むこと
を特徴とする混成集積回路。1. A hybrid integrated circuit comprising: a semiconductor pellet having at least an active element fixed on a thick film multilayer substrate; and a thin film substrate having a passive element fixed on the semiconductor pellet. 【請求項２】 厚膜多層基板上に固着された受動素子を
有する薄膜基板と、この薄膜基板上に固着された少くと
も能動素子を有する半導体ペレットとを含むことを特徴
とする混成集積回路。2. A hybrid integrated circuit comprising: a thin film substrate having a passive element adhered onto a thick film multilayer substrate; and a semiconductor pellet having at least an active element adhered onto the thin film substrate. 【請求項３】 能動素子と受動素子とは向い合う形状に
半導体ペレットと薄膜基板とが固着されている請求項１
または請求項２記載の混成集積回路。3. The semiconductor pellet and the thin film substrate are fixed to each other so that the active element and the passive element face each other.
Alternatively, the hybrid integrated circuit according to claim 2.
JP3303671A 1991-11-20 1991-11-20 Hybrid integrated circuit Withdrawn JPH05211279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3303671A JPH05211279A (en) 1991-11-20 1991-11-20 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3303671A JPH05211279A (en) 1991-11-20 1991-11-20 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH05211279A true JPH05211279A (en) 1993-08-20

Family

ID=17923830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3303671A Withdrawn JPH05211279A (en) 1991-11-20 1991-11-20 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH05211279A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998013873A1 (en) * 1996-09-27 1998-04-02 The Whitaker Corporation Integrated emitter drain bypass capacitor for microwave/rf power device applications
US5883422A (en) * 1996-06-28 1999-03-16 The Whitaker Corporation Reduced parasitic capacitance semiconductor devices
JP2005117038A (en) * 2003-10-03 2005-04-28 Agilent Technol Inc Integrated circuit and integrated circuit assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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