JPH11219950A - Manufacture of semiconductor integrated circuit and manufacturing device thereof - Google Patents
Manufacture of semiconductor integrated circuit and manufacturing device thereofInfo
- Publication number
- JPH11219950A JPH11219950A JP2174198A JP2174198A JPH11219950A JP H11219950 A JPH11219950 A JP H11219950A JP 2174198 A JP2174198 A JP 2174198A JP 2174198 A JP2174198 A JP 2174198A JP H11219950 A JPH11219950 A JP H11219950A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- silicon oxide
- plasma
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体集積回路の製
造方法に係り、特に高アスペクト比の微細なトレンチや
配線パターン間の溝をボイドを生じることなく絶縁膜で
完全に充填し、高集積化や高信頼化に好適な半導体集積
回路の誘電体絶縁分離基板や多層配線用層間絶縁膜の製
造方法並びにその製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for completely filling a fine trench having a high aspect ratio or a groove between wiring patterns with an insulating film without generating a void, thereby achieving high integration. The present invention relates to a method of manufacturing a dielectric insulating separation substrate of a semiconductor integrated circuit and an interlayer insulating film for multilayer wiring suitable for high reliability and an apparatus for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体集積回路の高集積化に伴う微細化
により、トレンチ溝や配線間隔が小さくなり、アスペク
ト比（溝の縦寸法／横寸法の比）が大きくなる。誘電体
絶縁分離層や配線層の高信頼化のためには、トレンチや
配線間の溝を絶縁物で充填することが望ましい。これ
は、配線間等の溝部のボイドが生ずる不具合−以降のプ
ロセス工程における薬品の侵入や反応ガスの吸着、デバ
イス完成後の水分等の浸入吸着による、金属配線材料の
腐食や層間絶縁膜の変質に伴う素子特性の変動等を防止
するためである。2. Description of the Related Art With the miniaturization accompanying the high integration of semiconductor integrated circuits, trench grooves and wiring intervals are reduced, and the aspect ratio (ratio of vertical dimension / horizontal dimension of the groove) is increased. In order to increase the reliability of the dielectric insulating separation layer and the wiring layer, it is desirable to fill the trench and the groove between the wirings with an insulator. This is due to the problem of voids in the grooves between the wirings, etc.-Corrosion of metal wiring materials and deterioration of interlayer insulating films due to intrusion of chemicals and adsorption of reactive gas in subsequent process steps, and intrusion of water and the like after device completion. This is to prevent the fluctuation of the element characteristics due to the above.
【０００３】配線間等の溝部を充填する方法は種々提案
されている。そのうち、高密度プラズマＣＶＤにおい
て、成膜時に基板に高周波または直流バイアスを印加す
ることにより、ＣＶＤによる薄膜堆積と同時にプラズマ
中の加速されたイオンによりスパッタエッチングを生じ
させる方法が用いられている。これは、スパッタエッチ
ングの速度はイオン照射角度に依存し、約４５°付近が
ピークとなり、垂直面や平坦面はほとんどエッチングさ
れないため、配線層エッジ部やトレンチ開口部の（オー
バーハング部）の堆積物が選択的にスパッタエッチング
され、また、スパッタされた堆積物が溝部内面に再付着
するため溝埋めできる。Various methods have been proposed for filling grooves between wirings and the like. Among them, in high-density plasma CVD, a method of applying a high frequency or direct current bias to a substrate at the time of film formation to generate sputter etching by accelerated ions in plasma simultaneously with deposition of a thin film by CVD is used. This is because the sputter etching rate depends on the ion irradiation angle, and peaks at about 45 °, and almost no vertical or flat surface is etched. The material is selectively sputter-etched, and the groove can be filled because the sputtered deposit adheres again to the inner surface of the groove.
【０００４】この方式をより効率的に実施するため、各
種の改良策が提案されている。これらに関係するものに
は、例えば、特開昭56−13480号公報，特開昭63−25724
6 号(特許登録第2539422号）公報，特開平2−310926号
（特許登録第2514250号）公報，特開平8−148486号公報
等が挙げられる。Various improvements have been proposed to more efficiently implement this method. Related to these are, for example, JP-A-56-13480 and JP-A-63-25724.
No. 6 (Patent Registration No. 2539422), JP-A-2-310926 (Patent Registration No. 2514250), and JP-A-8-148486.
【０００５】[0005]
【発明が解決しようとする課題】半導体集積回路の高集
積化に伴い、トレンチや配線層パターンの微細化と溝部
のアスペクト比が大きくなってきている。上記の従来技
術では、アスペクト比２.５ 以下の溝部にはボイドフリ
ーの溝埋めが可能である。しかし、アスペクト比がそれ
以上になるとオーバーハング部の堆積物はスパッタされ
るが、対抗面に再付着され結局開口部が塞がれて溝底部
にボイドが残存してしまう。With the increase in the degree of integration of semiconductor integrated circuits, the fineness of trench and wiring layer patterns and the aspect ratio of grooves have been increasing. In the above-described conventional technique, void-free filling of grooves having an aspect ratio of 2.5 or less is possible. However, when the aspect ratio is higher than that, the deposits in the overhang portion are sputtered, but are reattached to the opposing surface and eventually the opening is closed, leaving voids at the bottom of the groove.
【０００６】本発明の目的は、高アスペクト比の溝部に
ボイドなく絶縁膜を充填する方法を提供することにあ
る。An object of the present invention is to provide a method for filling a trench having a high aspect ratio with an insulating film without voids.
【０００７】更に、誘電体絶縁分離や多層配線用層間絶
縁膜として、産業的に有効な技術とするために、下記の
課題が全て達成された絶縁膜及びその製造方法を提供す
ることにある。It is still another object of the present invention to provide an insulating film and a method for manufacturing the same, all of which achieve the following objects, in order to achieve an industrially effective technique for dielectric isolation or interlayer insulating film for multilayer wiring.
【０００８】（１）層間絶縁膜本来の目的である層間の
絶縁（絶縁破壊強度の確保，リーク電流の低減）が基本
であり、更に誘電率，膜応力等の機能的性質。(1) Interlayer insulation (securing dielectric breakdown strength and reducing leakage current), which is the original purpose of the interlayer insulating film, is fundamental, and further, functional properties such as dielectric constant and film stress.
【０００９】（２）下地のシリコン基板や金属配線に対
する不純物や水分の浸入を防止して腐食を防ぎ信頼性を
確保し、基板や配線材料との熱膨張係数に差異による変
形を防止し、基板や配線材料と長期にわたって反応せず
かつ密着性が良いこと等の構造的整合性。(2) Impurities and moisture are prevented from penetrating into the underlying silicon substrate and metal wiring to prevent corrosion and ensure reliability, to prevent deformation due to a difference in thermal expansion coefficient between the substrate and wiring material, Structural integrity, such as not reacting with metal or wiring materials for a long time and having good adhesion.
【００１０】（３）表面の平坦化研磨やスルーホールの
加工性が良好なこと、耐熱性や耐薬品性等の以降の工程
とのプロセスマッチング。(3) Process matching with subsequent processes such as flattening of the surface and good workability of through holes, heat resistance and chemical resistance.
【００１１】（４）工程数，工程コスト，ターンアラウ
ンドタイム等及びプロセス均一性・再現性，歩留まりや
プロセス異物の対策等、製造工程の環境適応性等の生産
性。(4) Productivity such as the number of processes, process cost, turnaround time, process uniformity and reproducibility, environmental adaptability of the manufacturing process such as measures against yield and process foreign matter.
【００１２】[0012]
【課題を解決するための手段】上記目的は、分離用絶縁
膜を以下の工程で形成することにより、達成される。 （１）基板の溝内面や下部配線の表面層をシリコン膜
（アモルファスまたは多結晶シリコン）で被覆し、
（２）上記シリコン膜を酸化してシリコン酸化膜を主体
とする膜に改質し、（３）必要に応じて再度（１)，
(２）の工程を繰り返す、ことにより達成される。The above object can be attained by forming an isolation insulating film in the following steps. (1) covering the inner surface of the groove of the substrate and the surface layer of the lower wiring with a silicon film (amorphous or polycrystalline silicon);
(2) The silicon film is oxidized to be reformed into a film mainly composed of a silicon oxide film. (3) If necessary, (1),
This is achieved by repeating step (2).
【００１３】これは、ＣＶＤによるシリコン膜の堆積
は、基板の凹凸の表面形状の忠実に沿って形成され(con
formal）、酸化はほぼ元の形状通りに膜厚が増える性質
を利用することにより、微細溝の充填を可能にしたもの
である。[0013] This is because the deposition of a silicon film by CVD is formed in conformity with the surface shape of the concavo-convex substrate.
Formal) and oxidation make it possible to fill the fine grooves by utilizing the property that the film thickness increases almost in the original shape.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施例を図面を用
いて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１５】図１は本発明による多層配線用層間絶縁膜
の基本工程の断面模式図を示す。FIG. 1 is a schematic cross-sectional view of a basic step of an interlayer insulating film for a multilayer wiring according to the present invention.
【００１６】（ａ）は直径２００mmの能動層の形成され
たシリコンウエハ１０上にシリコン酸化膜（ＳｉＯ2 ）
２０，アルミニウム（Ａｌ）を主体とする下層配線層３
０が形成された状態の被膜形成基板である。アルミニウ
ム配線層３０は、詳細にはモリブデンシリサイド６０ｎ
ｍ−アルミニウム(０.５％銅，シリコン含有）８００ｎ
ｍ−モリブデンシリサイド４０ｎｍの３層積層構造であ
る。配線幅０.４μｍ,配線間隔０.３μｍ，配線膜厚０.
９μｍであり、アスペクト比は３.０である。 （ｂ）は第１層のシリコン膜４１を高密度プラズマＣＶ
Ｄ法により、厚み４０ｎｍ堆積させた状態を示す。プラ
ズマの状態やプロセス条件は以下の通りである。1A shows a silicon oxide film (SiO 2 ) on a silicon wafer 10 on which an active layer having a diameter of 200 mm is formed.
20, lower wiring layer 3 mainly composed of aluminum (Al)
0 is a film-formed substrate in a state where it is formed. More specifically, the aluminum wiring layer 30 is made of molybdenum silicide 60n.
m-aluminum (0.5% copper, containing silicon) 800n
This is a three-layer laminated structure of m-molybdenum silicide of 40 nm. Wiring width 0.4 μm, wiring interval 0.3 μm, wiring thickness 0.3
9 μm, and the aspect ratio is 3.0. (B) shows that the first layer silicon film 41 is formed by high density plasma CV.
This shows a state where a thickness of 40 nm is deposited by the method D. The plasma state and process conditions are as follows.
【００１７】 反応ガス圧力 モノシランガス（ＳｉＨ4 ） ０.２〜０.３Ｐａ シリコンウエハの温度 制御せず （反応中はプラズマ照射により、 １５０〜２００℃に加熱される） 反応容器内の最大磁場強度 １１００Gauss マイクロ波(２.４５ＧＨｚ）照射強度 １.５ｋＷ 上記の反応条件により、反応時間１０ｓで４０ｎｍのシ
リコン膜が形成できる。ここで重要なことは、高アスペ
クト比特にアスペクト比２.５ 以上の形状の深溝の内部
でも、ほぼ均等な付き廻りが得られることである。Reaction gas pressure Monosilane gas (SiH 4 ) 0.2 to 0.3 Pa Temperature of silicon wafer Not controlled (heated to 150 to 200 ° C. by plasma irradiation during reaction) Maximum magnetic field strength in reaction vessel 1100 Gauss Microwave (2.45 GHz) irradiation intensity 1.5 kW Under the above reaction conditions, a 40 nm silicon film can be formed in a reaction time of 10 s. What is important here is that substantially uniform turning can be obtained even in a deep groove having a high aspect ratio, particularly a shape having an aspect ratio of 2.5 or more.
【００１８】（ｃ）は上記のシリコン膜４０を酸化させ
シリコン酸化膜４２に改質した状態を示す。酸化は上記
プラズマＣＶＤと同一装置の反応容器内で以下のプロセ
ス条件でプラズマ酸化させた。FIG. 3C shows a state in which the silicon film 40 is oxidized and reformed into a silicon oxide film 42. Oxidation was performed by plasma oxidation under the following process conditions in a reaction vessel of the same apparatus as that of the plasma CVD.
【００１９】 反応ガス供給量 酸素ガス（Ｏ2 ） ０.２Ｐａ アルゴン（Ａｒ） ０.１〜０.１５Ｐａ 反応容器内の最大磁場強度 １１００Gauss マイクロ波(２.４５ＧＨｚ）照射強度 １.５ｋＷ 基板バイアス(１３.５６ＭＨｚ） ２.６ｋＷ プラズマ酸化の雰囲気にアルゴンを添加し、更に基板に
バイアスを印加したのは、プラズマ中の酸素イオンやア
ルゴンイオンが加速されて基板上の堆積膜に衝突し、特
に、イオンの照射角度が４５°近傍をピークとしたスパ
ッタエッチングの効果を発揮させるためである。この効
果により堆積膜の開口部の肩部４２ａが選択的にスパッ
タエッチングされ、開口部が塞がってボイドが発生して
しまうことを防止するためである。また、基板にバイア
ス印加することにより、酸化速度を向上させることがで
きる。Reaction gas supply amount Oxygen gas (O 2 ) 0.2 Pa Argon (Ar) 0.1 to 0.15 Pa Maximum magnetic field intensity in the reaction vessel 1100 Gauss Microwave (2.45 GHz) irradiation intensity 1.5 kW Substrate bias ( (13.56 MHz) 2.6 kW Argon was added to the atmosphere of plasma oxidation, and the bias was further applied to the substrate because oxygen ions and argon ions in the plasma were accelerated and collided with the deposited film on the substrate. This is for exhibiting the effect of sputter etching with the ion irradiation angle having a peak near 45 °. This effect is to prevent the shoulder 42a of the opening of the deposited film from being selectively sputter-etched, thereby preventing the opening from being closed and generating a void. Further, by applying a bias to the substrate, the oxidation rate can be improved.
【００２０】厚み４０ｎｍのシリコン膜は、上記の条件
でのプラズマ酸化により２０ｓ以内ですべてシリコン酸
化膜４２に改質させることができる。The silicon film having a thickness of 40 nm can be entirely transformed into the silicon oxide film 42 within 20 seconds by plasma oxidation under the above conditions.
【００２１】シリコン酸化膜４２の品位及び室温におけ
る特性は、以下の通りである。なお、これはシリコン基
板の平面部に形成した種々の膜厚のＴＥＧ(Test Elemen
t Group）を用いて評価した値である。The quality and characteristics at room temperature of the silicon oxide film 42 are as follows. It should be noted that the TEG (Test Elemen) of various thicknesses formed on the plane portion of the silicon substrate
t Group).
【００２２】 酸化速度（酸化膜厚） ２５０ｎｍ／min 絶縁破壊強度 ≧５.２ＭＶ／cm 抵抗率 １×１０15Ω−cm 誘電率（１ＭＨｚ） ４.１±０.１ 異物密度（≧０.３μｍ） ≦０.０２ケ／cm2 プラズマダメ−ジ なし（アンテナ比１００００の ＭＯＳデバイスのＶ−Ｉ特性のシ フトより） 緩衝フッ酸によるエッチング速度 ０.８ｎｍ／ｓ （ＨＦ：ＮＨ4Ｆ＝１：１０） 昇温脱離ガス分析（含有水分量） 熱酸化膜（ドライ酸素）と同等 屈折率 １.４５２〜１.４６５ 赤外吸収スペクトルのピーク波数 （Ｓｉ−Ｏ結合） １０７８〜１０８０／cm （Ｓｉ−Ｈ結合） 検出限界以下(＜１×１０11／cm3) 上記の様に、絶縁破壊強度、抵抗率の値およびプラズマ
ダメージ評価の結果は層間絶縁膜の基本的性質を充分満
足している。また、エッチング速度，屈折率，赤外吸収
スペクトル（Ｓｉ−Ｏ結合）からは、緻密性が検証され
る。昇温脱離ガス分析や赤外吸収スペクトル（Ｓｉ−Ｈ
結合）の分析値から含有水分量は、従来の高信頼性膜と
して半導体素子に用いられているシリコンの熱酸化(ド
ライ酸化)による酸化膜と同等であり、これらを総合す
ると、高品位緻密性膜と評価できる。Oxidation rate (oxide film thickness) 250 nm / min Dielectric breakdown strength ≧ 5.2 MV / cm Resistivity 1 × 10 15 Ω-cm Dielectric constant (1 MHz) 4.1 ± 0.1 Foreign matter density (≧ 0.3 μm) ) ≦ 0.02 pcs / cm 2 No plasma damage (From shift of VI characteristics of MOS device with antenna ratio of 10000) Etching rate by buffered hydrofluoric acid 0.8 nm / s (HF: NH 4 F = 1: 10) Thermal desorption analysis (Moisture content) Equivalent to thermal oxide film (dry oxygen) Refractive index 1.452 to 1.465 Peak wavenumber of infrared absorption spectrum (Si-O bond) 1078 to 1080 / cm (Si-H bond) Detection limit or less (<1 × 10 11 / cm 3 ) As described above, the values of the dielectric breakdown strength, the resistivity, and the results of the plasma damage evaluation sufficiently satisfy the basic properties of the interlayer insulating film. Further, the denseness is verified from the etching rate, the refractive index, and the infrared absorption spectrum (Si—O bond). Thermal desorption gas analysis and infrared absorption spectrum (Si-H
From the analysis value of (bonding), the moisture content is equivalent to the oxide film by thermal oxidation (dry oxidation) of silicon, which has been used in semiconductor devices as a conventional highly reliable film, and when these are combined, high-quality denseness Can be evaluated as a membrane.
【００２３】（ｄ）は上記の膜の上の再びシリコン膜４
３を堆積させた状態を示す。形成装置及び条件は（ｂ）
と全く同様である。シリコンの膜厚は次工程のプラズマ
酸化により２.１ 倍のシリコン酸化膜となることを見込
んで決められる。溝幅ｄをｎサイクルの堆積，酸化の工
程で完全に充填するためには、シリコン層の各サイクル
毎の膜厚ａ1 ，ａ2 ，・・・，ａn は、２.１(ａ1 ＋ａ
2 ＋・・・＋ａn )＝０.５ｄ と表わされる。(D) shows the silicon film 4 on the above film again.
3 shows a state where 3 is deposited. The forming apparatus and conditions are (b)
Is exactly the same as The film thickness of silicon is determined in consideration of the fact that a silicon oxide film of 2.1 times will be formed by plasma oxidation in the next step. Depositing a groove width d of the n cycles, in order to completely fill in the oxidation step, the thickness a 1, a 2 of each cycle of the silicon layer, · · ·, a n is 2.1 (a 1 + A
2 +... + A n ) = 0.5d.
【００２４】シリコン膜厚がやや多き過ぎると、酸化
後、アルミニウム配線層３０に適切な圧縮応力を与え、
アルミニウム配線層３０の断線防止に効果的である。シ
リコン膜厚が厚過ぎると、酸化後、アルミニウム配線層
３０に過剰な応力を与え変形を生ずるため、適切な厚み
を選定する必要がある。ここでは、溝幅の加工寸法のバ
ラツキ誤差を考慮し、過剰応力の発生を防止するため、
膜厚は３０ｎｍとした。 （ｅ）は再び上記シリコン膜をプラズマ酸化させて、シ
リコン酸化膜４４に改質した状態を示す。膜改質の条件
は（ｃ）に示した場合と同一である。If the silicon film thickness is too large, an appropriate compressive stress is applied to the aluminum wiring layer 30 after oxidation,
This is effective in preventing disconnection of the aluminum wiring layer 30. If the silicon film is too thick, an excessive stress is applied to the aluminum wiring layer 30 after oxidation to cause deformation, so that it is necessary to select an appropriate thickness. Here, in order to prevent the occurrence of excessive stress, taking into account the variation error of the processing dimensions of the groove width,
The film thickness was 30 nm. (E) shows a state in which the silicon film is again subjected to plasma oxidation to be modified into a silicon oxide film 44. The conditions for film modification are the same as those shown in FIG.
【００２５】（ｆ）は第３回目のシリコン膜堆積とそれ
をプラズマ酸化させた状態を示す。条件は上記第１回
目，第２回目と同様であり、シリコン膜厚は１５０ｎ
ｍ、改質後のシリコン酸化膜４５の厚みは３１０ｎｍで
ある。(F) shows the state of the third silicon film deposition and its plasma oxidation. The conditions are the same as those of the first and second times, and the silicon film thickness is 150 n.
m, the thickness of the modified silicon oxide film 45 is 310 nm.
【００２６】（ｇ）はシリコン酸化膜４５の表面層を超
精密化学的機械的研磨（ＣＭＰ：Chemical Mechanical
Polishing)により、平坦化５０させた状態を示す。ＣＭ
Ｐはアンモニア(ＮＨ4ＯＨ）またはアミンノ加工液ベー
スのヒュームドシリカと高純度セリアにより、膜の剥離
やスクラッチ等の欠陥の発生がなく平坦化できる。この
様にして作成したサンプルの断面を走査型電子顕微鏡
（ＳＥＭ）で観察すると、配線溝部は完全に充填されて
いることが確認できた。これは、（１）シリコン膜が、
基板の凹凸の表面形状に忠実に沿って堆積される(confo
rmal）ため、（２）シリコン酸化膜形成時に基板にバイ
アス印加して、開口部の肩部をスパッタエッチングさせ
ることにより、開口部が塞がれてボイドが形成されるこ
とが防止できたためである。(G) Ultra-precision chemical mechanical polishing (CMP) of the surface layer of the silicon oxide film 45.
Polishing) shows a state where the surface is flattened 50. CM
P can be planarized by using fumed silica based on ammonia (NH 4 OH) or an amine processing liquid and high-purity ceria without causing defects such as film peeling and scratching. When the cross section of the sample thus prepared was observed with a scanning electron microscope (SEM), it was confirmed that the wiring groove was completely filled. This is because (1) the silicon film
Deposited along the topography of the substrate irregularities (confo
(2) It is because (2) a bias is applied to the substrate when the silicon oxide film is formed, and the shoulder of the opening is sputter-etched, thereby preventing the opening from being closed and the formation of a void. .
【００２７】上記実施例では、３回のサイクルにより形
成したが、サイクル回数はパターンの形状やサイズによ
り変更が可能である。また溝部が完全に充填された後
は、シリコン酸化膜を直接に堆積させることもできる。In the above embodiment, three cycles are used, but the number of cycles can be changed depending on the shape and size of the pattern. After the trench is completely filled, a silicon oxide film can be directly deposited.
【００２８】また上記実施例では、適用としてシリコン
酸化膜を主体とする多層配線層間絶縁膜について詳細に
述べたが、それ以外の応用、例えばシリコン基板上の狭
幅溝へ誘電体膜を充填するＳＴＩ（Shallow Trench Iso
lation）等ヘも適用できる。膜の材質としては、酸化膜
以外にプラズマ窒化による窒化膜の形成も可能である。Further, in the above embodiment, the multilayer wiring interlayer insulating film mainly composed of a silicon oxide film has been described in detail as an application, but other applications, for example, filling a narrow groove on a silicon substrate with a dielectric film. STI (Shallow Trench Iso
lation) can also be applied. As a material of the film, a nitride film can be formed by plasma nitriding other than the oxide film.
【００２９】プラズマＣＶＤ法によるシリコン膜の成
膜、及びプラズマ酸化によるシリコン酸化膜の製造装置
を詳述する。An apparatus for forming a silicon film by plasma CVD and a device for manufacturing a silicon oxide film by plasma oxidation will be described in detail.
【００３０】図２は有磁場マイクロ波のプラズマＣＶＤ
装置１００の断面模式図を示す。この種の構成はＥＣＲ
(Electron Cyclotron Resonance)−ＣＶＤとも呼ばれて
いる。装置は反応容器１２０の内部及び周囲に、シリコ
ンウエハ１１０をセットするためのヘリウムガス冷却付
きの静電チャック方式の基板支持台１２１、それに高周
波電圧を印加するための高周波電源１２２，シリコンウ
エハ１１０を出し入れするための搬送ロボット１３１付
きウエハロード・アード室１３０，圧力調整のためのゲ
ートバルブ１２３と真空排気用ターボ分子ポンプ１２
４，マイクロ波導波管１２５とマイクロ波導入用石英製
窓１２６，ＥＣＲ形成用磁界コイル１２７、及び反応ガ
ス供給制御系１４０が備え付けられている。FIG. 2 shows a plasma CVD of a magnetic field microwave.
1 shows a schematic cross-sectional view of an apparatus 100. This type of configuration is ECR
It is also called (Electron Cyclotron Resonance) -CVD. The apparatus includes a substrate support table 121 of an electrostatic chuck type with helium gas cooling for setting the silicon wafer 110 inside and around the reaction vessel 120, a high frequency power supply 122 for applying a high frequency voltage thereto, and the silicon wafer 110. Wafer load / ard chamber 130 with transfer robot 131 for loading / unloading, gate valve 123 for pressure adjustment, and turbo-molecular pump 12 for evacuation
4, a microwave waveguide 125, a quartz window 126 for microwave introduction, a magnetic field coil 127 for ECR formation, and a reaction gas supply control system 140 are provided.
【００３１】まず、シリコンウエハ１１０をウエハロー
ド・アンロード室１３０を通して基板支持台１２１にセ
ットする。次に反応容器１２０内をゲートバルブ１２３
を開放にして真空排気用ターボ分子ポンプ１２４により
真空排気する。到達圧力は０.１ｍＰａ以下である。First, the silicon wafer 110 is set on the substrate support 121 through the wafer loading / unloading chamber 130. Next, the inside of the reaction vessel 120 is closed with a gate valve 123.
Is opened, and vacuum evacuation is performed by the evacuation turbo molecular pump 124. The ultimate pressure is 0.1 mPa or less.
【００３２】基板支持台１２１への高周波１２２の印加
は、堆積膜のスパッタエッチングを使用する時、即ち、
配線パターンの微細溝部への膜の堆積充填時に用いる。The high frequency 122 is applied to the substrate support 121 when sputter etching of the deposited film is used, that is,
It is used when depositing and filling a film into the fine groove of the wiring pattern.
【００３３】同一反応容器１２０内でシリコン膜のＣＶ
Ｄとそのプラズマ酸化を高速に実施するためには、反応
ガスの交換や流入を迅速にする必要がある。本方式で
は、１回の反応時間は短く、シリコン膜堆積や酸化に要
するガス量も少量であるため、高精度の制御は必要とし
ない。反応容器１２０内に反応ガスを迅速に流入させる
ためには、高真空に排気後、ゲートバルブ１２３を閉
じ、所定の体積及び圧力のガス留１４１に留保されたガ
スをバルブ１４２を開放してパルス的に反応容器１２０
内に流入させることにより達成できる。反応時間が長く
なるときは、これを繰り返すことにより、反応の量（シ
リコン膜厚，酸化膜厚）を確保することができる。CV of silicon film in the same reaction vessel 120
In order to perform D and its plasma oxidation at a high speed, it is necessary to quickly exchange and inflow the reaction gas. In this method, a single reaction time is short, and the amount of gas required for silicon film deposition and oxidation is small, so that high-precision control is not required. In order to quickly flow the reaction gas into the reaction vessel 120, after evacuation to a high vacuum, the gate valve 123 is closed, and the gas retained in the gas reservoir 141 having a predetermined volume and pressure is opened by opening the valve 142 to form a pulse. Reaction vessel 120
It can be achieved by flowing into. When the reaction time becomes long, this is repeated to ensure the amount of reaction (silicon film thickness, oxide film thickness).
【００３４】また、プラズマＣＶＤ・酸化装置として有
磁場マイクロ波プラズマＣＶＤ・酸化装置を用いている
が、これに限定されるものではなく、他の高密度プラズ
マ処理装置、例えば、ＩＣＰ（Inductively Coupled Pl
asma：誘導結合プラズマ），ヘリコン波プラズマ等の高
密度プラズマ処理装置，通常のＲＦプラズマ処理装置等
も使用可能である。また、連続処理装置としてＣＶＤ用
反応容器，酸化用反応容器を分離し、個々の容器間に基
板を搬送させて実施する処理方式でも可能である。Although a magnetic field microwave plasma CVD / oxidizing apparatus is used as the plasma CVD / oxidizing apparatus, the present invention is not limited to this. Other high-density plasma processing apparatuses, for example, ICP (Inductively Coupled Pl
Asma: inductively coupled plasma), a high-density plasma processing apparatus such as a helicon wave plasma, and an ordinary RF plasma processing apparatus can also be used. In addition, a processing method in which a CVD reaction vessel and an oxidation reaction vessel are separated as a continuous processing apparatus, and the substrate is transported between the individual vessels, is also possible.
【００３５】[0035]
【発明の効果】本発明によれば、従来広く用いられてい
るプラズマＣＶＤとプラズマ酸化工程を組み合わせるこ
とにより、（１）半導体装置の基板や配線間の狭く高い
アスペクト比の溝に絶縁膜を完全に充填することが可能
であり、（２）絶縁膜及び配線層の高信頼性が確保さ
れ、（３）他のプロセスとのマッチングが容易であり、
（４）生産性にも優れているため、半導体装置、特に高
集積半導体集積回路素子の特性及び信頼性の改善・向上
に大きな効果がある。According to the present invention, by combining the widely used plasma CVD and plasma oxidation processes, (1) an insulating film is completely formed in a narrow groove having a high aspect ratio between a substrate and a wiring of a semiconductor device. (2) High reliability of the insulating film and the wiring layer is secured, (3) Matching with other processes is easy,
(4) Since it is excellent in productivity, it has a great effect on improving and improving the characteristics and reliability of a semiconductor device, particularly a highly integrated semiconductor integrated circuit element.
【００３６】また更に、本発明の方式は次の利点があ
り、産業的なメリットは大である。Further, the method of the present invention has the following advantages, and has a great industrial advantage.
【００３７】（５）半導体基板内の均一性に優れる。こ
れは、２種類のガス（ＳｉＨ4とＯ2、等）を反応させて
シリコン酸化膜を直接に堆積させるのに比べて、１種類
のガス（ＳｉＨ4 ）で済むシリコン膜形成は均一性に優
れており、プラズマ酸化による膜厚はシリコン膜厚によ
って決まるためである。(5) Excellent uniformity in the semiconductor substrate. This is because, compared with the case where two kinds of gases (SiH 4 and O 2 , etc.) are reacted to directly deposit a silicon oxide film, the formation of a silicon film which requires only one kind of gas (SiH 4 ) is more uniform. This is because the film thickness by plasma oxidation is determined by the silicon film thickness.
【００３８】（６）歩留まり低下の元凶である異物が少
ない。上記と同様に、シリコン酸化膜を直接に堆積させ
るのに比べて、シリコン膜形成は本質的に異物発生が少
なく、プラズマ酸化では原理的には異物の発生はないた
めである。さらにこのために、装置のクリーニングが容
易となり、この観点でもコスト低減の寄与が大きい。(6) There are few foreign substances which are the cause of the decrease in yield. This is because, as in the above case, the formation of the silicon film essentially reduces the generation of foreign matter, and the plasma oxidation does not generate any foreign matter in principle, as compared with the case where the silicon oxide film is directly deposited. Further, for this reason, cleaning of the apparatus is facilitated, and from this viewpoint, the contribution of cost reduction is large.
【図１】本発明の一実施例の半導体装置の製造工程を示
す部分断面図。FIG. 1 is a partial cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.
【図２】本発明の製造プロセスを実施するためのプラズ
マＣＶＤ装置の構成図。FIG. 2 is a configuration diagram of a plasma CVD apparatus for performing the manufacturing process of the present invention.
１０…シリコンウエハ基板、３０…アルミニウム配線
層、４０…層間絶縁膜、４１，４３…シリコン膜(Ｓ
ｉ）、４２，４４，４５…シリコン酸化膜(ＳｉＯ2)、
５０…平坦化、１００…プラズマＣＶＤ装置、１１０…
シリコンウエハ、120…反応容器、１４０…反応ガス供
給制御系。10 silicon wafer substrate, 30 aluminum wiring layer, 40 interlayer insulating film, 41, 43 silicon film (S
i), 42, 44, 45 ... silicon oxide film (SiO 2 ),
50: flattening, 100: plasma CVD device, 110:
Silicon wafer, 120: reaction vessel, 140: reaction gas supply control system.
Claims (5)
主成分とする絶縁膜を充填形成する方法において、溝部
開口内面にシリコン膜を堆積させた後、該シリコン膜を
酸化させてシリコン酸化膜に改質することを特徴とする
半導体集積回路の製造方法。In a method of filling and forming an insulating film containing a silicon oxide film as a main component in a groove opening of a semiconductor substrate, a silicon film is deposited on an inner surface of the groove opening, and the silicon film is oxidized to form a silicon oxide film. A method for manufacturing a semiconductor integrated circuit, wherein the method is modified into a film.
形成方法において、（ａ）下部配線パターンの配線の表
面をシリコン膜で被覆する工程、（ｂ）上記シリコン膜
をシリコン酸化膜に改質する工程、上記（ａ）及び
（ｂ）の工程の１回以上の繰り返すことにより、溝開口
部を空孔（ボイド）なく充填する工程からなることを特
徴とする半導体集積回路の製造方法。2. A method of forming an interlayer insulating film for a multilayer wiring of a semiconductor integrated circuit, comprising: (a) covering the surface of the wiring of the lower wiring pattern with a silicon film; and (b) converting the silicon film to a silicon oxide film. A method of manufacturing a semiconductor integrated circuit, comprising: filling a groove opening without voids by repeating at least one of the steps of (a) and (b) above.
の堆積及びそのシリコン酸化膜への改質はプラズマ化学
反応処理（プラズマＣＶＤ，プラズマ酸化）によること
を特徴とする半導体集積回路の製造方法。3. A method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the deposition of the silicon film and the modification of the silicon oxide film are performed by a plasma chemical reaction process (plasma CVD, plasma oxidation). .
及びそのシリコン酸化膜への改質のプラズマ化学反応処
理（プラズマＣＶＤ，プラズマ酸化）は、高密度プラズ
マにより発生したプラズマを基板に吸引して、基板の溝
開口部のエッジ部のオーバーハング部をスパッタエッチ
ングさせながら反応処理することを特徴とする半導体集
積回路の製造方法。4. A plasma chemical reaction process (plasma CVD, plasma oxidation) for depositing a silicon film and modifying the silicon oxide film according to claim 3, wherein the plasma generated by the high-density plasma is sucked into the substrate. And performing a reaction process while sputter-etching an overhang portion at an edge of the groove opening of the substrate.
及びそのシリコン酸化膜への改質によりシリコン酸化膜
を主成分とする絶縁膜を充填形成させるプラズマ処理装
置において、シリコン原料ガスと酸素ガスを交互にパル
ス状に供給する手段とを具備することを特徴とする半導
体集積回路の製造装置。5. A plasma processing apparatus in which a silicon film is deposited in a groove opening of a semiconductor substrate and an insulating film containing a silicon oxide film as a main component is formed by reforming the silicon film into a silicon oxide film. Means for alternately supplying gas in a pulsed manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2174198A JPH11219950A (en) | 1998-02-03 | 1998-02-03 | Manufacture of semiconductor integrated circuit and manufacturing device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2174198A JPH11219950A (en) | 1998-02-03 | 1998-02-03 | Manufacture of semiconductor integrated circuit and manufacturing device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11219950A true JPH11219950A (en) | 1999-08-10 |
Family
ID=12063510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2174198A Pending JPH11219950A (en) | 1998-02-03 | 1998-02-03 | Manufacture of semiconductor integrated circuit and manufacturing device thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11219950A (en) |
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| KR100322890B1 (en) * | 1999-12-30 | 2002-02-08 | 박종섭 | Method for forming oxide layer of semiconductor device |
| JP2002203796A (en) * | 2000-07-07 | 2002-07-19 | Applied Materials Inc | Deposition of amorphous silicon film by high-density plasma hdp-cvd at low temperature |
| US6815299B2 (en) | 2000-08-31 | 2004-11-09 | Nissan Motor Co., Ltd. | Method for manufacturing silicon carbide device using water rich anneal |
| JP2005229129A (en) * | 2000-06-08 | 2005-08-25 | Genitech Inc | Method of forming thin film |
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| WO2009093760A1 (en) * | 2008-01-24 | 2009-07-30 | Tokyo Electron Limited | Method for forming silicon oxide film, storage medium, and plasma processing apparatus |
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| JP2013077823A (en) * | 2000-03-13 | 2013-04-25 | Foundation For Advancement Of International Science | Method for forming oxide film |
| JP2019024080A (en) * | 2017-06-06 | 2019-02-14 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Bottom-up growth of silicon oxide and silicon nitride using sequential deposition-etch-treat methods |
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| KR100322890B1 (en) * | 1999-12-30 | 2002-02-08 | 박종섭 | Method for forming oxide layer of semiconductor device |
| JP2013077823A (en) * | 2000-03-13 | 2013-04-25 | Foundation For Advancement Of International Science | Method for forming oxide film |
| JP2005229129A (en) * | 2000-06-08 | 2005-08-25 | Genitech Inc | Method of forming thin film |
| JP4684706B2 (en) * | 2000-06-08 | 2011-05-18 | ジニテック インク． | Thin film formation method |
| JP2002203796A (en) * | 2000-07-07 | 2002-07-19 | Applied Materials Inc | Deposition of amorphous silicon film by high-density plasma hdp-cvd at low temperature |
| US6815299B2 (en) | 2000-08-31 | 2004-11-09 | Nissan Motor Co., Ltd. | Method for manufacturing silicon carbide device using water rich anneal |
| JP2010283388A (en) * | 2002-04-11 | 2010-12-16 | Hitachi Kokusai Electric Inc | Method of producing semiconductor device |
| JP2010283357A (en) * | 2002-07-19 | 2010-12-16 | Asm America Inc | Method to form ultra high quality silicon-containing compound layers |
| JP4671201B2 (en) * | 2005-07-19 | 2011-04-13 | パイオニア株式会社 | Protective film manufacturing method, inorganic film manufacturing method |
| JPWO2007010736A1 (en) * | 2005-07-19 | 2009-01-29 | パイオニア株式会社 | Protective film manufacturing method, inorganic film manufacturing method |
| WO2007010736A1 (en) * | 2005-07-19 | 2007-01-25 | Pioneer Corporation | Protection film manufacturing method and inorganic film manufacturing method |
| JP2007294082A (en) * | 2006-03-31 | 2007-11-08 | Semiconductor Energy Lab Co Ltd | Method for deleting data from nand type nonvolatile memory |
| JP2009152551A (en) * | 2007-10-22 | 2009-07-09 | Applied Materials Inc | Method and system for improving dielectric film quality for void free gap fill |
| WO2009093760A1 (en) * | 2008-01-24 | 2009-07-30 | Tokyo Electron Limited | Method for forming silicon oxide film, storage medium, and plasma processing apparatus |
| JP2010206223A (en) * | 2010-06-11 | 2010-09-16 | Hitachi Kokusai Electric Inc | Method of manufacturing semiconductor device, and substrate processing apparatus |
| JP2019024080A (en) * | 2017-06-06 | 2019-02-14 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Bottom-up growth of silicon oxide and silicon nitride using sequential deposition-etch-treat methods |
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