JPH11177014A - Electronic device and manufacture thereof - Google Patents
Electronic device and manufacture thereofInfo
- Publication number
- JPH11177014A JPH11177014A JP9338687A JP33868797A JPH11177014A JP H11177014 A JPH11177014 A JP H11177014A JP 9338687 A JP9338687 A JP 9338687A JP 33868797 A JP33868797 A JP 33868797A JP H11177014 A JPH11177014 A JP H11177014A
- Authority
- JP
- Japan
- Prior art keywords
- wiring member
- wiring
- input
- electronic device
- lsi chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子装置およびそ
の製造方法に関し、特に、携帯用電子機器などに用いら
れる複数のＬＳＩチップが内蔵されたカード状の電子装
置に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device and a method of manufacturing the same, and more particularly, to a technology effective when applied to a card-like electronic device having a plurality of LSI chips built therein and used for portable electronic equipment. .
【０００２】[0002]
【従来の技術】最近、例えば通信機器、情報機器、事務
機器などの分野において、携帯可能な電子機器が広く普
及してきている。これらの携帯用電子機器には、ＩＣカ
ードやメモリカードなどで呼ばれているカード状の電子
装置が組み込まれており、これらの電子装置はマイクロ
プロセッサや半導体メモリなどのＬＳＩが内蔵されて構
成されている。そのような携帯用電子機器は、携帯性を
より高めるために、より一層小型化、軽量化が望まれて
おり、これに伴ってそれに組み込まれるＩＣカードやメ
モリカードなどの電子装置も、より一層小型化が図られ
ている。2. Description of the Related Art Recently, portable electronic devices have become widespread in fields such as communication devices, information devices, and office devices. These portable electronic devices incorporate card-shaped electronic devices called IC cards and memory cards, and these electronic devices are configured by incorporating LSIs such as microprocessors and semiconductor memories. ing. Such portable electronic devices are required to be further reduced in size and weight in order to further enhance portability, and accordingly, electronic devices such as IC cards and memory cards incorporated therein are further required. The miniaturization is achieved.
【０００３】そのような電子装置は、例えば基板状の配
線部材上に複数のＬＳＩチップが実装されて、配線部材
の一部に設けられた入出力端子を通じて外部からＬＳＩ
チップに対して電気信号が入出力可能に構成されてい
る。例えばＩＣカードでは、配線部材上にマイクロプロ
セッサチップとともにメモリチップが実装されて、演算
機能およびメモリ機能が備えられており、入出力端子を
通じて外部からマイクロプロセッサチップに入力された
制御信号に基づいて、メモリチップに記憶されているデ
ータの照合、書き替えなどが行われるようになってい
る。また、メモリカードでは、配線部材上にメモリチッ
プが実装されて、入出力端子を通じて外部から入力され
た制御信号に基づいて、メモリチップに記憶されている
データの照合、書き替えなどが行われるようになってい
る。In such an electronic device, for example, a plurality of LSI chips are mounted on a wiring member in a substrate shape, and the LSI device is externally provided through input / output terminals provided in a part of the wiring member.
An electric signal can be input to and output from the chip. For example, in an IC card, a memory chip is mounted on a wiring member together with a microprocessor chip, and has an arithmetic function and a memory function, and based on a control signal externally input to the microprocessor chip through an input / output terminal, The data stored in the memory chip is collated and rewritten. In a memory card, a memory chip is mounted on a wiring member, and data stored in the memory chip is collated and rewritten based on a control signal input from the outside through an input / output terminal. It has become.
【０００４】例えば、日経ＢＰ社発行、「日経マイクロ
デバイス」、１９８８年３月号、第４９〜第６５頁に
は、そのようなＩＣカードの製造方法が開示されてい
る。[0004] For example, a method for manufacturing such an IC card is disclosed in "Nikkei Micro Device", March 1988, pp. 49-65, published by Nikkei BP.
【０００５】この文献には、ガラス・エポキシなどの配
線部材上に複数のＬＳＩチップを実装してＩＣカードを
製造する技術が示されている。This document discloses a technique for manufacturing an IC card by mounting a plurality of LSI chips on a wiring member such as glass epoxy.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、前記し
たような従来技術では、配線部材上に実装するＬＳＩチ
ップの数が多くなると、必然的に配線部材上の配線の引
き回しが複雑になるという問題がある。However, in the prior art as described above, when the number of LSI chips mounted on a wiring member increases, the problem of inevitably complicating the routing of the wiring on the wiring member. is there.
【０００７】すなわち、配線部材の面積が一定の場合、
これに実装されるＬＳＩチップの数が多くなると、ＬＳ
Ｉチップの実装密度が高くなるので、配線部材上に形成
される配線の密度も高くなってくる。このため、配線の
形成に高精度の微細化技術が要求されるようになるの
で、コストアップが避けられなくなる。That is, when the area of the wiring member is constant,
When the number of LSI chips mounted on this increases,
Since the mounting density of the I chip increases, the density of wiring formed on the wiring member also increases. For this reason, a high-precision miniaturization technique is required for forming the wiring, so that an increase in cost cannot be avoided.
【０００８】本発明の目的は、複数のＬＳＩチップを配
線部材上に実装する電子装置において、配線部材上の配
線の引き回しを簡単にする技術を提供することにある。An object of the present invention is to provide a technique for simplifying the routing of wiring on a wiring member in an electronic device in which a plurality of LSI chips are mounted on the wiring member.
【０００９】また、本発明の目的は、複数のＬＳＩチッ
プを配線部材上に実装する電子装置を、コストアップを
伴うことなく製造する技術を提供することにある。Another object of the present invention is to provide a technique for manufacturing an electronic device in which a plurality of LSI chips are mounted on a wiring member without increasing the cost.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１２】（１）本発明の電子装置は、配線部材上に
複数のＬＳＩチップが実装され、前記配線部材に設けら
れた入出力端子を通じて外部から前記ＬＳＩチップに対
する電気信号が入出力可能に構成されている電子装置で
あって、前記配線部材は第１の配線部材と第２の配線部
材とからなり、前記複数のＬＳＩチップは前記第１の配
線部材と前記第２の配線部材との間に実装されて、前記
第１の配線部材上に裏面が固定された前記ＬＳＩチップ
はその表面の電極が前記第２の配線部材上の配線に接続
され、前記第２の配線部材上に裏面が固定された前記Ｌ
ＳＩチップはその表面の電極が前記第１の配線部材上の
配線に接続されている。(1) An electronic device according to the present invention is configured such that a plurality of LSI chips are mounted on a wiring member, and that an electric signal to / from the LSI chip can be input / output from outside through input / output terminals provided on the wiring member. Wherein the wiring member comprises a first wiring member and a second wiring member, and the plurality of LSI chips are provided between the first wiring member and the second wiring member. The LSI chip mounted on the first wiring member and having a back surface fixed on the first wiring member has an electrode on the front surface connected to wiring on the second wiring member, and has a back surface on the second wiring member. Said L fixed
The electrode on the surface of the SI chip is connected to the wiring on the first wiring member.
【００１３】（２）本発明の電子装置は、（１）記載の
電子装置において、前記ＬＳＩチップの電極はバンプ状
電極からなる。(2) The electronic device according to the present invention is the electronic device according to (1), wherein the electrodes of the LSI chip are bump-shaped electrodes.
【００１４】（３）本発明の電子装置は、（１）または
（２）記載の電子装置において、前記第１の配線部材お
よび前記第２の配線部材の一部に入出力端子が設けら
れ、前記第１の配線部材上に裏面が固定された前記ＬＳ
Ｉチップに対する電気信号は前記第２の配線部材の前記
入出力端子を通じて入出力可能に構成され、前記第２の
配線部材上に裏面が固定された前記ＬＳＩチップに対す
る電気信号は前記第１の配線部材の前記入出力端子を通
じて入出力可能に構成されている。(3) In the electronic device according to the present invention, in the electronic device according to (1) or (2), input / output terminals are provided on a part of the first wiring member and the second wiring member. The LS having a back surface fixed on the first wiring member
An electric signal to the I chip is configured to be input / output through the input / output terminal of the second wiring member, and an electric signal to the LSI chip having a back surface fixed on the second wiring member is the first wiring. Input / output is possible through the input / output terminal of the member.
【００１５】（４）本発明の電子装置は、（１）または
（２）記載の電子装置において、前記第１の配線部材お
よび第２の配線部材の一部に入出力端子が設けられ、前
記第１の配線部材上に裏面が固定された前記ＬＳＩチッ
プおよび前記第２の配線部材上に裏面が固定された前記
ＬＳＩチップに対する電気信号は、前記第１の配線部材
または第２の配線部材の前記入出力端子を通じて入出力
可能に構成されている。(4) The electronic device according to (1) or (2), wherein an input / output terminal is provided on a part of the first wiring member and the second wiring member. An electric signal for the LSI chip having the back surface fixed on the first wiring member and the LSI chip having the back surface fixed on the second wiring member is equal to the electric signal of the first wiring member or the second wiring member. Input / output is possible through the input / output terminal.
【００１６】（５）本発明の電子装置は、（１）または
（２）記載の電子装置において、前記第１の配線部材お
よび前記第２の配線部材の一部および他部に入出力端子
が設けられ、前記第１の配線部材上に裏面が固定された
前記ＬＳＩチップに対する電気信号は前記第２の配線部
材のいずれか一方側の前記入出力端子を通じて入出力可
能に構成され、前記第２の配線部材上に裏面が固定され
た前記ＬＳＩチップに対する電気信号は前記第１の配線
部材のいずれか一方側の前記入出力端子を通じて入出力
可能に構成されている。(5) In the electronic device according to the present invention, in the electronic device according to (1) or (2), an input / output terminal is provided at a part or another part of the first wiring member and the second wiring member. An electrical signal to the LSI chip, the back surface of which is fixed on the first wiring member, is configured to be able to input and output through the input / output terminal on one side of the second wiring member; An electric signal to the LSI chip whose back surface is fixed on the wiring member is input / output through the input / output terminal on either side of the first wiring member.
【００１７】（６）本発明の電子装置は、（１）または
（２）記載の電子装置において、前記第１の配線部材お
よび第２の配線部材の一部および他部に入出力端子が設
けられ、前記第１の配線部材および前記第２の配線部材
の一部あるいは他部に各々の一方側の前記入出力端子同
士を導通させるソケットが接続され、前記第１の配線部
材上に裏面が固定された前記ＬＳＩチップおよび前記第
２の配線部材上に裏面が固定された前記ＬＳＩチップに
対する電気信号は、前記第１の配線部材または第２の配
線部材の他方側の前記入出力端子を通じて入出力可能に
構成されている。(6) In the electronic device according to the present invention, in the electronic device according to (1) or (2), an input / output terminal is provided on a part and another part of the first wiring member and the second wiring member. A socket for conducting the input / output terminals on one side is connected to a part or another part of the first wiring member and the second wiring member, and a back surface is provided on the first wiring member. An electric signal to the fixed LSI chip and the LSI chip whose back surface is fixed on the second wiring member is input through the input / output terminal on the other side of the first wiring member or the second wiring member. It is configured to be able to output.
【００１８】（７）本発明の電子装置の製造方法は、
（ａ）配線と導通する入出力端子が設けられた第１の配
線部材上に、ＬＳＩチップをその表面の電極を前記配線
に接続する工程、（ｂ）配線と導通する入出力端子が設
けられた第２の配線部材上に、他のＬＳＩチップをその
表面の電極を前記配線に接続する工程、（ｃ）前記第１
の配線部材と前記第２の配線部材とを、各々前記ＬＳＩ
チップの前記電極を接続した面同士を前記ＬＳＩチップ
の位置が重ならないように対向させるとともに、前記第
１の配線部材と前記第２の配線部材との間の周囲の位置
にスペーサを配置する工程、（ｄ）前記第１の配線部材
および前記第２の配線部材を押圧することにより、前記
第１の配線部材上の前記配線に表面の電極が接続されて
いる前記ＬＳＩチップの裏面を前記第２の配線部材上に
固定するとともに、前記第２の配線部材上の前記配線に
表面の電極が接続されている前記ＬＳＩチップの裏面を
前記第１の配線部材上に固定し、同時に前記スペーサを
前記第１の配線部材上および第２の配線部材上に固定す
る工程、（ｅ）前記第１の配線部材および第２の配線部
材の前記入出力端子を除いた周囲を箱状のケースで覆う
工程を含んでいる。(7) The method of manufacturing an electronic device according to the present invention comprises:
(A) a step of connecting an electrode on the surface of an LSI chip to the wiring on a first wiring member provided with input / output terminals that are conductive to the wiring; and (b) providing an input / output terminal that is conductive to the wiring. Connecting another LSI chip with electrodes on the surface of the second wiring member to the wiring, and (c) connecting the first LSI chip to the first wiring member.
And the second wiring member are respectively connected to the LSI
A step of causing the surfaces of the chip to which the electrodes are connected to face each other so that the positions of the LSI chips do not overlap, and disposing a spacer at a peripheral position between the first wiring member and the second wiring member (D) pressing the first wiring member and the second wiring member so that the back surface of the LSI chip in which an electrode on the front surface is connected to the wiring on the first wiring member is moved to the second position; And fixing the back surface of the LSI chip, in which electrodes on the front surface are connected to the wiring on the second wiring member, on the first wiring member, and simultaneously fixing the spacer on the first wiring member. Fixing the first wiring member and the second wiring member, and (e) covering the periphery of the first wiring member and the second wiring member excluding the input / output terminals with a box-shaped case. Including process
【００１９】（８）本発明の電子装置の製造方法は、
（７）記載の電子装置において、前記ＬＳＩチップの裏
面の前記第１の配線部材または前記第２の配線部材上へ
の固定は接着材を介して行う。(8) The method of manufacturing an electronic device according to the present invention comprises:
(7) In the electronic device described in (7), the back surface of the LSI chip is fixed on the first wiring member or the second wiring member via an adhesive.
【００２０】（９）本発明の電子装置の製造方法は、
（７）または（８）記載の電子装置において、前記第１
の配線部材および第２の配線部材として、その一部およ
び他部に入出力端子を設けたものを用いる。(9) The method of manufacturing an electronic device according to the present invention comprises:
(7) In the electronic device according to (8), the first device
As the wiring member and the second wiring member, those provided with input / output terminals at a part thereof and other parts are used.
【００２１】[0021]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一の機能を有する部材には同
一の符号を付し、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.
【００２２】（実施の形態１）図１は、実施の形態１で
ある電子装置を示す断面図である。(First Embodiment) FIG. 1 is a sectional view showing an electronic device according to a first embodiment.
【００２３】例えばガラス・エポキシなどからなる基板
状の配線部材（上部配線部材）１と第２の配線部材（下
部配線部材）２との間には、マイクロプロセッサチッ
プ、メモリチップなどからなる複数のＬＳＩチップ３が
実装されている。第１の配線部材１および第２の配線部
材２上には各々配線４、５が形成されている。Between a substrate-like wiring member (upper wiring member) 1 made of, for example, glass and epoxy, and a second wiring member (lower wiring member) 2, a plurality of microprocessor chips, memory chips and the like are provided. An LSI chip 3 is mounted. Wirings 4 and 5 are formed on the first wiring member 1 and the second wiring member 2, respectively.
【００２４】ＬＳＩチップ３はその表面に例えばＰｂ−
Ｓｎ合金からなるバンプ状の電極６が形成されており、
第１の配線部材１上に両面テープなどの接着材７を介し
てその裏面が固定されたＬＳＩチップ３は、その表面の
電極６が第２の配線部材２上の配線５に接続されてい
る。一方、第２の配線部材２上に接着材７を介してその
裏面が固定されたＬＳＩチップ３は、その表面の電極６
が第１の配線部材１上の配線４に接続されている。この
ように、複数のＬＳＩチップ３は、交互に実装方向が逆
になるように第１の配線部材１と第２の配線部材２との
間に実装されている。The LSI chip 3 has, for example, Pb-
A bump-shaped electrode 6 made of a Sn alloy is formed,
In the LSI chip 3 whose back surface is fixed on the first wiring member 1 via an adhesive 7 such as a double-sided tape, the electrodes 6 on the front surface are connected to the wiring 5 on the second wiring member 2. . On the other hand, the LSI chip 3 whose back surface is fixed on the second wiring member 2 via the adhesive 7 is connected to the electrode 6 on the front surface.
Are connected to the wiring 4 on the first wiring member 1. Thus, the plurality of LSI chips 3 are mounted between the first wiring member 1 and the second wiring member 2 so that the mounting directions are alternately reversed.
【００２５】第１の配線部材１の一部には配線４と導通
する入出力端子８が形成され、第２の配線部材２の一部
には配線５と導通する入出力端子９が形成されている。
各入出力端子８、９は各配線部材１、２の側面に形成さ
れた中間配線１０、１１を介して各配線４、５に接続さ
れている。図２は、図１の主要部の拡大構造を示してい
る。または、図３に示すように、各入出力端子８（９）
は各配線部材１（２）に形成されたスルーホール配線１
２（１３）を介して各配線４（５）に接続されていても
よい。An input / output terminal 8 is formed on a part of the first wiring member 1 and is electrically connected to the wiring 4, and an input / output terminal 9 is formed on a part of the second wiring member 2 and is electrically connected to the wiring 5. ing.
The input / output terminals 8 and 9 are connected to the wirings 4 and 5 via intermediate wirings 10 and 11 formed on the side surfaces of the wiring members 1 and 2, respectively. FIG. 2 shows an enlarged structure of a main part of FIG. Alternatively, as shown in FIG. 3, each input / output terminal 8 (9)
Is a through hole wiring 1 formed in each wiring member 1 (2).
2 (13) may be connected to each wiring 4 (5).
【００２６】第１の配線部材１と第２の配線部材２との
間の周囲の位置には、樹脂などの絶縁材料からなるスペ
ーサ１４が介在されていて、第１の配線部材１と第２の
配線部材２との間の間隔を一定に保持している。このス
ペーサ１４は接着材７を介して第１の配線部材１および
第２の配線部材２に固定するようにしてもよい。At a peripheral position between the first wiring member 1 and the second wiring member 2, a spacer 14 made of an insulating material such as resin is interposed, and the first wiring member 1 and the second wiring member 2 are interposed. Of the wiring member 2 is kept constant. The spacer 14 may be fixed to the first wiring member 1 and the second wiring member 2 via the adhesive 7.
【００２７】第１の配線部材１および第２の配線部材２
の周囲は、入出力端子８、９の位置を除いて、例えばア
ルミニウム（Ａｌ）やステンレスなどの導電性材料から
なる箱状のケース１５によって囲まれて機械的な保護が
行われている。この箱状のケース１５はアース用電極と
して使用できるようになっている。First wiring member 1 and second wiring member 2
Is surrounded by a box-shaped case 15 made of a conductive material such as aluminum (Al) or stainless steel, except for the positions of the input / output terminals 8 and 9, thereby providing mechanical protection. This box-shaped case 15 can be used as a ground electrode.
【００２８】このような電子装置は、第１の配線部材１
に設けられた入出力端子８を通じて、第１の配線部材１
の配線４に電極６が接続されたＬＳＩチップ３に対する
電気信号が入出力可能になる。また、第２の配線部材２
に設けられた入出力端子９を通じて、第２の配線部材２
の配線５に電極６が接続されたＬＳＩチップ３に対する
電気信号が入出力可能になる。Such an electronic device includes the first wiring member 1
The first wiring member 1 through the input / output terminal 8 provided in
An electric signal to and from the LSI chip 3 in which the electrode 6 is connected to the wiring 4 can be input and output. Also, the second wiring member 2
Through the input / output terminal 9 provided on the second wiring member 2
An electric signal to and from the LSI chip 3 in which the electrode 6 is connected to the wiring 5 can be input and output.
【００２９】このように、複数のＬＳＩチップ３を交互
に実装方向が逆になるように第１の配線部材１と第２の
配線部材２との間に実装することにより、第１の配線部
材１および第２の配線部材２上に形成する配線４、５の
引き回しを簡単にすることができる。なお、複数のＬＳ
Ｉチップ３は必ずしも規則的に交互に実装方向を逆にす
ることなく、ランダムに逆になっていてもよい。As described above, by mounting the plurality of LSI chips 3 between the first wiring member 1 and the second wiring member 2 so that the mounting directions are alternately reversed, the first wiring member The routing of the wirings 4 and 5 formed on the first and second wiring members 2 can be simplified. Note that a plurality of LS
The I-chips 3 may be randomly reversed without necessarily reversing the mounting direction regularly.
【００３０】次に、上記のような構造を有する電子装置
の製造方法を図４〜図１０を用いて説明する。Next, a method of manufacturing an electronic device having the above-described structure will be described with reference to FIGS.
【００３１】まず、図４に示すように、上部配線部材と
なる第１の配線部材１を用意する。この第１の配線部材
１上には、印刷法などで形成された配線４が形成されて
おり、この配線４のＬＳＩチップのバンプ状の電極が接
続される位置には、ランド部４ａが形成されている。配
線４は、図２あるいは図３に示したように、第１の配線
部材４の反対面に形成された入出力端子８と導通してい
る。First, as shown in FIG. 4, a first wiring member 1 serving as an upper wiring member is prepared. A wiring 4 formed by a printing method or the like is formed on the first wiring member 1, and a land portion 4a is formed at a position where the bump-shaped electrode of the LSI chip of the wiring 4 is connected. Have been. The wiring 4 is electrically connected to the input / output terminal 8 formed on the opposite surface of the first wiring member 4 as shown in FIG. 2 or FIG.
【００３２】次に、図５に示すように、下部配線部材と
なる第１の配線部材２を用意する。この第２の配線部材
２上には、印刷法などで形成された配線５が形成されて
おり、この配線５のＬＳＩチップのバンプ状の電極が接
続される位置には、ランド部５ａが形成されている。配
線５は、図２あるいは図３に示したように、第２の配線
部材５の反対面に形成された入出力端子９と導通してい
る。Next, as shown in FIG. 5, a first wiring member 2 serving as a lower wiring member is prepared. A wiring 5 formed by a printing method or the like is formed on the second wiring member 2, and a land 5a is formed at a position where the bump-shaped electrode of the LSI chip of the wiring 5 is connected. Have been. The wiring 5 is electrically connected to the input / output terminal 9 formed on the opposite surface of the second wiring member 5, as shown in FIG.
【００３３】次に、図６に示すように、第１の配線部材
１上に例えば２個のＬＳＩチップ３を、その配線４のラ
ンド部４ａにその電極６を位置決めした状態で熱処理し
て、電極６を溶融させてランド部４ａに接続する。Next, as shown in FIG. 6, for example, two LSI chips 3 are heat-treated on the first wiring member 1 in a state where the electrodes 6 are positioned on the lands 4 a of the wirings 4. The electrode 6 is melted and connected to the land 4a.
【００３４】次に、図７に示すように、同様にして第２
の配線部材２上に例えば２個のＬＳＩチップ３を、その
配線５のランド部５ａにその電極６を位置決めした状態
で熱処理して、電極６を溶融させてランド部５ａに接続
する。Next, as shown in FIG.
For example, two LSI chips 3 are heat-treated on the wiring member 2 with the electrodes 6 positioned on the lands 5a of the wiring 5 to melt the electrodes 6 and connect them to the lands 5a.
【００３５】次に、図８に示すように、第１の配線部材
１と第２の配線部材２とを、ＬＳＩチップ３の電極６を
接続した面同士をＬＳＩチップ３の位置が重ならないよ
うに対向させ、第１の配線部材１および第２の配線部材
２のそれぞれのＬＳＩチップ３の裏面が接する位置に両
面テープなどの接着材７を設けるとともに、第１の配線
部材１と第２の配線部材２との間の周囲の位置に樹脂な
どの絶縁材料からなるスペーサ１４を配置する。また、
スペーサ１４が接する位置にも接着材７を設けておくよ
うにしてもよい。Next, as shown in FIG. 8, the first wiring member 1 and the second wiring member 2 are connected to each other by connecting the electrodes 6 of the LSI chip 3 so that the positions of the LSI chips 3 do not overlap. An adhesive 7 such as a double-sided tape is provided at a position where the back surface of each LSI chip 3 of the first wiring member 1 and the second wiring member 2 is in contact with the first wiring member 1 and the second wiring member 2. A spacer 14 made of an insulating material such as a resin is arranged at a position around the wiring member 2. Also,
The adhesive 7 may be provided at a position where the spacer 14 contacts.
【００３６】次に、第１の配線部材１および第２の配線
部材２を矢印方向に押圧することにより、図９に示すよ
うに、第１の配線部材１上の配線４に表面の電極６が接
続されている２個のＬＳＩチップ３の裏面を接着材７を
介して第２の配線部材２上に固定するとともに、第２の
配線部材２上の配線５に表面の電極６が接続されている
２個のＬＳＩチップ３の裏面を接着材７を介して第１の
配線部材１上に固定する。同時に、スペーサ１４を第１
の配線部材１および第２の配線部材２上に固定する。こ
れによって、複数のＬＳＩチップ３は第１の配線部材１
と第２の配線部材２との間に実装される。Next, by pressing the first wiring member 1 and the second wiring member 2 in the direction of the arrow, as shown in FIG. Are fixed on the second wiring member 2 via an adhesive 7, and the electrode 6 on the front surface is connected to the wiring 5 on the second wiring member 2. The back surfaces of the two LSI chips 3 are fixed on the first wiring member 1 via an adhesive 7. At the same time, the spacer 14 is
On the wiring member 1 and the second wiring member 2. Thereby, the plurality of LSI chips 3 are connected to the first wiring member 1.
And the second wiring member 2.
【００３７】次に、図１０に示すように、例えばアルミ
ニウム（Ａｌ）やステンレスなどの導電性材料からなる
箱状のケース１５を矢印方向に嵌入することにより、図
１に示したような電子装置が完成する。Next, as shown in FIG. 10, a box-shaped case 15 made of a conductive material such as aluminum (Al) or stainless steel is fitted in the direction of the arrow, thereby obtaining the electronic device as shown in FIG. Is completed.
【００３８】本実施の形態によれば、カード状の電子装
置は、複数のＬＳＩチップ３が第１の配線部材１と第２
の配線部材２との間に実装され、ＬＳＩチップ３の電極
６が接続される配線４、５は第１の配線部材１と第２の
配線部材２とに分けられて形成されるので、配線部材上
に形成される配線の引き回しを簡単にすることができ
る。すなわち、配線部材上に実装されるＬＳＩチップの
数が多くなっても、配線の引き回しを上部配線部材であ
る第１の配線部材１と下部配線部材である第２の配線部
材２とに二分して形成するので、ＬＳＩチップの実装密
度が高くなっても、配線部材上に形成される配線の密度
は従来のように高くはならない。According to the present embodiment, in the card-like electronic device, a plurality of LSI chips 3 are connected to the first wiring member 1 and the second
Since the wirings 4 and 5 mounted between the wiring member 2 and the electrodes 6 of the LSI chip 3 are formed separately from the first wiring member 1 and the second wiring member 2, the wiring Routing of the wiring formed on the member can be simplified. That is, even if the number of LSI chips mounted on the wiring member increases, the wiring routing is divided into the first wiring member 1 as the upper wiring member and the second wiring member 2 as the lower wiring member. Therefore, even if the mounting density of the LSI chip increases, the density of the wiring formed on the wiring member does not increase as in the related art.
【００３９】これに伴い、配線の形成に高精度の微細化
技術が要求されないので、コストアップが避けられるよ
うになる。Accordingly, a high-precision miniaturization technique is not required for forming the wiring, so that an increase in cost can be avoided.
【００４０】なお、図１の構造の電子装置において、入
出力端子８、９が形成されていない第１の配線部材１お
よび第２の配線部材２の他部において、第１の配線部材
１の配線４と第２の配線部材２の配線５とを所定の接続
関係となるような配線経路を設けることにより、複数の
ＬＳＩチップ３に対する電気信号を第１の配線部材１の
入出力端子８または第２の配線部材２の入出力端子９
を、共通の入出力端子として利用することができる。In the electronic device having the structure shown in FIG. 1, the other parts of the first wiring member 1 and the second wiring member 2 where the input / output terminals 8 and 9 are not formed have the same structure as the first wiring member 1. By providing a wiring path such that the wiring 4 and the wiring 5 of the second wiring member 2 have a predetermined connection relationship, electric signals to the plurality of LSI chips 3 can be transmitted to the input / output terminals 8 of the first wiring member 1 or Input / output terminal 9 of second wiring member 2
Can be used as a common input / output terminal.
【００４１】（実施の形態２）本実施の形態では、第１
の配線部材および第２の配線部材の一部および他部に入
出力端子を設けた例を示すもので、図１１を用いてその
構造を説明する。(Embodiment 2) In this embodiment, the first
This is an example in which input / output terminals are provided on a part and another part of the wiring member and the second wiring member. The structure will be described with reference to FIG.
【００４２】すなわち、図１１に示すように、第１の配
線部材１の一部および他部に入出力端子８を設けるとと
もに、第２の配線部材２の一部および他部にも入出力端
子９を設けるようにする。この場合、第１の配線部材１
および第２の配線部材２の周囲は、筒状のケース１６に
よって覆われる。That is, as shown in FIG. 11, an input / output terminal 8 is provided on a part and the other part of the first wiring member 1, and an input / output terminal is also provided on a part and the other part of the second wiring member 2. 9 is provided. In this case, the first wiring member 1
The periphery of the second wiring member 2 is covered with a cylindrical case 16.
【００４３】本実施の形態によれば、電子装置は、第１
の配線部材１の一部および他部に設けられた入出力端子
８を通じて、第１の配線部材１の配線４に電極６が接続
されたＬＳＩチップ３に対する電気信号が入出力可能に
なり、また、第２の配線部材２の一部および他部に設け
られた入出力端子９を通じて、第２の配線部材２の配線
５に電極６が接続されたＬＳＩチップ３に対する電気信
号が入出力可能になる。従って、必要に応じて何れかの
入出力端子８、９を利用してＬＳＩチップ３に対する電
気信号が入出力可能になるので、利用の自由度が広まる
という効果が得られる。According to the present embodiment, the electronic device comprises the first
Through the input / output terminals 8 provided on a part of the wiring member 1 and other parts, an electric signal to / from the LSI chip 3 having the electrode 6 connected to the wiring 4 of the first wiring member 1 can be input / output. An electric signal can be input / output to / from the LSI chip 3 having the electrode 6 connected to the wiring 5 of the second wiring member 2 through input / output terminals 9 provided on a part of the second wiring member 2 and another part. Become. Therefore, an electric signal can be input / output to / from the LSI chip 3 by using one of the input / output terminals 8 and 9 as needed, so that the effect of increasing the degree of freedom of use is obtained.
【００４４】（実施の形態３）本実施の形態では、第１
の配線部材および第２の配線部材の一部および他部に入
出力端子を設ける場合、一部に各々の一方側の入出力端
子同士を導通させるソケットを接続するようにした例を
示すもので、図１２を用いてその構造を説明する。(Embodiment 3) In this embodiment, the first
In the case where input / output terminals are provided in a part and another part of the wiring member and the second wiring member, an example is shown in which a socket for connecting the input / output terminals on one side to each other is connected to a part. The structure will be described with reference to FIG.
【００４５】すなわち、図１２に示すように、第１の配
線部材１の一部および他部に入出力端子８を設けるとと
もに、第２の配線部材２の一部および他部にも入出力端
子９を設けるようにした場合、第１の配線部材１および
第２の配線部材２の一部に各々の一方側の入出力端子
８、９同士を導通させるソケット１７を接続するように
する。ソケット１７には導通用配線１８が形成されてい
る。第１の配線部材１および第２の配線部材２の周囲
は、筒状のケース１６によって覆われる。That is, as shown in FIG. 12, an input / output terminal 8 is provided on a part and the other part of the first wiring member 1, and an input / output terminal is also provided on a part and the other part of the second wiring member 2. In the case where 9 is provided, a socket 17 that connects the input / output terminals 8 and 9 on one side to each other is connected to a part of the first wiring member 1 and a part of the second wiring member 2. The socket 17 is provided with a conductive wiring 18. The periphery of the first wiring member 1 and the second wiring member 2 is covered by a cylindrical case 16.
【００４６】本実施の形態によれば、電子装置は、第１
の配線部材１上に裏面が固定されたＬＳＩチップ３およ
び第２の配線部材２上に裏面が固定されたＬＳＩチップ
３に対する電気信号は、第１の配線部材１または第２の
配線部材２の他方側の入出力端子８、９を通じて入出力
可能となる。従って、何れか側の入出力端子８、９を利
用してＬＳＩチップ３に対する電気信号が入出力可能に
なるので、利用の自由度が広まるという効果が得られ
る。なお、ソケット１７は着脱自在にできる。According to the present embodiment, the electronic device comprises the first
The electric signal to the LSI chip 3 having the back surface fixed on the wiring member 1 and the LSI chip 3 having the back surface fixed on the second wiring member 2 is the electric signal of the first wiring member 1 or the second wiring member 2. Input / output is enabled through the input / output terminals 8 and 9 on the other side. Therefore, since it becomes possible to input and output electric signals to and from the LSI chip 3 by using the input / output terminals 8 and 9 on either side, it is possible to obtain an effect that the degree of freedom of use is increased. The socket 17 can be detached.
【００４７】なお、本発明の変形例として、図１３に示
すように、第１の配線部材１と第２の配線部材２との一
端部同士をテープ１９によって接着して、両配線部材
１、２を平面上に広げて利用するようにできる。この場
合、第１の配線部材１上の配線４と第２の配線部材２上
の配線５とを導通させるようにする。このような利用方
法は、特に細長いスペースを必要とするような用途に適
用することにより効果的となる。As a modification of the present invention, as shown in FIG. 13, one ends of the first wiring member 1 and the second wiring member 2 are adhered to each other with a tape 19, and 2 can be used by spreading it on a plane. In this case, the wiring 4 on the first wiring member 1 and the wiring 5 on the second wiring member 2 are made conductive. Such a use method is particularly effective when applied to an application requiring an elongated space.
【００４８】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲において種々変更可能であることは言う
までもない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.
【００４９】例えば、前記実施の形態で示した、第１の
配線部材および第２の配線部材は、基板状の材料に限る
ことなく、ポリイミド樹脂などからなるテープを用いて
構成することができる。この場合も、必要な位置には配
線や入出力端子を設けておくことにより、同等の機能を
持たせることができる。For example, the first wiring member and the second wiring member shown in the above-mentioned embodiment can be constituted by using a tape made of polyimide resin or the like without being limited to the substrate-like material. Also in this case, by providing wiring and input / output terminals at necessary positions, equivalent functions can be provided.
【００５０】また、前記実施の形態で示した、第１の配
線部材と第２の配線部材との間に実装するＬＳＩチップ
の種類は必要に応じて任意の素子を選択することができ
る。The type of the LSI chip mounted between the first wiring member and the second wiring member shown in the above-described embodiment can be arbitrarily selected as needed.
【００５１】また、第１の配線部材および第２の配線部
材の全体を覆うように樹脂モールドを行うようにしても
よい。ただし、樹脂モールド時の樹脂の流れによって、
ＬＳＩチップに不要な力が加わって、信号経路の断線が
生ずる場合も考えられるので、樹脂モールドは必ずしも
必要ではない。Further, resin molding may be performed so as to cover the whole of the first wiring member and the second wiring member. However, due to the flow of resin during resin molding,
It is possible that an unnecessary force is applied to the LSI chip to cause a disconnection of the signal path. Therefore, the resin mold is not always necessary.
【００５２】[0052]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば以
下のとおりである。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００５３】（１）複数のＬＳＩチップを配線部材上に
実装する電子装置において、配線部材上の配線の引き回
しを簡単にすることができる。(1) In an electronic device in which a plurality of LSI chips are mounted on a wiring member, routing of wiring on the wiring member can be simplified.
【００５４】（２）複数のＬＳＩチップを配線部材上に
実装する電子装置を、コストアップを伴うことなく製造
できる。(2) An electronic device in which a plurality of LSI chips are mounted on a wiring member can be manufactured without increasing the cost.
【図１】本発明の実施の形態１である電子装置を示す断
面図である。FIG. 1 is a cross-sectional view illustrating an electronic device according to a first embodiment of the present invention.
【図２】本発明の実施の形態１である電子装置の主要部
を示す断面図である。FIG. 2 is a cross-sectional view illustrating a main part of the electronic device according to the first embodiment of the present invention.
【図３】本発明の実施の形態１である電子装置の主要部
を示す断面図である。FIG. 3 is a cross-sectional view illustrating a main part of the electronic device according to the first embodiment of the present invention.
【図４】本発明の実施の形態１である電子装置の製造方
法を示す平面図である。FIG. 4 is a plan view showing the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図５】本発明の実施の形態１である電子装置の製造方
法を示す平面図である。FIG. 5 is a plan view showing the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図６】本発明の実施の形態１である電子装置の製造方
法を示す断面図である。FIG. 6 is a sectional view illustrating the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図７】本発明の実施の形態１である電子装置の製造方
法を示す断面図である。FIG. 7 is a sectional view illustrating the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図８】本発明の実施の形態１である電子装置の製造方
法を示す断面図である。FIG. 8 is a sectional view illustrating the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図９】本発明の実施の形態１である電子装置の製造方
法を示す断面図である。FIG. 9 is a sectional view illustrating the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図１０】本発明の実施の形態１である電子装置の製造
方法を示す断面図である。FIG. 10 is a sectional view illustrating the method for manufacturing the electronic device according to the first embodiment of the present invention.
【図１１】本発明の実施の形態２である電子装置を示す
断面図である。FIG. 11 is a sectional view showing an electronic device according to a second embodiment of the present invention.
【図１２】本発明の実施の形態３である電子装置を示す
断面図である。FIG. 12 is a sectional view showing an electronic device according to a third embodiment of the present invention.
【図１３】本発明の電子装置の変形例を示す断面図であ
る。FIG. 13 is a cross-sectional view illustrating a modification of the electronic device of the present invention.
１ 第１の配線部材（上部配線部材） ２ 第２の配線部材（下部配線部材） ３ ＬＳＩチップ ４ 配線 ４ａ ランド部 ５ 配線 ５ａ ランド部 ６ 電極（バンブ状の電極） ７ 接着材 ８ 入出力端子 ９ 入出力端子 １０ 中間配線 １１ 中間配線 １２ スルーホール配線 １３ スルーホール配線 １４ スペーサ １５ 箱状のケース １６ 筒状のケース １７ ソケット １８ 導通用配線 １９ テープ DESCRIPTION OF SYMBOLS 1 1st wiring member (upper wiring member) 2 2nd wiring member (lower wiring member) 3 LSI chip 4 wiring 4a land part 5 wiring 5a land part 6 electrode (bump-shaped electrode) 7 adhesive 8 input / output terminal Reference Signs 9 I / O terminal 10 Intermediate wiring 11 Intermediate wiring 12 Through-hole wiring 13 Through-hole wiring 14 Spacer 15 Box-shaped case 16 Cylindrical case 17 Socket 18 Conduction wiring 19 Tape
───────────────────────────────────────────────────── フロントページの続き (72)発明者 落合 俊彦 東京都青梅市藤橋３丁目３番地２ 日立東 京エレクトロニクス株式会社内 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toshihiko Ochiai 3-3-2 Fujibashi, Ome-shi, Tokyo Inside Hitachi Tokyo Electronics Co., Ltd.
Claims (9)
され、前記配線部材に設けられた入出力端子を通じて外
部から前記ＬＳＩチップに対する電気信号が入出力可能
に構成されている電子装置であって、 前記配線部材は第１の配線部材と第２の配線部材とから
なり、前記複数のＬＳＩチップは前記第１の配線部材と
前記第２の配線部材との間に実装されて、前記第１の配
線部材上に裏面が固定された前記ＬＳＩチップはその表
面の電極が前記第２の配線部材上の配線に接続され、前
記第２の配線部材上に裏面が固定された前記ＬＳＩチッ
プはその表面の電極が前記第１の配線部材上の配線に接
続されていることを特徴とする電子装置。1. An electronic device having a plurality of LSI chips mounted on a wiring member and configured to be capable of externally inputting / outputting an electric signal to / from the LSI chip through input / output terminals provided on the wiring member. The wiring member includes a first wiring member and a second wiring member, and the plurality of LSI chips are mounted between the first wiring member and the second wiring member, and The LSI chip having the back surface fixed on the wiring member of the above has an electrode on the front surface connected to the wiring on the second wiring member, and the LSI chip having the back surface fixed on the second wiring member is An electronic device, wherein an electrode on a surface is connected to a wiring on the first wiring member.
特徴とする電子装置。2. The electronic device according to claim 1, wherein the electrode of the LSI chip comprises a bump electrode.
て、 前記第１の配線部材および前記第２の配線部材の一部に
入出力端子が設けられ、前記第１の配線部材上に裏面が
固定された前記ＬＳＩチップに対する電気信号は前記第
２の配線部材の前記入出力端子を通じて入出力可能に構
成され、前記第２の配線部材上に裏面が固定された前記
ＬＳＩチップに対する電気信号は前記第１の配線部材の
前記入出力端子を通じて入出力可能に構成されているこ
とを特徴とする電子装置。3. The electronic device according to claim 1, wherein an input / output terminal is provided on a part of the first wiring member and a part of the second wiring member, and the input / output terminal is provided on the first wiring member. An electric signal to the LSI chip with the back surface fixed is configured to be input / output through the input / output terminal of the second wiring member, and an electric signal to the LSI chip with the back surface fixed on the second wiring member. An electronic device configured to be able to input and output through the input and output terminals of the first wiring member.
て、 前記第１の配線部材および第２の配線部材の一部に入出
力端子が設けられ、前記第１の配線部材上に裏面が固定
された前記ＬＳＩチップおよび前記第２の配線部材上に
裏面が固定された前記ＬＳＩチップに対する電気信号
は、前記第１の配線部材または第２の配線部材の前記入
出力端子を通じて入出力可能に構成されていることを特
徴とする電子装置。4. The electronic device according to claim 1, wherein an input / output terminal is provided on a part of the first wiring member and a part of the second wiring member, and a back surface is provided on the first wiring member. An electric signal to the LSI chip with the fixed surface and the LSI chip with the back surface fixed on the second wiring member can be input / output through the input / output terminal of the first wiring member or the second wiring member. An electronic device, comprising:
て、 前記第１の配線部材および前記第２の配線部材の一部お
よび他部に入出力端子が設けられ、前記第１の配線部材
上に裏面が固定された前記ＬＳＩチップに対する電気信
号は前記第２の配線部材のいずれか一方側の前記入出力
端子を通じて入出力可能に構成され、前記第２の配線部
材上に裏面が固定された前記ＬＳＩチップに対する電気
信号は前記第１の配線部材のいずれか一方側の前記入出
力端子を通じて入出力可能に構成されていることを特徴
とする電子装置。5. The electronic device according to claim 1, wherein an input / output terminal is provided on a part and another part of the first wiring member and the second wiring member, and the first wiring is provided. An electric signal to the LSI chip having a back surface fixed on a member is configured to be able to be input and output through the input / output terminal on either side of the second wiring member, and the back surface is fixed on the second wiring member. An electronic device, wherein an electrical signal to the LSI chip is input / output via the input / output terminal on one side of the first wiring member.
て、 前記第１の配線部材および第２の配線部材の一部および
他部に入出力端子が設けられ、前記第１の配線部材およ
び前記第２の配線部材の一部あるいは他部に各々の一方
側の前記入出力端子同士を導通させるソケットが接続さ
れ、前記第１の配線部材上に裏面が固定された前記ＬＳ
Ｉチップおよび前記第２の配線部材上に裏面が固定され
た前記ＬＳＩチップに対する電気信号は、前記第１の配
線部材または第２の配線部材の他方側の前記入出力端子
を通じて入出力可能に構成されていることを特徴とする
電子装置。6. The electronic device according to claim 1, wherein an input / output terminal is provided on a part and another part of the first wiring member and the second wiring member, and the first wiring member is provided. And a LS having a back surface fixed to the first wiring member, wherein a socket for electrically connecting the input / output terminals on one side to each other is connected to a part or another portion of the second wiring member.
An electrical signal to the I chip and the LSI chip whose back surface is fixed on the second wiring member can be input / output through the input / output terminal on the other side of the first wiring member or the second wiring member. An electronic device, comprising:
られた第１の配線部材上に、ＬＳＩチップをその表面の
電極を前記配線に接続する工程、（ｂ）配線と導通する
入出力端子が設けられた第２の配線部材上に、他のＬＳ
Ｉチップをその表面の電極を前記配線に接続する工程、
（ｃ）前記第１の配線部材と前記第２の配線部材とを、
各々前記ＬＳＩチップの前記電極を接続した面同士を前
記ＬＳＩチップの位置が重ならないように対向させると
ともに、前記第１の配線部材と前記第２の配線部材との
間の周囲の位置にスペーサを配置する工程、（ｄ）前記
第１の配線部材および前記第２の配線部材を押圧するこ
とにより、前記第１の配線部材上の前記配線に表面の電
極が接続されている前記ＬＳＩチップの裏面を前記第２
の配線部材上に固定するとともに、前記第２の配線部材
上の前記配線に表面の電極が接続されている前記ＬＳＩ
チップの裏面を前記第１の配線部材上に固定し、同時に
前記スペーサを前記第１の配線部材上および第２の配線
部材上に固定する工程、（ｅ）前記第１の配線部材およ
び第２の配線部材の前記入出力端子を除いた周囲を箱状
のケースで覆う工程、を含むことを特徴とする電子装置
の製造方法。7. A step of connecting an LSI chip electrode to the wiring on a first wiring member provided with an input / output terminal conductive to the wiring, and FIG. On the second wiring member provided with the output terminal, another LS
Connecting an I-chip to an electrode on the surface of the I-chip,
(C) connecting the first wiring member and the second wiring member,
The surfaces of the LSI chips to which the electrodes are connected are opposed to each other so that the positions of the LSI chips do not overlap, and a spacer is provided at a peripheral position between the first wiring member and the second wiring member. (D) pressing the first wiring member and the second wiring member so that the back surface of the LSI chip in which electrodes on the front surface are connected to the wiring on the first wiring member; The second
Said LSI fixed on the wiring member of the above, and the electrode on the surface is connected to the wiring on the second wiring member.
Fixing the back surface of the chip on the first wiring member and simultaneously fixing the spacer on the first wiring member and the second wiring member; (e) the first wiring member and the second wiring member; Covering the periphery of the wiring member excluding the input / output terminals with a box-shaped case.
って、 前記ＬＳＩチップの裏面の前記第１の配線部材または前
記第２の配線部材上への固定は接着材を介して行うこと
を特徴とする電子装置の製造方法。8. The method for manufacturing an electronic device according to claim 7, wherein the fixing of the back surface of the LSI chip on the first wiring member or the second wiring member is performed via an adhesive. A method for manufacturing an electronic device, comprising:
方法であって、 前記第１の配線部材および第２の配線部材として、その
一部および他部に入出力端子を設けたものを用いること
を特徴とする電子装置の製造方法。9. The method for manufacturing an electronic device according to claim 7, wherein the first wiring member and the second wiring member are provided with input / output terminals in a part and another part thereof. A method for manufacturing an electronic device, wherein the method is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9338687A JPH11177014A (en) | 1997-12-09 | 1997-12-09 | Electronic device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9338687A JPH11177014A (en) | 1997-12-09 | 1997-12-09 | Electronic device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11177014A true JPH11177014A (en) | 1999-07-02 |
Family
ID=18320519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9338687A Pending JPH11177014A (en) | 1997-12-09 | 1997-12-09 | Electronic device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11177014A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006203086A (en) * | 2005-01-24 | 2006-08-03 | Citizen Electronics Co Ltd | Electronic part package and manufacturing method thereof |
-
1997
- 1997-12-09 JP JP9338687A patent/JPH11177014A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006203086A (en) * | 2005-01-24 | 2006-08-03 | Citizen Electronics Co Ltd | Electronic part package and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9305861B2 (en) | Method and system for electrically coupling a chip to chip package | |
| US4941033A (en) | Semiconductor integrated circuit device | |
| US6774473B1 (en) | Semiconductor chip module | |
| US4860087A (en) | Semiconductor device and process for producing the same | |
| JP2002043503A (en) | Semiconductor device | |
| CN103620775A (en) | Stacked chip-on-board module with edge connector | |
| JP2003017649A (en) | Semiconductor device and semiconductor module | |
| US6825568B2 (en) | Flip chip package structure and flip chip device with area bump | |
| KR100336081B1 (en) | Semiconductor chip | |
| JPH11177014A (en) | Electronic device and manufacture thereof | |
| JP2821315B2 (en) | Single inline module | |
| JPH11186492A (en) | Semiconductor package and its mounting structure | |
| JPH06177322A (en) | Memory element | |
| JPH09330952A (en) | Printed circuit board and method for laminating semiconductor chip | |
| JPH1174421A (en) | Composite semiconductor device | |
| JPH104122A (en) | Semiconductor device | |
| JP2004031432A (en) | Semiconductor device | |
| JPH07282218A (en) | Semiconductor integrated circuit device | |
| JPH06350025A (en) | Semiconductor device | |
| JPH11185001A (en) | Ic module for ic card | |
| JPH0969587A (en) | Bga type semiconductor device and bga module | |
| JP2000164627A (en) | Semiconductor device, module, and ic card provided with it | |
| JPH07255025A (en) | Liquid crystal display module | |
| JPH10163415A (en) | Semiconductor device and module | |
| JPH0373550A (en) | Wire bonder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |