JPH1117057A - Bga type semiconductor device with inspection pads - Google Patents
Bga type semiconductor device with inspection padsInfo
- Publication number
- JPH1117057A JPH1117057A JP9169771A JP16977197A JPH1117057A JP H1117057 A JPH1117057 A JP H1117057A JP 9169771 A JP9169771 A JP 9169771A JP 16977197 A JP16977197 A JP 16977197A JP H1117057 A JPH1117057 A JP H1117057A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- printed circuit
- circuit board
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＢＧＡ（Ball Gri
d Array ）型半導体装置に関し、特に検査パッドを有す
る半導体装置に関する。TECHNICAL FIELD The present invention relates to a BGA (Ball Gri
d Array) type semiconductor device, and more particularly to a semiconductor device having a test pad.
【０００２】[0002]
【従来の技術】半導体装置、特にＩＣチップが樹脂やセ
ラミックで封止された半導体装置では、半導体装置をプ
リント基板に実装する前に半導体装置の電気的特性を検
査するための検査パッドが設けられる。従来、この種の
ＢＧＡ型半導体装置として、例えば特開平８−７５５４
号公報に示されるものがある。図４は、このＢＧＡ型半
導体装置１’の一例の断面図である。半導体装置の基板
２の表面及び裏面にはそれぞれ所要パターンの配線３，
５が形成されており、表裏面の各配線はスルーホール８
により相互に電気接続されている。前記基板２の表面に
はＩＣチップ９が搭載され、ＩＣチップ９の電極パッド
と配線パターンとはボンデイングワイヤ１０により接続
され、かつ前記ＩＣチップ９及びボンデイングワイヤ１
０はモールド樹脂１１により封止されている。また、前
記基板２の裏面の配線５の一部は外部電極パッド６とし
て格子状に配列形成されており、各パッド６には半田バ
ンプ７が形成されている。そして、前記配線５の他の一
部を利用して前記半田バンプ７に隣接する位置に検査パ
ッド４Ａが形成されている。2. Description of the Related Art In a semiconductor device, particularly a semiconductor device in which an IC chip is sealed with a resin or ceramic, an inspection pad for inspecting electrical characteristics of the semiconductor device before mounting the semiconductor device on a printed circuit board is provided. . Conventionally, as this type of BGA type semiconductor device, for example, Japanese Patent Laid-Open No.
There is one shown in Japanese Patent Publication No. FIG. 4 is a sectional view of an example of the BGA type semiconductor device 1 '. Wiring 3 of a required pattern is provided on the front and back surfaces of the substrate 2 of the semiconductor device, respectively.
5 are formed, and each wiring on the front and back surfaces is a through hole 8.
Are electrically connected to each other. An IC chip 9 is mounted on the surface of the substrate 2, an electrode pad of the IC chip 9 is connected to a wiring pattern by a bonding wire 10, and the IC chip 9 and the bonding wire 1 are connected.
Numeral 0 is sealed by a mold resin 11. Further, a part of the wiring 5 on the back surface of the substrate 2 is arranged and formed in a grid pattern as external electrode pads 6, and a solder bump 7 is formed on each pad 6. An inspection pad 4A is formed at a position adjacent to the solder bump 7 using another part of the wiring 5.
【０００３】したがって、この構造では、ＢＧＡ型半導
体装置１を単体検査する場合には、基板２の裏面側に露
呈されている検査パッド４Ａに検査装置（テスタ）のプ
ローブを接触させ、テスタを通して半導体装置に通電を
行うことで検査が実現できる。しかしながら、この半導
体装置１’では、図５に示すように、プリント基板２１
に実装する際には、基板２の裏面側をプリント基板２１
の表面に対向させ、半田バンプ７を利用してプリント基
板２１に接続する構成とされるため、実装した後には検
査パッド４Ａが基板２の裏面側に隠れることになり、テ
スタのプローブを検査パッドに接触させることが困難と
なり、実質的な検査は困難になる。Accordingly, in this structure, when the BGA type semiconductor device 1 is to be inspected as a single unit, the probe of the inspection device (tester) is brought into contact with the inspection pad 4A exposed on the back side of the substrate 2, and the semiconductor is passed through the tester. Inspection can be realized by energizing the apparatus. However, in this semiconductor device 1 ', as shown in FIG.
When mounting on a printed circuit board 21,
Is connected to the printed circuit board 21 by using the solder bumps 7 so that the test pad 4A is hidden on the back side of the substrate 2 after mounting. And it is difficult to make a substantial inspection.
【０００４】そこで、従来では、図５に示すように、半
導体装置を実装するプリント基板２１に、実装した半導
体装置１’に隠されることがない領域に検査パッド２３
を配設することが提案されており、この検査パッド２３
に対してテスタのプローブ２２を接触させることで、半
導体装置１’をプリント基板２１に実装した状態での検
査を可能としている。Conventionally, as shown in FIG. 5, a test pad 23 is provided on a printed circuit board 21 on which a semiconductor device is mounted, in a region which is not hidden by the mounted semiconductor device 1 '.
It is proposed that the test pad 23
By contacting the probe 22 of the tester with the semiconductor device 1, the inspection in a state where the semiconductor device 1 ′ is mounted on the printed circuit board 21 is enabled.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この提
案されている構成では、プリント基板２１に検査パッド
２３を配設するためのスペースを確保しなければならな
いため、プリント基板における半導体装置の実装効率が
低下される原因となっている。However, in the proposed structure, a space for arranging the inspection pads 23 on the printed circuit board 21 must be ensured, so that the mounting efficiency of the semiconductor device on the printed circuit board is reduced. This is the cause of the decline.
【０００６】本発明の目的は、プリント基板における実
装効率を低下させることなく、当該プリント基板に実装
した状態でも特性検査を可能にしたＢＧＡ型半導体装置
を提供することにある。An object of the present invention is to provide a BGA type semiconductor device capable of performing a characteristic inspection even in a state of being mounted on a printed circuit board without lowering the mounting efficiency on the printed circuit board.
【０００７】[0007]
【課題を解決するための手段】本発明は、基板の表面上
にＩＣチップが搭載され、前記基板の裏面に前記ＩＣチ
ップに電気接続される複数個の外部電極パッドが配列形
成されているＢＧＡ型半導体装置において、前記基板の
表面に前記ＩＣチップに電気接続される検査パッドが配
設され、この検査パッドに対してテスト用のプローブが
接触可能に構成されていることを特徴とする。例えば、
基板の表面と裏面のそれぞれに形成された配線と、前記
各配線を相互に電気接続するために前記基板に設けられ
たスルーホールと、前記基板の表面に搭載されたＩＣチ
ップと、前記ＩＣチップを前記基板表面の配線に電気接
続する手段と、前記基板裏面の配線によって格子状に配
列形成された外部電極パッドと、前記基板表面の配線の
一部で構成される検査パッドとを備える構成とされる。According to the present invention, there is provided a BGA in which an IC chip is mounted on a front surface of a substrate, and a plurality of external electrode pads electrically connected to the IC chip are formed on the rear surface of the substrate. In the semiconductor device, a test pad electrically connected to the IC chip is provided on a surface of the substrate, and a test probe can be brought into contact with the test pad. For example,
A wiring formed on each of a front surface and a back surface of the substrate, a through hole provided in the substrate for electrically connecting the wirings to each other, an IC chip mounted on the surface of the substrate, and the IC chip Means for electrically connecting to the wiring on the surface of the substrate, external electrode pads arranged in a grid pattern by the wiring on the rear surface of the substrate, and a test pad comprising a part of the wiring on the surface of the substrate. Is done.
【０００８】本発明のＢＧＡ型半導体装置では、検査パ
ッドが半導体装置の表面に配設されているため、半導体
装置を実装した状態でも半導体装置の上側からテスタの
プローブを接触させての特性検査が可能とされるため、
半導体装置を実装するプリント基板に検査パッドを配設
する必要がなく、実装した半導体装置に近接して他の半
導体装置を実装することが可能となり、プリント基板の
実装効率が向上される。In the BGA type semiconductor device of the present invention, since the test pad is provided on the surface of the semiconductor device, even when the semiconductor device is mounted, the characteristic test can be performed by contacting the probe of the tester from above the semiconductor device. To be possible,
It is not necessary to dispose an inspection pad on a printed circuit board on which the semiconductor device is mounted, and it is possible to mount another semiconductor device close to the mounted semiconductor device, thereby improving the mounting efficiency of the printed circuit board.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１（ａ）及び（ｂ）は、本発明の
ＢＧＡ型半導体装置１の一実施形態の一部を破断した上
面図とそのＡＡ線断面図である。セラミック等の絶縁性
の基板２の表面には所要パターンの配線３が形成され、
ているが、基板２の周辺部には前記配線３の一部によっ
て多数個の検査パッド４として形成されている。また、
前記基板２の裏面には配線５により多数個の外部電極パ
ッド６が格子状に配列形成されており、その表面には半
田バンプ７が形成されている。そして、前記基板２の表
面と裏面の各配線３，５は、基板２を厚さ方向に貫通す
るスルーホール８によって相互に電気接続されている。
また、前記基板２の表面上には、ＩＣチップ９が搭載さ
れ、ボンデイングワイヤ１０にて前記配線３に電気接続
されるとともに、これらＩＣチップ９とボンディングワ
イヤ１０を含む領域はモールド樹脂１１によって封止さ
れている。Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are a partially cutaway top view and a cross-sectional view taken along the line AA of an embodiment of the BGA type semiconductor device 1 of the present invention. Wiring 3 having a required pattern is formed on the surface of an insulating substrate 2 such as a ceramic.
However, a large number of test pads 4 are formed on the periphery of the substrate 2 by a part of the wiring 3. Also,
A large number of external electrode pads 6 are arranged in a grid on the back surface of the substrate 2 by wirings 5, and solder bumps 7 are formed on the surface thereof. The wirings 3 and 5 on the front and back surfaces of the substrate 2 are electrically connected to each other by through holes 8 penetrating the substrate 2 in the thickness direction.
An IC chip 9 is mounted on the surface of the substrate 2 and is electrically connected to the wiring 3 by a bonding wire 10, and a region including the IC chip 9 and the bonding wire 10 is sealed by a mold resin 11. Has been stopped.
【００１０】図２は図１のＢＧＡ型半導体装置１の要部
の拡大断面図である。基板２の表面及び裏面にそれぞれ
形成された配線３，５は、基板２を貫通するスルーホー
ル８によって相互に電気接続されており、かつ前記基板
２の表面と裏面にはそれぞれソルダレジスト１２，１３
が形成され、このソルダレジスト１２，１３によって前
記各配線３，５は被覆され、保護されている。そして、
このソルダレジスト１２，１３を部分的に除去して下層
の前記各配線３，５の一部を露呈させることで、前記し
た各パッド４，６を形成しており、特に基板２の裏面で
はこのパッド６を外部電極パッドとして前記半田バンプ
７を形成している。一方、前記基板２の表面では単にソ
ルダレジスト１２を除去した部分を露呈させてパッド４
を形成しており、このパッドを検査パッドとして構成し
ている。したがって、検査パッド４を形成するために特
別な工程が必要とされることはない。ここで、前記検査
パッド４は、基板２の裏面に形成した外部電極パッド６
に対応して同一ピッチの格子状に配列形成されている。FIG. 2 is an enlarged sectional view of a main part of the BGA type semiconductor device 1 of FIG. Wirings 3 and 5 formed on the front and back surfaces of the substrate 2 are electrically connected to each other by through holes 8 penetrating the substrate 2, and solder resists 12 and 13 are provided on the front and back surfaces of the substrate 2, respectively.
The wirings 3 and 5 are covered and protected by the solder resists 12 and 13, respectively. And
The pads 4 and 6 are formed by partially removing the solder resists 12 and 13 and exposing a part of the wirings 3 and 5 in the lower layer. The solder bumps 7 are formed using the pads 6 as external electrode pads. On the other hand, on the surface of the substrate 2, the portion where the solder resist 12 is simply removed is exposed to expose the pad 4.
Is formed, and this pad is configured as an inspection pad. Therefore, no special process is required for forming the inspection pad 4. Here, the inspection pad 4 is formed of an external electrode pad 6 formed on the back surface of the substrate 2.
Corresponding to the same pitch.
【００１１】このように構成された、ＢＧＡ型半導体装
置１は、図３に示すように、プリント基板２１に実装す
る際には、これまでと同様に基板２の裏面に配設されて
いる半田バンプ７を利用したフェースダウンボンディン
グ法によって、プリント基板２１の表面に形成されてい
る図外の配線に接続することで、機械的及び電気的な実
装が実現される。そして、この実装された状態では、基
板２の表面に形成されている検査パッド４に対して図外
のテスタのプローブ２２を接触させ、テスタを通して通
電を行うことにより半導体装置１の特性検査を行なうこ
とができる。この場合、検査パッド４においては、図２
に示した基板２の表面のソルダレジスト１２の除去部分
にプローブ２２を当接することで、この部分に露呈され
ている配線３にプルーブが接触されて電気接続されるこ
とは言うまでもない。As shown in FIG. 3, when the BGA type semiconductor device 1 configured as described above is mounted on a printed circuit board 21, the solder disposed on the back surface of the substrate 2 is the same as before. By connecting to a wiring (not shown) formed on the surface of the printed circuit board 21 by a face-down bonding method using the bumps 7, mechanical and electrical mounting is realized. In this mounted state, a probe 22 of a tester (not shown) is brought into contact with an inspection pad 4 formed on the surface of the substrate 2, and a characteristic test of the semiconductor device 1 is performed by conducting electricity through the tester. be able to. In this case, in the inspection pad 4, FIG.
It goes without saying that the probe 22 is brought into contact with the portion of the surface of the substrate 2 where the solder resist 12 is removed as shown in FIG.
【００１２】したがって、プリント基板２１に検査パッ
ドを設けなくとも実装した半導体装置１の特性検査が可
能となり、図３に示すように、プリント基板２１に複数
個の半導体装置を実装する場合に、隣接される他の半導
体装置１Ａを近接配置することが可能となり、プリント
基板２１における半導体装置の実装効率を高めることが
可能となる。また、この実施形態のように、検査パッド
４を半田バンプ７を形成した外部電極パッド６と同一ピ
ッチの格子状に形成していることで、テスタのプローブ
２２は前記検査パッド４のみならず、半導体装置の上下
を逆向きにしたときに外部電極パッド（半田ハンプ）６
に接触が可能であり、かつまたプリント基板２１に形成
した実装用の配線パターンにも接触可能であるために、
実装前の半導体装置１の外部電極パッド６やプリント基
板２１の配線にそれぞれプローブ２２を接触させて、こ
れらの試験を行うことも可能となり、テスタの汎用性を
高めることができる。Therefore, it is possible to inspect the characteristics of the semiconductor device 1 mounted on the printed circuit board 21 without providing an inspection pad, and when mounting a plurality of semiconductor devices on the printed circuit board 21 as shown in FIG. It is possible to arrange another semiconductor device 1 </ b> A in close proximity, and to improve the mounting efficiency of the semiconductor device on the printed circuit board 21. Further, as in this embodiment, the test pads 4 are formed in a grid pattern having the same pitch as the external electrode pads 6 on which the solder bumps 7 are formed, so that the probe 22 of the tester is not only the test pad 4 but also When the semiconductor device is turned upside down, the external electrode pad (solder hump) 6
, And also can be in contact with the mounting wiring pattern formed on the printed circuit board 21,
These tests can be performed by bringing the probes 22 into contact with the external electrode pads 6 of the semiconductor device 1 before mounting and the wiring of the printed circuit board 21, respectively, and the versatility of the tester can be improved.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、半導体装
置の表面に検査パッドが設けられているので、半導体装
置をプリント基板に実装した状態で半導体装置の検査が
実行できるため、プリント基板に検査パッドを設ける必
要がなく、本発明のＢＧＡ型半導体装置を実装するプリ
ント基板の実装効率を向上することができる。また、検
査パッドは、基板表面の配線を覆う絶縁膜の一部を除去
し、その部分に配線を露呈させる構成とすることによ
り、検査パッドを形成するために特別な工程は不要とな
り、容易に製造することが可能となる。また、検査パッ
ドを外部電極パッドと同じ格子状に形成することによ
り、テスタのプローブの汎用性を高めることが可能とな
る。。As described above, according to the present invention, since the inspection pads are provided on the surface of the semiconductor device, the inspection of the semiconductor device can be performed in a state where the semiconductor device is mounted on the printed circuit board. There is no need to provide an inspection pad, and the mounting efficiency of a printed circuit board on which the BGA type semiconductor device of the present invention is mounted can be improved. In addition, the inspection pad has a configuration in which a part of the insulating film covering the wiring on the substrate surface is removed and the wiring is exposed to that part, so that a special process for forming the inspection pad is not required, and the inspection pad can be easily formed. It can be manufactured. Further, by forming the inspection pads in the same grid as the external electrode pads, it is possible to increase the versatility of the probe of the tester. .
【図１】本発明の実施形態の一部を破断した上面図と、
そのＡＡ線断面図である。FIG. 1 is a top view in which a part of an embodiment of the present invention is broken;
It is the AA line sectional view.
【図２】図１の要部の拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.
【図３】図１の半導体装置を実装した状態での試験方法
を説明するための図である。FIG. 3 is a diagram for explaining a test method in a state where the semiconductor device of FIG. 1 is mounted.
【図４】従来の半導体装置の一例の断面図である。FIG. 4 is a cross-sectional view of an example of a conventional semiconductor device.
【図５】従来の半導体装置を実装した状態での試験方法
を説明するための図である。FIG. 5 is a diagram for explaining a test method in a state where a conventional semiconductor device is mounted.
１ ＢＧＡ型半導体装置 ２ 基板 ３，５ 配線 ４ 検査パッド ６ 外部接続パッド ７ 半田バンプ ８ スルーホール ９ ＩＣチップ １１ モールド樹脂 １２，１３ ソルダレジスト ２１ プリント基板 ２２ プローブ DESCRIPTION OF SYMBOLS 1 BGA type semiconductor device 2 Substrate 3, 5 wiring 4 Inspection pad 6 External connection pad 7 Solder bump 8 Through hole 9 IC chip 11 Mold resin 12, 13 Solder resist 21 Printed board 22 Probe
Claims (4)
前記基板の裏面に前記ＩＣチップに電気接続される複数
個の外部電極パッドが配列形成されているＢＧＡ型半導
体装置において、前記基板の表面に前記ＩＣチップに電
気接続される検査パッドが配設され、この検査パッドに
対してテスト用のプローブが接触可能に構成されている
ことを特徴とする検査パッド付きＢＧＡ型半導体装置。An IC chip is mounted on a surface of a substrate,
In a BGA type semiconductor device in which a plurality of external electrode pads electrically connected to the IC chip are arranged and formed on the back surface of the substrate, test pads electrically connected to the IC chip are provided on the surface of the substrate. A BGA type semiconductor device with a test pad, wherein a test probe can be brought into contact with the test pad.
た配線と、前記各配線を相互に電気接続するために前記
基板に設けられたスルーホールと、前記基板の表面に搭
載されたＩＣチップと、前記ＩＣチップを前記基板表面
の配線に電気接続する手段と、前記基板裏面の配線によ
って格子状に配列形成された外部電極パッドと、前記基
板表面の配線の一部で構成される検査パッドとを備える
ことを特徴とする検査パッド付きＢＧＡ型半導体装置。2. A wiring formed on each of a front surface and a back surface of a substrate, a through hole provided in the substrate for electrically connecting the wirings to each other, and an IC chip mounted on the surface of the substrate. Means for electrically connecting the IC chip to the wiring on the surface of the substrate, external electrode pads arranged in a grid pattern by the wiring on the rear surface of the substrate, and an inspection pad comprising a part of the wiring on the surface of the substrate A BGA type semiconductor device with a test pad, comprising:
によって被覆され、この被覆が除去された箇所において
前記各配線が露呈され、この露呈された配線部分によっ
て前記外部電極パッドと検査パッドが形成される請求項
２に記載の検査パッド付きＢＧＡ型半導体装置。3. The wiring on the front surface and the back surface of the substrate is covered with an insulating film, and each wiring is exposed at a location where the coating is removed, and the external electrode pad and the inspection pad are formed by the exposed wiring portion. The BGA type semiconductor device with a test pad according to claim 2 formed.
辺領域に配列形成され、かつ前記外部電極パッドと同じ
格子状に配列形成されている請求項３に記載の検査パッ
ド付きＢＧＡ型半導体装置。4. The BGA type semiconductor device with test pads according to claim 3, wherein the test pads are arranged in a peripheral region on the surface of the substrate and are arranged in the same grid as the external electrode pads. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9169771A JPH1117057A (en) | 1997-06-26 | 1997-06-26 | Bga type semiconductor device with inspection pads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9169771A JPH1117057A (en) | 1997-06-26 | 1997-06-26 | Bga type semiconductor device with inspection pads |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117057A true JPH1117057A (en) | 1999-01-22 |
Family
ID=15892564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9169771A Pending JPH1117057A (en) | 1997-06-26 | 1997-06-26 | Bga type semiconductor device with inspection pads |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117057A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008164623A (en) * | 2008-01-25 | 2008-07-17 | Elpida Memory Inc | Semiconductor device |
| JP2008251608A (en) * | 2007-03-29 | 2008-10-16 | Casio Comput Co Ltd | Semiconductor device and manufacturing process of the same |
| JP2016514367A (en) * | 2013-03-01 | 2016-05-19 | クアルコム，インコーポレイテッド | Package substrate with test pads on fine pitch trace |
-
1997
- 1997-06-26 JP JP9169771A patent/JPH1117057A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008251608A (en) * | 2007-03-29 | 2008-10-16 | Casio Comput Co Ltd | Semiconductor device and manufacturing process of the same |
| US7932517B2 (en) | 2007-03-29 | 2011-04-26 | Casio Computer Co., Ltd. | Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof |
| JP2008164623A (en) * | 2008-01-25 | 2008-07-17 | Elpida Memory Inc | Semiconductor device |
| JP2016514367A (en) * | 2013-03-01 | 2016-05-19 | クアルコム，インコーポレイテッド | Package substrate with test pads on fine pitch trace |
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