JP3895465B2 - Board mounting method, board mounting structure - Google Patents

Board mounting method, board mounting structure Download PDF

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Publication number
JP3895465B2
JP3895465B2 JP13243798A JP13243798A JP3895465B2 JP 3895465 B2 JP3895465 B2 JP 3895465B2 JP 13243798 A JP13243798 A JP 13243798A JP 13243798 A JP13243798 A JP 13243798A JP 3895465 B2 JP3895465 B2 JP 3895465B2
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Prior art keywords
substrate
mounting
protruding
semiconductor device
solder
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JPH11330690A (en
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康文 内田
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

【０００１】
【発明の属する技術分野】
本発明は、基板の実装方法、基板の実装構造に関するものである。
【０００２】
【従来の技術】
図１２及び図１３に示すように、従来のＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒｅｙ）構造の半導体装置４０は、基板表面から基板裏面にわたって設けられた複数の配線１９（図１４参照）を有する基板１４と、個々の配線１９（図１４参照）と基板表面側で金線１８などにより電気的に接続された半導体素子１６と、半導体素子１６と金線１８及び金線１８の接続箇所などを外部環境から保護する樹脂などにより形成されたパッケージ１３と、基板１４の裏面側に基板１４の四辺に沿ってアレイ状に設けられ基板裏面側の配線１９（図１４参照）と電気的に接続する複数の半田ボール１２とから構成されている。
【０００３】
図１４に示すように、配線１９は、基板１４の主材である樹脂材１５に形成されたスルーホール２２内とこのスルーホール２２内の配線と接続するように基板表面にパタンニングされた金などの導電性材料により構成され、基板表面側の金線１８との接合箇所と基板裏面側の半田ボール１２との接触領域以外の部分はソルダレジスト１７により被覆されている。
【０００４】
また、上述したような構成の半導体装置４０が実装される実装基板６０には、図１５に示すように、半田ボール１２と対応する箇所に夫々半田ボール用電極パッド３２が設けられ、個々の半田ボール用電極パッド３２には他の電子部品と電気的に接続するための配線３６がそれぞれ形成されている。
【０００５】
半導体装置４０の実装基板６０への実装は、実装基板３０の半田ボール用電極パッド３２上に半導体装置４０の半田ボール１２が載置されるように半導体装置４０を位置合わせして実装基板６０上に搭載した後、リフロー処理することにより半田ボール１２を溶融して行われている。
【０００６】
【発明が解決しようとする課題】
しかしながら、上述したようなＢＧＡ構造の半導体装置において、基板の裏面側に設けられた複数の半田ボールの基板裏面からの高さにはバラツキがある。そのため、実装基板上に半導体装置を載置したときに半導体基板が斜めになったり、一部の半田ボールと電極パッドとが精度よく接続されずに接続不良となってしまう。
【０００７】
また、すべての半田ボールを全く同じ高さにすることは難しく、基板裏面からの高さのバラツキを無くすことはできないので、得られた製品全部に対し良好に接続されているかどうかの検査を行わなければならず、手間がかかるという難点がある。
【０００８】
さらに、半田ボールの接続状態を確認する際に、接続箇所が隠れてしまうために半田ボールと電極パッドとが良好に接続しているかどうかを検査するのは困難である。特に、半導体装置の中央に近い位置の半田ボールは側面側から確認するのが難しく、殆ど確認できないという問題がある。そのため、接続不良箇所が存在しても見過ごしてしまう恐れが大きく、不良品を出荷してしまうという問題がある。
【０００９】
また、半導体装置や実装基板に形成する配線はそれぞれ他の半田ボールや電極パッド等と接触しないように設けなければならず、また、半田ボールや電極パッド自体の寸法の縮小にも限界があるため、配線密度向上及び実装の高密度化の妨げとなっている。
【００１０】
以上のことから本発明は、例えば、半導体装置の基板と実装基板、プリント配線基板とプリント配線基板などのように、平行に配置された二つの基板の複数の端子同士をすべて確実に接続できる基板の実装方法を提供することを第１の目的とする。また、半導体装置を実装基板に精度よく接続できる基板の実装方法を提供することを第２の目的とする。
【００１１】
さらに、例えば、半導体装置の基板と実装基板、プリント配線基板とプリント配線基板などのように、平行に配置された二つの基板の端子同士の接続が確実な実装構造を提供することを第３の目的とする。
【００１２】
また、実装基板に対する接続精度が高い半導体装置を提供することを第４の目的とする。
【００１３】
【課題を解決するための手段】
上記第１の目的を達成するために、請求項１の発明の基板の実装方法は、一方の基板及び他方の基板を、前記一方の基板と前記他方の基板とを電気的に接続する弾性を備えた突状端子及び前記一方の基板と前記他方の基板とを電気的に接続する半田バンプを挟んで配置し、前記突状端子が撓むように前記突状端子に前記一方の基板及び前記他方の基板を接触させ、前記半田バンプを溶融することにより前記一方の基板と前記他方の基板とを前記突状端子が撓んだ状態で固定することを特徴としている。
また、請求項２の発明の基板の実装方法は、二つの基板を電気的に接続する弾性を備えた突状端子及び前記二つの基板を電気的に接続する半田バンプが設けられた一方の基板と、電極パッドが設けられた他方の基板とを用い、前記突状端子と前記電極パッドとを接触させて前記突状端子を撓ませ、前記突状端子を撓ませた状態で前記半田バンプを溶融して前記一方の基板と前記他方の基板とを固定することを特徴としている。
さらに、請求項３の発明の基板の実装方法は、二つの基板を電気的に接続する弾性を備えた突状端子及び前記二つの基板を電気的に接続する半田バンプの一方及び電極パッドが設けられた一方の基板と、前記突状端子及び前記半田バンプの他方及び電極パッドが設けられた他方の基板とを用い、前記突状端子と前記突状端子が設けられていない方の基板に設けられた前記電極パッドとを接触させて前記突状端子を撓ませ、前記突状端子を撓ませた状態で前記半田バンプを溶融して前記一方の基板と前記他方の基板とを固定することを二つの基板を電気的に接続する弾性を備えた突状端子及び前記二つの基板を電気的に接続する半田バンプの何れか一方並びに電極パッドが設けられた一方の基板と、前記突状端子及び前記半田バンプの他方並びに電極パッドが設けられた他方の基板とを用い、前記突状端子と前記突状端子が設けられていない方の基板に設けられた前記電極パッドとを接触させて前記突状端子を撓ませ、前記突状端子を撓ませた状態で前記半田バンプを溶融して前記一方の基板と前記他方の基板とを固定することを特徴としている。
【００１４】
すなわち、基板と基板とを電気的に接続する端子として弾性の突状端子を用いているため、基板と基板とを電気的に接続してその状態で固定する際に、他の突状端子よりも高さの高い突状端子はその分だけ余分に撓んで他の突状端子の高さと同じ高さとなるので、突状端子の基板表面からの高さが全て同じでなくとも全ての突状端子を確実に接続できる。したがって、二つの基板の複数の端子同士をすべて確実に接続することが可能である。
【００１６】
また、二つの基板を半田により固定するため、固定のための特別な設備が不要である。また半田端子の位置を確認しやすい位置とすれば、半田の接続状態を容易に確認できる。
さらに、請求項４の発明は、請求項１〜３のいずれかに記載の基板の実装方法において、前記半田バンプはリフローすることにより溶融することを特徴としている。
【００２０】
上記第２の目的を達成するために、請求項５の発明は、請求項１〜４のいずれかに記載の基板の実装方法において、前記一方の基板及び前記他方の基板のいずれかの基板は半導体装置の基板であることを特徴としている。これにより、半導体装置を高い精度で基板に実装できるので接続不良に起因する不良品の発生を抑えることができる。
【００２１】
さらに、上記第３の目的を達成するために、請求項６の発明の基板の実装構造は、所定距離離間して配置された一方の基板及び他方の基板と、前記一方の基板と前記他方の基板との基板間に形成され前記一方の基板と前記他方の基板とを電気的に接続する弾性を備えた突状端子、及び前記一方の基板と前記他方の基板との基板間に形成され前記一方の基板と前記他方の基板とを電気的に接続する半田バンプとを有し、前記突状端子は撓んだ状態で前記一方の基板及び前記他方の基板と接触し、前記半田バンプにより、前記一方の基板と前記他方の基板とは固定されている。
また、請求項７の発明の基板の実装構造は、略平行に配置された二つの基板の一方の基板に固定され、前記二つの基板を電気的に接続し、かつ、弾性を備えた複数の突状端子と、前記突状端子が他方の基板の端子に接触し、かつ、撓んだ状態で前記一方の基板と前記他方の基板とを固定するとともに、前記二つの基板を電気的に接続する半田バンプと、を備えている。
【００２３】
請求項６又は請求項７の発明における半田バンプは、基板と基板とを固定するために特別な設備が不要であるので、製造設備にかかるコストを抑えられるという利点がある。
また、請求項８の発明は、請求項６又は請求項７に記載の基板の実装構造において、前記半田バンプと前記突状端子とはアレイ状に配置されていることを特徴としている。
さらに請求項９の発明は、請求項８記載の基板の実装構造において、前記突状端子は前記半田バンプよりも内側の領域に設けられていることを特徴としている。
すなわち、接合状態の検査をしにくい位置の端子を突状端子とし接合状態の検査をしやすい位置に半田バンプを配置する構成としているため、接合状態の検査の際に、接続不良箇所を見過ごす恐れが少なく、不良品を出荷してしまうことを極力避けることができる。
【００２４】
上記第４の目的を達成するために、請求項１０の発明は、請求項６〜９のいずれかに記載の基板の実装構造において、前記一方の基板及び前記他方の基板のいずれかの基板は半導体装置の基板であることを特徴としている。これにより、半導体装置を搭載した製品に半導体装置の実装に起因する接続不良を低減できる。
【００２９】
【発明の実施の形態】
以下、本発明の実施の形態を図１〜図１１を参照して説明する。
【００３０】
（第１の実施形態）
図１〜図６を参照して第１の実施形態を説明する。まず、図１及び図２に示すように、第１の実施形態では半導体装置の外部端子として突状端子であるバッドリード１０を設けている。この半導体装置２０は、表面から裏面に繋がる各々独立した複数の配線１９（図３参照）が設けられた基板１４と、基板１４に設けられたダイパッド上に接着剤２５（図３参照）により固定され、かつ、図示しない自身の電極部が金線１８により基板１４の個々の配線１９（図３参照）に各々ボンディングされた半導体素子１６と、半導体素子１６と金線１８とを外部環境から保護する樹脂などにより形成されたパッケージ１３と、基板１４の配線１９（図３参照）と基板１４の裏面側で接続する第１の外部端子である半田ボール１２と、基板１４の配線と基板の裏面側で接続する第２の外部端子であるバッドリード１０と、を備えている。
【００３１】
半田ボール１２とバッドリード１０は、図２に示すように、半導体装置２０の基板の裏面側にアレイ状に配置されている。半田ボール１２は最外周のみに設けられており、半導体装置２０と実装基板３０とを電気的に接続すると共に、半導体装置２０を実装基板３０（図５及び図６参照）に固定する固定手段として働く。バッドリード１０は、半田ボールよりも内側の領域に設けられており、図４に示すように、先端部分が互い違いに開いた電気伝導率のよい金属より成る板状部材から構成され、半導体装置２０と実装基板３０（図５及び図６参照）とを電気的に接続する。
【００３２】
図３に示すように、バッドリード１０は、基板１４に設けられたバッドリード固定穴１４ａに挿入されて半導体装置２０に固定されている。バッドリード固定穴１４ａは、基板１４の表面層のソルダレジスト１７とソルダレジスト１７の下層の配線１９とを貫通して基板１４の主材である樹脂材１５にまで達する深さに形成されている。したがって、バッドリード固定穴１４ａにバッドリード１０が挿入されると、バッドリード１０の側部が配線１９と接触するのでバッドリード１０と配線１９とが電気的に接続されることとなる。
【００３３】
また、バッドリード１０がバッドリード固定穴１４ａに挿入されたときの基板表面からの高さｋは、前述した半田ボール１２の基板表面からの高さｈよりも若干高くされている。また、バッドリード１０は、半田ボール１２よりも占める空間が小さいため、外部端子として半田ボール１２を配置する場合よりも多く配置できる。したがって、従来よりも多数の配線を設けることができ、高密度配線が可能である。
【００３４】
基板１４に設けられた配線１９は、基板１４の主材である樹脂材１５に形成されたスルーホール２２内に埋め込まれた金や銅などの導電性材料と、スルーホール２２内の導電性材料と接続するように基板１４の表面及び裏面にパタンニングされた金や銅などの導電性材料とにより構成され、基板表面側の金線１８とのボンディング箇所以外は全てソルダレジスト１７により被覆されている。
【００３５】
図５に示すように、第１の実施形態における実装基板３０には、半田ボール１２と接続する領域には従来と同様な円形状の半田ボール用電極パッド３２が設けられており、バッドリード１０と接続する領域にはバッドリード１０の先端部が完全に開いたときよりも若干大きい寸法の矩形状のバッドリード用電極パッド３４が設けられている。バッドリード用電極パッド３４は、半田ボール用電極パッド３２よりも寸法がかなり小さいため、配線３６の間隔ｊを従来よりも狭めて高密度配線を実現することが可能である。
【００３６】
上記構成の半導体装置２０を上記構成の実装基板３０に実装する方法を、図６を参照して以下に説明する。
【００３７】
まず、図６（ａ）に示すように、半導体装置２０の半田ボール１２が実装基板３０に設けられた半田ボール用電極パッド３２の上方位置に配置されると共に、半導体装置２０のバッドリード１０が実装基板３０に設けられたバッドリード用電極パッド３４の上方位置に配置されるように位置合わせする。
【００３８】
次に、半導体装置２０を降下させて実装基板３０上に載置する。このとき、図６（ｂ）に示すように、半導体装置２０はバッドリード用電極パッド３４と接触した第２の外部端子であるバッドリード１０により支持され、第１の外部端子である半田ボール１２は半田ボール用電極パッド３２に接触せずに宙に浮いた状態となっている。
【００３９】
さらに、図６（ｃ）に示すように、半田ボール１２と半田ボール用電極パッド３２とが接触するまで実装基板３０上に載置した半導体装置２０上に平板状の重り５０を置き均一な負荷を与える。このとき、バッドリード１０はバッドリード用電極パッド３４に押しつけられるため、先端が撓んで基板表面からの高さｋ（図３参照）が半田ボール１２の基板表面からの高さｈ（図３参照）と同じとなる。したがって、バッドリード１０の基板表面からの高さｋに多少のバラツキがあっても全てのバッドリード１０が実装基板のバッドリード用電極パッド３４に押しつけられて半田ボール１２の基板表面からの高さｈと同じとなるまで先端が撓むため、全てのバッドリード１０が確実にバッドリード用電極パッド３４と接触することとなる。
【００４０】
半田ボール１２と半田ボール用電極パッド３２とが接触するまで実装基板３０上に載置した半導体装置２０に対して均一な負荷を与えた状態でリフロー処理を施す。これにより、図６（ｄ）に示すように、半田ボール１２は溶融して半田ボール用電極パッド３２に接合し、半導体装置２０を実装基板３０上に固定する。このとき、バッドリード１０は実装基板３０のバッドリード用電極パッド３４に先端が撓んで接触した状態で固定される。したがって、半導体装置２０の全ての外部端子１０，１２と実装基板３０の電極３２，３４との電気的接続を確実に行える。
【００４１】
（第２の実施形態）
図７〜図１０を参照して第２の実施形態を説明する。まず、図７（ａ）及び図７（ｂ）に示すように、第２の実施形態では、実装基板３１の電極として平板状のパッドからなる半田ボール用電極パッド３２とバッドリード１０とを設ける構成としている。
【００４２】
半田ボール用電極パッド３２とバッドリード１０とは、実装基板３１の表面側にアレイ状に配置されている。半田ボール用電極パッド３２は最外周のみに設けられている。バッドリード１０は、半田ボールよりも内側の領域に設けられており、上述の第１の実施形態の図４において説明したように、先端部分が互い違いに開いた電気伝導率のよい金属より成る板状部材から構成され、半導体装置２０と実装基板３０（図１０参照）とを電気的に接続する。
【００４３】
図７（ｂ）に示すように、バッドリード１０は、実装基板３１に設けられたバッドリード固定穴３１ａに挿入されて実装基板３１に固定されている。バッドリード固定穴３１ａは、実装基板３１の表面の配線３６と電気的に接続されているため、バッドリード固定穴３１ａに挿入されたバッドリード１０は実装基板３１の配線３６と電気的に接続されることとなる。
【００４４】
また、バッドリード１０がバッドリード固定穴３１ａに挿入されたときの実装基板表面からの高さｋは、後述する半田ボール１２の半導体装置２１の基板表面からの高さｈよりも若干高くされている。また、バッドリード１０は、半田ボール用電極パッド３２よりも占める空間が小さいため、配線３６の電極として半田ボール用電極パッド３２を配置する場合よりも多く配置できる。したがって、従来よりも多数の配線３６を設けることができ、実装基板３１の配線３６の高密度化が可能である。
【００４５】
第２の実施形態における半導体装置２１は、図８及び図９に示すように、外部端子としてアレイ状に配置された半田ボール１２とバッドリード用電極パッド３４とを備えている。半田ボール１２は最外周のみに設けられており、半導体装置２１と実装基板３１とを電気的に接続すると共に、半導体装置２１を実装基板３１（図７参照）に固定する固定手段として働く。バッドリード用電極パッド３４は、半田ボール１２の内側位置の前述した実装基板３１に設けられたバッドリード１０と対応する位置に設けられ、半導体装置２１と実装基板３１とを電気的に接続する。なお、その他の構成は上述した第１の実施例と同様であるので同じ符号を付して説明を省略する。
【００４６】
上記構成の実装基板３１に上記構成の半導体装置２１を実装する方法を、図１０を参照して以下に説明する。
【００４７】
まず、図１０（ａ）に示すように、半導体装置２１の半田ボール１２が実装基板３１に設けられた半田ボール用電極パッド３２の上方位置に配置されると共に、実装基板３１のバッドリード１０が半導体装置２１に設けられたバッドリード用電極パッド３４の上方位置に配置されるように位置合わせする。
【００４８】
次に、半導体装置２１を降下させて実装基板３１上に載置する。このとき、図１０（ｂ）に示すように、半導体装置２１は実装基板３１に設けられたバッドリード１０により支持され、半田ボール１２は実装基板３１の半田ボール用電極パッド３２に接触せずに宙に浮いた状態となっている。
【００４９】
さらに、図１０（ｃ）に示すように、半田ボール１２と半田ボール用電極パッド３２とが接触するまで実装基板３１上に載置した半導体装置２１上に平板状の重り５０を置き均一な負荷を与える。このとき、バッドリード１０はバッドリード用電極パッド３４に押しつけられるため、先端が撓んで基板表面からの高さｋ（図７参照）が半田ボール１２の基板表面からの高さｈ（図８参照）と同じとなる。したがって、バッドリード１０の基板表面からの高さｋに多少のバラツキがあっても全てのバッドリード１０が実装基板のバッドリード用電極パッド３４に押しつけられて半田ボール１２の基板表面からの高さｈと同じとなるまで先端が撓むため、全てのバッドリード１０が確実にバッドリード用電極パッド３４と接触することとなる。
【００５０】
半田ボール１２と半田ボール用電極パッド３２とが接触するまで実装基板３１上に載置した半導体装置２１に対して均一な負荷を与えた状態でリフロー処理を施す。これにより、図１０（ｄ）に示すように、半田ボール１２は溶融して半田ボール用電極パッド３２に接合し、半導体装置２０を実装基板３１上に固定する。このとき、バッドリード１０は半導体装置２１のバッドリード用電極パッド３４に先端が撓んで接触した状態で固定される。
【００５１】
したがって、半導体装置２１の全ての半田ボール１２とバッドリード用電極パッド３４とを、実装基板３１の半田ボール用電極パッド３２とバッドリード１０との電気的接続を確実に行える。
【００５２】
また、以上説明した第１の実施形態と第２の実施形態では、接合状態の検査をしにくい位置の外部端子を全てバッドリード１０とし接合状態の検査をしやすい位置に半田ボールを設ける構成としているため、接合状態の検査の際に、接続不良箇所を見過ごす恐れが少なく、不良品を出荷してしまうことを極力避けることができる。
【００５３】
なお、以上説明した第１の実施形態と第２の実施形態では、半田ボールを最外周全てに設ける場合を挙げたが、最外周全てに半田ボールを設ける必要はなく、半導体装置が実装基板に固定される最低限の数の半田ボールを最外周に部分的に設けるようにすることもできる。
【００７１】
上記第１の実施形態から第２の実施形態において、突状端子として先端に弾性を有するバッドリード１０を先端部分が互い違いに開いた電気伝導率のよい金属より成る板状部材形状より構成しているが、本発明ではこの様な構成に限らず、例えば、図１１（ａ）や図１１（ｂ）に示した構成とすることもできる。
【００７２】
さらに、上記第１の実施形態から第２の実施形態において突状端子として挙げたバッドリード１０は、先端のみに弾性を有する構成であるが、例えば、導電性材料からなるバネ部材などのように、突状端子全体に弾性を有する構成としてもよい。
【００７３】
また、上記第１の実施形態から第２の実施形態においては、半導体装置を実装基板に載置した後に重りによって半導体装置に負荷を与えてバッドリード１０の撓みを確実にしているが、半導体装置がバッドリード１０を充分に撓ませる重量を備えている場合は、重りによる負荷を与えなくてもよい。
【００７４】
なお、上記第１の実施形態から第２の実施形態において、バッドリード１０の表面や、バッドリード用電極３４の表面に自然酸化膜などが形成されていても、半導体装置を実装するときにバッドリード１０の先端がバッドリード用電極３４に押圧されて撓み表面の自然酸化膜をこすりとるので導通性を向上できるという利点もある。
【００７５】
なお、上記第１の実施形態から第２の実施形態では、半導体装置を実装基板に実装する場合を挙げたが、半導体装置や他の電子部品などが実装された実装基板をプリント配線板など他の基板に接続する場合にも本発明を適用することができる。
【００７６】
【発明の効果】
以上説明したように、請求項１〜４の発明によれば、平行に配置された二つの基板の複数の端子同士をすべて確実に接続できる、という効果を達成する。また、請求項５の発明によれば、半導体装置を基板に精度よく接続できる、という効果を達成する。
【００７７】
さらに、請求項６〜７の発明によれば、平行に配置された二つの基板の端子同士の接続が確実な実装構造を提供できる、という効果を達成する。また、請求項８〜９の発明によれば、接合状態の検査をしにくい位置の端子を突状端子とし接合状態の検査をしやすい位置に半田バンプを配置する構成としているため、接合状態の検査の際に、接続不良箇所を見過ごす恐れが少なく、不良品を出荷してしまうことを極力避けることができる。また、請求項１０の発明によれば、基板に精度よく接続された半導体装置の実装構造を提供できる、という効果を達成する。
【図面の簡単な説明】
【図１】 本発明の第１の実施形態における半導体装置の概略を示す横断面図である。
【図２】 本発明の第１の実施形態における半導体装置の概略を示す下面図である。
【図３】 図１で示した半導体装置の概略構造を示す部分断面図である。
【図４】 第１の実施形態の半導体装置に設けたバッドリードの概略構成を示す斜視図である。
【図５】 本発明の第１の実施形態における実装基板の概略を示す部分上面図である。
【図６】 図１に示した半導体装置を図５に示した実装基板に実装方法を示す工程図である。
【図７】 （ａ）は、本発明の第２の実施形態における実装基板の概略を示す部分上面図であり、（ｂ）は、図７（ａ）におけるＡ−Ａ線図である。
【図８】 本発明の第２の実施形態における半導体装置の概略構造を示す部分断面図である。
【図９】 本発明の第２の実施形態における半導体装置の概略を示す下面図である。
【図１０】 図８に示した半導体装置を図７に示した実装基板に実装方法を示す工程図である。
【図１１】 （ａ）は、バッドリード１０の第２の構成例を示す斜視図であり、（ｂ）は、バッドリード１０の第３の構成例を示す斜視図である。
【図１２】 従来の半導体装置の概略を示す横断面図である。
【図１３】 従来の半導体装置の概略を示す下面図である。
【図１４】 図１２で示した従来の半導体装置の概略構造を示す部分断面図である。
【図１５】 従来の実装基板の概略を示す部分上面図である。
【符号の説明】
１０ バッドリード
１２ 半田ボール
１３ パッケージ
１４ 基板
１４ａ バッドリード固定穴
１５ 樹脂材
１６ 半導体素子
１７ ソルダレジスト
１８ 金線
１９，３６ 配線
２０ 半導体装置
２２ スルーホール
２５ 接着剤
３０ 実装基板
３２ 半田ボール用電極パッド
３４ バッドリード用電極パッド[0001]
BACKGROUND OF THE INVENTION
The present invention is implementation of the substrate, those related to the implementation structure of the substrate.
[0002]
[Prior art]
As shown in FIG. 12 and a beauty 13, a conventional BGA (Ball Grid Arrey) semiconductor device 40 of the structure includes a substrate 14 having a plurality of wirings 19 formed over the back surface of the substrate from the substrate surface (FIG. 14 see) , the individual wires 19 (FIG. 14 see) and the semiconductor element 16 is electrically connected by such as a gold wire or the like 18 at the substrate surface side and the external environment connection points of the semiconductor element 16 and the gold wire 18 and the gold wire 18 multiple package 13 formed by a resin to protect, for electrically connecting the substrate rear surface side of the wiring 19 is provided in an array on the back side along the four sides of the substrate 14 of the substrate 14 (FIG. 14 see) from And solder balls 12.
[0003]
As shown in FIG. 14 , the wiring 19 is a gold patterned on the surface of the substrate so as to be connected to the inside of the through hole 22 formed in the resin material 15 which is the main material of the substrate 14 and the wiring in the through hole 22. A portion other than the contact area between the bonding point with the gold wire 18 on the substrate surface side and the solder ball 12 on the back surface side of the substrate is covered with a solder resist 17.
[0004]
Further, as shown in FIG. 15, solder ball electrode pads 32 are provided at locations corresponding to the solder balls 12 on the mounting substrate 60 on which the semiconductor device 40 having the above-described configuration is mounted . The ball electrode pads 32 are respectively formed with wirings 36 for electrical connection with other electronic components.
[0005]
The semiconductor device 40 is mounted on the mounting substrate 60 by positioning the semiconductor device 40 so that the solder balls 12 of the semiconductor device 40 are placed on the solder ball electrode pads 32 of the mounting substrate 30. After mounting, the solder balls 12 are melted by a reflow process.
[0006]
[Problems to be solved by the invention]
However, in the semiconductor device having the BGA structure as described above, the height of the plurality of solder balls provided on the back surface side of the substrate from the back surface of the substrate varies. For this reason, when the semiconductor device is placed on the mounting substrate, the semiconductor substrate is inclined or some solder balls and the electrode pads are not accurately connected, resulting in poor connection.
[0007]
In addition, it is difficult to make all the solder balls exactly the same height, and it is impossible to eliminate the variation in height from the back of the board, so check whether all the obtained products are connected well. There is a drawback that it takes time and effort.
[0008]
Further, when the connection state of the solder ball is confirmed, the connection portion is hidden, so it is difficult to inspect whether the solder ball and the electrode pad are well connected. In particular, it is difficult to confirm the solder ball at a position close to the center of the semiconductor device from the side surface side, and there is a problem that it cannot be almost confirmed. For this reason, there is a high risk of overlooking even if there is a connection failure location, and there is a problem that defective products are shipped.
[0009]
In addition, the wiring formed on the semiconductor device and the mounting substrate must be provided so as not to come into contact with other solder balls, electrode pads, etc., and there is a limit to reducing the size of the solder balls or electrode pads themselves. This hinders improvement in wiring density and density of mounting.
[0010]
From the above, the present invention is a substrate that can securely connect all the terminals of two substrates arranged in parallel, such as a substrate and mounting substrate of a semiconductor device, a printed wiring substrate and a printed wiring substrate, etc. The first object is to provide a mounting method. It is a second object of the present invention to provide a substrate mounting method capable of accurately connecting a semiconductor device to a mounting substrate.
[0011]
Furthermore, for example, it is a third object of the present invention to provide a mounting structure in which the terminals of two substrates arranged in parallel such as a substrate and a mounting substrate of a semiconductor device and a printed wiring substrate and a printed wiring substrate are securely connected. Objective.
[0012]
A fourth object is to provide a semiconductor device with high connection accuracy to a mounting substrate .
[0013]
[Means for Solving the Problems]
In order to achieve the first object, the substrate mounting method of the invention of claim 1 is characterized in that the elasticity of electrically connecting the one substrate and the other substrate to the one substrate and the other substrate is provided. The protruding terminals provided and the solder bumps for electrically connecting the one substrate and the other substrate are disposed between the one substrate and the other substrate so that the protruding terminals are bent. The substrate is brought into contact and the solder bumps are melted to fix the one substrate and the other substrate in a state where the protruding terminals are bent.
According to a second aspect of the present invention, there is provided a substrate mounting method comprising: one substrate provided with a protruding terminal having elasticity for electrically connecting two substrates; and a solder bump for electrically connecting the two substrates. And the other substrate provided with an electrode pad, the protruding terminal and the electrode pad are brought into contact with each other to bend the protruding terminal, and the solder bump is bent in a state where the protruding terminal is bent. The one substrate and the other substrate are fixed by melting.
Further, the substrate mounting method of the invention of claim 3 is provided with a protruding terminal having elasticity for electrically connecting two substrates, one of solder bumps for electrically connecting the two substrates, and an electrode pad. One of the projected terminals, the other of the protruding terminals and the solder bumps, and the other substrate provided with the electrode pads, and provided on the substrate on which the protruding terminals and the protruding terminals are not provided. Bending the protruding terminals by contacting the electrode pads formed, and melting the solder bumps in a state where the protruding terminals are bent to fix the one substrate and the other substrate; and one substrate either has one and electrodes pads provided in the solder bumps to electrically connect the protruding terminal and the two substrates having a resilient electrically connecting the two substrates, the protruding terminals and the other hand the arrangement of the solder bump Electrodes pads with the other substrate provided causes the protruding terminal and the projecting of the terminals brought into contact with the electrode pads provided on the substrate of which is not provided deflect the projecting terminal The solder bumps are melted in a state where the protruding terminals are bent, and the one substrate and the other substrate are fixed.
[0014]
In other words, since an elastic protruding terminal is used as a terminal for electrically connecting the board and the board, when the board and the board are electrically connected and fixed in that state, the other protruding terminals Since the protruding terminals with a high height bend to the same extent as the other protruding terminals, the protruding terminals have all the protruding shapes even if the protruding terminals are not all the same height from the substrate surface. The terminal can be connected securely. Therefore, it is possible to reliably connect all the terminals of the two substrates.
[0016]
Moreover, since the two substrates are fixed by soldering, no special equipment for fixing is required. If the position of the solder terminal is easy to check, the solder connection state can be easily checked.
Furthermore, a fourth aspect of the invention is characterized in that, in the substrate mounting method according to any one of the first to third aspects, the solder bumps are melted by reflowing.
[0020]
In order to achieve the second object, the invention according to claim 5 is the substrate mounting method according to any one of claims 1 to 4, wherein any one of the one substrate and the other substrate is It is characterized by being a substrate of a semiconductor device. Thus, it is possible to suppress the occurrence of defective products due to poor connection because it mounted on board a semiconductor device with high accuracy.
[0021]
Furthermore, in order to achieve the third object, the substrate mounting structure of the invention of claim 6 includes one substrate and the other substrate that are spaced apart by a predetermined distance, the one substrate, and the other substrate. A protruding terminal formed between the substrates and having elasticity to electrically connect the one substrate and the other substrate, and between the one substrate and the other substrate; Solder bumps that electrically connect one substrate and the other substrate, the protruding terminal is in contact with the one substrate and the other substrate in a bent state, by the solder bump, The one substrate and the other substrate are fixed.
According to a seventh aspect of the present invention, there is provided a substrate mounting structure which is fixed to one of the two substrates arranged substantially in parallel, electrically connects the two substrates, and has a plurality of elasticity. A protruding terminal, and the protruding terminal is in contact with a terminal of the other substrate and is fixed in a state where the one substrate and the other substrate are bent, and the two substrates are electrically connected. Solder bumps.
[0023]
The solder bump in the invention of claim 6 or claim 7 has an advantage that the cost for manufacturing equipment can be suppressed because no special equipment is required to fix the board to the board .
According to an eighth aspect of the present invention, in the substrate mounting structure according to the sixth or seventh aspect, the solder bumps and the protruding terminals are arranged in an array.
Further, a ninth aspect of the present invention is characterized in that, in the substrate mounting structure according to the eighth aspect, the protruding terminals are provided in a region inside the solder bump.
In other words, since the terminal at a position where it is difficult to inspect the bonding state is a protruding terminal and the solder bumps are arranged at a position where the inspection of the bonding state is easy to perform, there is a risk of overlooking a defective connection point during the inspection of the bonding state. Therefore, it is possible to avoid shipping defective products as much as possible.
[0024]
To achieve the above fourth object, the invention of claim 10, in the mounting structure of the substrate mounting serial to claim 6-9, one of the substrate of one substrate and the other substrate it is characterized in that it is a substrate of the semiconductor device. Thereby, the connection failure resulting from mounting of a semiconductor device can be reduced in the product in which the semiconductor device is mounted.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0030]
(First embodiment)
The first embodiment will be described with reference to FIGS. First, as shown in FIGS. 1 and 2, in the first embodiment, a bad lead 10 that is a protruding terminal is provided as an external terminal of the semiconductor device. The semiconductor device 20 is fixed on a substrate 14 provided with a plurality of independent wirings 19 (see FIG. 3) connected from the front surface to the back surface, and an adhesive 25 (see FIG. 3) on a die pad provided on the substrate 14. In addition, the semiconductor element 16 in which its own electrode portion (not shown) is bonded to each wiring 19 (see FIG. 3) of the substrate 14 by the gold wire 18, and the semiconductor element 16 and the gold wire 18 are protected from the external environment. A package 13 formed of resin or the like, a wiring 19 (see FIG. 3) of the substrate 14, a solder ball 12 as a first external terminal connected on the back side of the substrate 14, a wiring of the substrate 14 and the back side of the substrate And a bad lead 10 which is a second external terminal connected on the side.
[0031]
As shown in FIG. 2, the solder balls 12 and the bad leads 10 are arranged in an array on the back side of the substrate of the semiconductor device 20. The solder balls 12 are provided only on the outermost periphery, and electrically connect the semiconductor device 20 and the mounting substrate 30 as fixing means for fixing the semiconductor device 20 to the mounting substrate 30 (see FIGS. 5 and 6). work. The bad lead 10 is provided in a region on the inner side of the solder ball, and as shown in FIG. 4, is constituted by a plate-like member made of a metal having good electrical conductivity with its tip portions opened alternately, and the semiconductor device 20. Are electrically connected to the mounting board 30 (see FIGS. 5 and 6).
[0032]
As shown in FIG. 3, the bad lead 10 is inserted into a bad lead fixing hole 14 a provided in the substrate 14 and fixed to the semiconductor device 20. The bad lead fixing hole 14 a is formed to a depth that reaches the resin material 15 that is the main material of the substrate 14 through the solder resist 17 on the surface layer of the substrate 14 and the wiring 19 below the solder resist 17. . Therefore, when the bad lead 10 is inserted into the bad lead fixing hole 14a, the side portion of the bad lead 10 comes into contact with the wiring 19, so that the bad lead 10 and the wiring 19 are electrically connected.
[0033]
Further, the height k from the substrate surface when the bad lead 10 is inserted into the bad lead fixing hole 14a is slightly higher than the height h from the substrate surface of the solder ball 12 described above. Further, since the space occupied by the bad leads 10 is smaller than that of the solder balls 12, more pad leads 10 can be arranged than when the solder balls 12 are arranged as external terminals. Therefore, a larger number of wirings can be provided than before, and high-density wiring is possible.
[0034]
The wiring 19 provided on the substrate 14 includes a conductive material such as gold or copper embedded in the through hole 22 formed in the resin material 15 which is the main material of the substrate 14, and a conductive material in the through hole 22. Are formed of a conductive material such as gold or copper patterned on the front and back surfaces of the substrate 14 and are all covered with the solder resist 17 except for bonding points with the gold wires 18 on the substrate surface side. Yes.
[0035]
As shown in FIG. 5, the mounting substrate 30 in the first embodiment is provided with circular solder ball electrode pads 32 similar to the conventional one in the region connected to the solder balls 12. A rectangular lead electrode pad 34 having a slightly larger size than that when the front end portion of the bad lead 10 is completely opened is provided in the region connected to the negative lead 10. Since the bad lead electrode pad 34 is considerably smaller in size than the solder ball electrode pad 32, it is possible to realize a high density wiring by narrowing the interval j of the wiring 36 as compared with the conventional case.
[0036]
A method of mounting the semiconductor device 20 having the above configuration on the mounting substrate 30 having the above configuration will be described below with reference to FIG.
[0037]
First, as shown in FIG. 6A, the solder balls 12 of the semiconductor device 20 are disposed above the solder ball electrode pads 32 provided on the mounting substrate 30, and the bad leads 10 of the semiconductor device 20 are disposed. Positioning is performed so as to be disposed above the bad lead electrode pad 34 provided on the mounting substrate 30.
[0038]
Next, the semiconductor device 20 is lowered and placed on the mounting substrate 30. At this time, as shown in FIG. 6B, the semiconductor device 20 is supported by the bad lead 10 as the second external terminal in contact with the bad lead electrode pad 34, and the solder ball 12 as the first external terminal. Is in a state of floating in the air without contacting the solder ball electrode pad 32.
[0039]
Further, as shown in FIG. 6C, a flat weight 50 is placed on the semiconductor device 20 placed on the mounting substrate 30 until the solder balls 12 and the solder ball electrode pads 32 come into contact with each other, and a uniform load is applied. give. At this time, since the bad lead 10 is pressed against the bad lead electrode pad 34, the tip is bent and the height k from the substrate surface (see FIG. 3) is the height h from the substrate surface of the solder ball 12 (see FIG. 3). ) Is the same. Therefore, even if there is some variation in the height k of the bad lead 10 from the substrate surface, all the bad leads 10 are pressed against the bad lead electrode pads 34 of the mounting substrate, and the height of the solder balls 12 from the substrate surface. Since the tip bends until it becomes the same as h, all the bad leads 10 are surely in contact with the bad lead electrode pads 34.
[0040]
The reflow process is performed in a state where a uniform load is applied to the semiconductor device 20 placed on the mounting substrate 30 until the solder balls 12 and the solder ball electrode pads 32 come into contact with each other. As a result, as shown in FIG. 6D, the solder ball 12 is melted and joined to the solder ball electrode pad 32, and the semiconductor device 20 is fixed onto the mounting substrate 30. At this time, the bad lead 10 is fixed in a state where the tip is bent and in contact with the bad lead electrode pad 34 of the mounting substrate 30. Therefore, electrical connection between all the external terminals 10 and 12 of the semiconductor device 20 and the electrodes 32 and 34 of the mounting substrate 30 can be reliably performed.
[0041]
(Second Embodiment)
A second embodiment will be described with reference to FIGS. First, as shown in FIGS. 7A and 7B, in the second embodiment, solder ball electrode pads 32 made of flat pads and bad leads 10 are provided as electrodes of the mounting substrate 31. It is configured.
[0042]
The solder ball electrode pads 32 and the bad leads 10 are arranged in an array on the surface side of the mounting substrate 31. The solder ball electrode pads 32 are provided only on the outermost periphery. The bad lead 10 is provided in a region inside the solder ball, and as described with reference to FIG. 4 of the first embodiment described above, a plate made of a metal having good electrical conductivity with its tip portions opened alternately. The semiconductor device 20 and the mounting substrate 30 (see FIG. 10) are electrically connected.
[0043]
As shown in FIG. 7B, the bad lead 10 is inserted into a bad lead fixing hole 31 a provided in the mounting substrate 31 and fixed to the mounting substrate 31. Since the bad lead fixing hole 31a is electrically connected to the wiring 36 on the surface of the mounting substrate 31, the bad lead 10 inserted into the bad lead fixing hole 31a is electrically connected to the wiring 36 of the mounting substrate 31. The Rukoto.
[0044]
Further, the height k from the surface of the mounting substrate when the bad lead 10 is inserted into the bad lead fixing hole 31a is slightly higher than the height h of the solder ball 12 described later from the substrate surface of the semiconductor device 21. Yes. Further, since the pad leads 10 occupy a smaller space than the solder ball electrode pads 32, more pad leads 10 can be disposed than when the solder ball electrode pads 32 are disposed as the electrodes of the wiring 36. Therefore, more wirings 36 can be provided than in the prior art, and the wirings 36 on the mounting substrate 31 can be densified.
[0045]
As shown in FIGS. 8 and 9, the semiconductor device 21 according to the second embodiment includes solder balls 12 and bad lead electrode pads 34 arranged in an array as external terminals. The solder balls 12 are provided only on the outermost periphery, and serve as a fixing means for electrically connecting the semiconductor device 21 and the mounting substrate 31 and fixing the semiconductor device 21 to the mounting substrate 31 (see FIG. 7). The pad electrode 34 for bad lead is provided at a position corresponding to the bad lead 10 provided on the mounting board 31 described above inside the solder ball 12, and electrically connects the semiconductor device 21 and the mounting board 31. Since other configurations are the same as those of the first embodiment described above, the same reference numerals are given and description thereof is omitted.
[0046]
A method of mounting the semiconductor device 21 having the above configuration on the mounting substrate 31 having the above configuration will be described below with reference to FIG.
[0047]
First, as shown in FIG. 10A, the solder balls 12 of the semiconductor device 21 are disposed above the solder ball electrode pads 32 provided on the mounting substrate 31, and the bad leads 10 of the mounting substrate 31 are disposed. Positioning is performed so as to be disposed above the bad lead electrode pad 34 provided in the semiconductor device 21.
[0048]
Next, the semiconductor device 21 is lowered and placed on the mounting substrate 31. At this time, as shown in FIG. 10B, the semiconductor device 21 is supported by the bad leads 10 provided on the mounting substrate 31, and the solder balls 12 do not contact the solder ball electrode pads 32 of the mounting substrate 31. It is in a state of floating in the air.
[0049]
Further, as shown in FIG. 10C, a flat weight 50 is placed on the semiconductor device 21 placed on the mounting substrate 31 until the solder balls 12 and the solder ball electrode pads 32 come into contact with each other, and a uniform load is applied. give. At this time, since the bad lead 10 is pressed against the bad lead electrode pad 34, the tip is bent and the height k from the substrate surface (see FIG. 7) is the height h from the substrate surface of the solder ball 12 (see FIG. 8). ) Is the same. Therefore, even if there is some variation in the height k of the bad lead 10 from the substrate surface, all the bad leads 10 are pressed against the bad lead electrode pads 34 of the mounting substrate, and the height of the solder balls 12 from the substrate surface. Since the tip bends until it becomes the same as h, all the bad leads 10 are surely in contact with the bad lead electrode pads 34.
[0050]
The reflow process is performed in a state where a uniform load is applied to the semiconductor device 21 placed on the mounting substrate 31 until the solder ball 12 and the solder ball electrode pad 32 come into contact with each other. As a result, as shown in FIG. 10D, the solder ball 12 is melted and joined to the solder ball electrode pad 32, and the semiconductor device 20 is fixed onto the mounting substrate 31. At this time, the bad lead 10 is fixed in a state where the tip of the bad lead 10 is in contact with the bad lead electrode pad 34 of the semiconductor device 21.
[0051]
Therefore, all the solder balls 12 of the semiconductor device 21 and the bad lead electrode pads 34 can be reliably connected to the solder ball electrode pads 32 of the mounting substrate 31 and the bad leads 10.
[0052]
In the first and second embodiments described above, the external terminals at positions where it is difficult to inspect the bonding state are all bad leads 10 and solder balls are provided at positions where the bonding state is easily inspected. Therefore, when inspecting the bonding state, there is little risk of overlooking the connection failure portion, and it is possible to avoid shipping defective products as much as possible.
[0053]
In the first embodiment and the second embodiment described above, the solder ball is provided on the outermost periphery. However, it is not necessary to provide the solder ball on the outermost periphery, and the semiconductor device is mounted on the mounting substrate. A minimum number of fixed solder balls may be partially provided on the outermost periphery.
[0071]
In the first to second embodiments described above, the bad lead 10 having elasticity at the tip as a protruding terminal is configured by a plate-like member made of a metal having good electrical conductivity with the tip portions opened alternately. are, but in the present invention is not limited to such a configuration, for example, may be a configuration shown in FIG. 11 (a) and FIG. 11 (b).
[0072]
Furthermore, although the bad lead 10 cited as the projecting terminal in the first to second embodiments has a configuration having elasticity only at the tip, for example, a spring member made of a conductive material or the like. The entire projecting terminal may have elasticity.
[0073]
In the first embodiment to the second embodiment, the semiconductor device is mounted on the mounting substrate and then the weight is applied to the semiconductor device by the weight to ensure the bending of the bad lead 10. Is provided with a weight sufficient to bend the bad lead 10, it is not necessary to apply a load due to the weight.
[0074]
In the first to second embodiments, even when a natural oxide film or the like is formed on the surface of the bad lead 10 or the surface of the bad lead electrode 34, Since the tip of the lead 10 is pressed by the bad lead electrode 34 and the natural oxide film on the bent surface is rubbed, there is an advantage that the conductivity can be improved.
[0075]
In the first to second embodiments, the semiconductor device is mounted on the mounting board. However, the mounting board on which the semiconductor device or other electronic component is mounted may be a printed wiring board or the like. The present invention can also be applied to the case of connecting to other substrates.
[0076]
【The invention's effect】
As described above, according to the first to fourth aspects of the present invention, the effect that all of the plurality of terminals of the two boards arranged in parallel can be reliably connected is achieved. Further, according to the invention of claim 5, can be accurately connect the semiconductor device to board, to achieve the effect that.
[0077]
Furthermore, according to the inventions of claims 6 to 7 , an effect is achieved that a mounting structure in which the terminals of the two substrates arranged in parallel can be reliably connected to each other can be provided . In addition, according to the inventions of claims 8 to 9, since the terminal at a position where it is difficult to inspect the joining state is a protruding terminal, the solder bump is disposed at a position where the joining state is easily inspected. At the time of inspection, there is little fear of overlooking the connection failure portion, and it is possible to avoid the defective product from being shipped as much as possible. Further, according to the invention of claim 10 can provide a mounting structure of a semiconductor device which is precisely connected to the base plate, to achieve the effect that.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a bottom view schematically showing the semiconductor device according to the first embodiment of the present invention.
3 is a partial cross-sectional view showing a schematic structure of the semiconductor device shown in FIG. 1; FIG.
FIG. 4 is a perspective view showing a schematic configuration of a bad lead provided in the semiconductor device of the first embodiment.
FIG. 5 is a partial top view showing an outline of a mounting substrate in the first embodiment of the present invention.
6 is a process diagram showing a method of mounting the semiconductor device shown in FIG. 1 on the mounting substrate shown in FIG. 5;
7A is a partial top view showing an outline of a mounting substrate according to a second embodiment of the present invention, and FIG. 7B is an AA diagram in FIG. 7A.
FIG. 8 is a partial cross-sectional view showing a schematic structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 9 is a bottom view schematically showing a semiconductor device according to a second embodiment of the present invention.
10 is a process diagram showing a method for mounting the semiconductor device shown in FIG. 8 on the mounting substrate shown in FIG. 7;
11A is a perspective view showing a second configuration example of the bad lead 10, and FIG. 11B is a perspective view showing a third configuration example of the bad lead 10. FIG.
FIG. 12 is a cross-sectional view schematically showing a conventional semiconductor device.
FIG. 13 is a bottom view schematically showing a conventional semiconductor device.
14 is a partial cross-sectional view showing a schematic structure of the conventional semiconductor device shown in FIG . 12 ;
FIG. 15 is a partial top view schematically showing a conventional mounting board.
[Explanation of symbols]
10 Bad Lead 12 Solder Ball 13 Package 14 Substrate 14a Bad Lead Fixing Hole 15 Resin Material 16 Semiconductor Element 17 Solder Resist 18 Gold Wire 19, 36 Wiring 20 Semiconductor Device 22 Through Hole 25 Adhesive 30 Mounting Substrate 32 Solder Ball Electrode Pad 34 Bad lead electrode pad

Claims (10)

一方の基板及び他方の基板を、前記一方の基板と前記他方の基板とを電気的に接続する弾性を備えた突状端子及び前記一方の基板と前記他方の基板とを電気的に接続する半田バンプを挟んで配置し、
前記突状端子が撓むように前記突状端子に前記一方の基板及び前記他方の基板を接触させ、
前記半田バンプを溶融することにより前記一方の基板と前記他方の基板とを前記突状端子が撓んだ状態で固定することを特徴とする基板の実装方法。One substrate and the other substrate, a protruding terminal having elasticity for electrically connecting the one substrate and the other substrate, and solder for electrically connecting the one substrate and the other substrate Place it across the bump,
Bringing the one substrate and the other substrate into contact with the protruding terminal so that the protruding terminal is bent;
A method of mounting a substrate, comprising: fixing the one substrate and the other substrate in a state where the protruding terminals are bent by melting the solder bumps. 二つの基板を電気的に接続する弾性を備えた突状端子及び前記二つの基板を電気的に接続する半田バンプが設けられた一方の基板と、電極パッドが設けられた他方の基板とを用い、前記突状端子と前記電極パッドとを接触させて前記突状端子を撓ませ、
前記突状端子を撓ませた状態で前記半田バンプを溶融して前記一方の基板と前記他方の基板とを固定することを特徴とする基板の実装方法。Using a protruding terminal having elasticity for electrically connecting two substrates, one substrate provided with solder bumps for electrically connecting the two substrates, and the other substrate provided with electrode pads , The projecting terminal and the electrode pad are brought into contact with each other to bend the projecting terminal,
A method for mounting a substrate, comprising: melting the solder bump in a state where the protruding terminal is bent, and fixing the one substrate and the other substrate. 二つの基板を電気的に接続する弾性を備えた突状端子及び前記二つの基板を電気的に接続する半田バンプの何れか一方並びに電極パッドが設けられた一方の基板と、前記突状端子及び前記半田バンプの他方並びに電極パッドが設けられた他方の基板とを用い、前記突状端子と前記突状端子が設けられていない方の基板に設けられた前記電極パッドとを接触させて前記突状端子を撓ませ、
前記突状端子を撓ませた状態で前記半田バンプを溶融して前記一方の基板と前記他方の基板とを固定することを特徴とする基板の実装方法。And one substrate either has one and electrodes pads provided in the solder bumps to electrically connect the protruding terminal and the two substrates having a resilient electrically connecting the two substrates, the protruding terminals and using the other substrate other hand, as well as electrodes pads are provided in the solder bump is brought into contact with the electrode pads provided on the substrate towards said protruding terminal and the projecting terminal is not provided To bend the protruding terminal,
A method for mounting a substrate, comprising: melting the solder bump in a state where the protruding terminal is bent, and fixing the one substrate and the other substrate. 前記半田バンプはリフローすることにより溶融することを特徴とする請求項１〜３のいずれかに記載の基板の実装方法。  The method for mounting a substrate according to claim 1, wherein the solder bump is melted by reflowing. 前記一方の基板及び前記他方の基板のいずれかの基板は半導体装置の基板であることを特徴とする請求項１〜４のいずれかに記載の基板の実装方法。  The substrate mounting method according to claim 1, wherein one of the one substrate and the other substrate is a substrate of a semiconductor device. 所定距離離間して配置された一方の基板及び他方の基板と、
前記一方の基板と前記他方の基板との基板間に形成され前記一方の基板と前記他方の基板とを電気的に接続する弾性を備えた突状端子、及び前記一方の基板と前記他方の基板との基板間に形成され前記一方の基板と前記他方の基板とを電気的に接続する半田バンプとを有し、
前記突状端子は撓んだ状態で前記一方の基板及び前記他方の基板と接触し、
前記半田バンプにより、前記一方の基板と前記他方の基板とは固定されていることを特徴とする実装構造。One substrate and the other substrate that are spaced apart by a predetermined distance;
Protruding terminals formed between the one substrate and the other substrate and having elasticity to electrically connect the one substrate and the other substrate, and the one substrate and the other substrate And solder bumps formed between the substrates and electrically connecting the one substrate and the other substrate,
The protruding terminals are in contact with the one substrate and the other substrate in a bent state,
The mounting structure, wherein the one substrate and the other substrate are fixed by the solder bump. 略平行に配置された二つの基板の一方の基板に固定され、前記二つの基板を電気的に接続し、かつ、弾性を備えた複数の突状端子と、
前記突状端子が他方の基板の端子に接触し、かつ、撓んだ状態で前記一方の基板と前記他方の基板とを固定するとともに、前記二つの基板を電気的に接続する半田バンプと、
を備えた基板の実装構造。A plurality of protruding terminals fixed to one of the two substrates disposed substantially in parallel, electrically connecting the two substrates, and having elasticity; and
Solder bumps that contact the terminals of the other substrate and fix the one substrate and the other substrate in a bent state, and electrically connect the two substrates,
PCB mounting structure with 前記突状端子と前記半田バンプとはアレイ状に配置されていることを特徴とする請求項６又は請求項７に記載の基板の実装構造。  8. The substrate mounting structure according to claim 6, wherein the protruding terminals and the solder bumps are arranged in an array. 前記突状端子は前記半田バンプよりも内側の領域に設けられていることを特徴とする請求項８に記載の基板の実装構造。  9. The board mounting structure according to claim 8, wherein the protruding terminals are provided in a region inside the solder bumps. 前記一方の基板及び前記他方の基板のいずれかの基板は半導体装置の基板であることを特徴とする請求項６〜９のいずれかに記載の基板の実装構造。  The substrate mounting structure according to claim 6, wherein one of the one substrate and the other substrate is a substrate of a semiconductor device.
JP13243798A 1998-05-14 1998-05-14 Board mounting method, board mounting structure Expired - Fee Related JP3895465B2 (en)

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