JPH11135712A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH11135712A JPH11135712A JP9294363A JP29436397A JPH11135712A JP H11135712 A JPH11135712 A JP H11135712A JP 9294363 A JP9294363 A JP 9294363A JP 29436397 A JP29436397 A JP 29436397A JP H11135712 A JPH11135712 A JP H11135712A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- insulating substrate
- package
- pads
- functional block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に係わ
り、特に１つのパッケージの中に半導体チップとその周
辺機能ブロックとを内蔵させた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip and its peripheral function blocks are incorporated in one package.
【０００２】[0002]
【従来の技術】近年、半導体素子の微細化技術が著しく
進展したことにより、１チップに集積される回路規模も
飛躍的に増大してきた。回路規模が増大したことにより
中央演算処理装置を中心にその周辺回路、電子部品等を
含む所定の機能処理システム全体を同一基板上に配置す
ることが容易に実現されるようになってきた。この種の
半導体装置のうちでマルチチップモジュールの一例が特
開平９−２２９８２号公報に記載されている。同公報記
載のマルチチップモジュールの断面図および平面図を示
した図５を参照すると、このマルチチップモジュール
は、半導体チップ２５が搭載されるアルミナセラミック
からなる絶縁性基板２７には予め必要な配線が施されて
おり、この配線に接続された外部リード２３が基板裏面
に植設されている。さらにこの基板裏面には、半導体チ
ップ２５を搭載するための凹部が設けられている。2. Description of the Related Art In recent years, with the remarkable progress in the miniaturization technology of semiconductor elements, the scale of circuits integrated on one chip has increased dramatically. Due to the increase in the circuit scale, it has become easy to arrange the entire predetermined function processing system including the central processing unit, its peripheral circuits, electronic components, and the like on the same substrate. An example of a multi-chip module of this type of semiconductor device is described in JP-A-9-22982. Referring to FIG. 5 which shows a cross-sectional view and a plan view of a multi-chip module described in the same publication, this multi-chip module has an insulating substrate 27 made of alumina ceramic on which a semiconductor chip 25 is mounted, and wiring required in advance. External leads 23 connected to the wiring are implanted on the back surface of the substrate. Further, a concave portion for mounting the semiconductor chip 25 is provided on the back surface of the substrate.
【０００３】この半導体チップ２５は、例えば発熱量の
多い中央処理ユニットＣＰＵや浮動小数点処理ユニット
ＦＰＵ等の論理回路素子であり、この半導体チップ２５
および凹部内に設けたステッチランド間を金属細線２６
で接続した後、ロウ材によりキャップ２４で封止を行っ
ている。The semiconductor chip 25 is a logic circuit element such as a central processing unit CPU or a floating point processing unit FPU which generates a large amount of heat.
And a thin metal wire 26 between the stitch lands provided in the recess.
After the connection, sealing is performed with the cap 24 using a brazing material.
【０００４】基板２７の凹部が設けられた裏面と反対面
にはキャリア２１が搭載される。このキャリア２１は、
裏面に凹部を有する絶縁基板であって、その側面には側
面電極２２が形成されている。さらに、キャリア表面に
は必要な配線および部品搭載のためのパッドが形成され
るとしている。A carrier 21 is mounted on a surface of the substrate 27 opposite to the back surface on which the concave portion is provided. This carrier 21
An insulating substrate having a concave portion on the back surface, and a side surface electrode 22 is formed on a side surface thereof. In addition, necessary wiring and pads for mounting components are formed on the surface of the carrier.
【０００５】このキャリア上に半田ペーストを印刷し、
メモリ等のモールドパッケージ半導体装置２８やチップ
コンデンサ等のチップ部品が搭載され、さらにこのキャ
リア２１上に別のキャリア２１を重ね合わせている。[0005] A solder paste is printed on the carrier,
Chip components such as a mold package semiconductor device 28 such as a memory and a chip capacitor are mounted, and another carrier 21 is superimposed on the carrier 21.
【０００６】絶縁性基板２７の半導体チップ２５の搭載
面と反対面にヒートシンク２９が高熱伝導性の接着剤３
０により接着された構成からなる。A heat sink 29 is provided on the surface of the insulating substrate 27 opposite to the surface on which the semiconductor chip 25 is mounted, with an adhesive 3 having high thermal conductivity.
0.
【０００７】このような構造を有する半導体装置におい
ては、これらの内蔵された機能ブロックと外部装置との
間で相互に授受される各種の信号や電源電流は、外部リ
ード２３を経由して伝送される。In a semiconductor device having such a structure, various signals and power supply currents mutually transmitted and received between these built-in functional blocks and external devices are transmitted via external leads 23. You.
【０００８】このように外部リード２３が外部端子とな
り、電気的に接続された状態では、外部に接続される装
置との何らかの原因により仮に過電流が流れた場合、半
導体装置に内蔵された半導体素子が破壊されることがあ
る。In the state where the external lead 23 is an external terminal and is electrically connected, if an overcurrent flows for some reason with a device connected to the outside, the semiconductor element built in the semiconductor device May be destroyed.
【０００９】この破壊を防止する手段の一つとして半導
体装置と外部装置との間の信号伝送を無線にすることが
考えられる。As one of means for preventing this destruction, it is conceivable to make signal transmission between a semiconductor device and an external device wireless.
【００１０】例えば、ＩＣカードもその一例である。デ
ータメモリおよびＣＰＵなどの制御素子を内蔵し必要な
情報が記録された従来のＩＣカードは、外部の所定の外
部装置に挿入することにより、ＩＣカードに内蔵される
ＣＰＵと外部装置とのデータの電送が行われる。For example, an IC card is one example. A conventional IC card in which necessary information is recorded by incorporating a control element such as a data memory and a CPU is inserted into an external predetermined external device, whereby data between the CPU incorporated in the IC card and the external device is exchanged. Electric transmission is performed.
【００１１】このＩＣカードを無線により外部装置との
データ電送を行う場合、カード内に無線部が当然必要で
ある。これを解決するためにこのＩＣカードを収容する
収容ケースを用いる例が特開平３−１４２２９２号公報
に記載されている。同公報記載の収容ケースは、ＩＣカ
ードとのデータを書き込み読み出すリードライト部と、
ＣＰＵと、無線部とを有し、外部装置の無線部と無線で
データを送受する。When wirelessly transmitting data to and from an external device using this IC card, a wireless unit is naturally required in the card. Japanese Patent Laid-Open No. 3-142292 discloses an example in which a housing case for housing the IC card is used to solve this problem. The storage case described in the publication includes a read / write unit that reads and writes data from and to an IC card,
It has a CPU and a wireless unit, and sends and receives data wirelessly to and from a wireless unit of an external device.
【００１２】[0012]
【発明が解決しようとする課題】前述した、外部リード
を経由して電源電流やデータの送受を行っている従来の
半導体装置においては、小型化、多ピン化の傾向が著し
いが、多ピン化になるとリードピッチが狭くなり、加工
コストが高くなる。さらに構造も複雑となり、不良発生
も多くなる。さらにまた、外部装置との間で相互に授受
される各種の信号や電源電流は、外部リード２３を経由
して伝送されるが、このような外部リード２３が外部端
子となり、電気的に接続された状態では、外部に接続さ
れる装置との何らかの原因により仮に過電流が流れた場
合、半導体装置に内蔵された半導体素子が破壊される。In the above-mentioned conventional semiconductor device in which power supply current and data are transmitted and received via external leads, there is a remarkable tendency to downsize and increase the number of pins. , The lead pitch becomes narrow, and the processing cost increases. Further, the structure becomes complicated, and the occurrence of defects increases. Furthermore, various signals and power supply currents exchanged with the external device are transmitted via the external leads 23. Such external leads 23 serve as external terminals and are electrically connected. In this state, if an overcurrent flows for some reason with a device connected to the outside, the semiconductor element built in the semiconductor device is destroyed.
【００１３】一方、ＩＣカードを収納する携帯可能で、
かつ無線でデータを送受する機能を持つ収納ケースは、
長時間使用すると供給電源の電流供給能力が低下し、誤
動作の原因となる。On the other hand, a portable device for storing an IC card,
And the storage case with the function to send and receive data wirelessly,
When used for a long time, the current supply capability of the power supply is reduced, which may cause a malfunction.
【００１４】本発明の目的は、上述した欠点に鑑みなさ
れたものであり、外部リードを有しない、携帯性のある
半導体装置を提供することにある。An object of the present invention is to provide a portable semiconductor device having no external leads in view of the above-mentioned drawbacks.
【００１５】[0015]
【課題を解決するための手段】本発明の半導体装置は、
制御用の半導体チップとこの半導体チップの入出力信号
を外部装置との間で無線で送受信する機能ブロックとを
内蔵することにより、外部装置との入出力信号用の外部
リードを持たないリードレス構造のパッケージとするこ
とを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
Leadless structure with no external leads for input / output signals with external devices by incorporating a control semiconductor chip and a functional block for wirelessly transmitting and receiving input / output signals of the semiconductor chips to / from external devices. The package is characterized in that:
【００１６】また、前記リードレス構造を樹脂パッケー
ジとすることもできる。The leadless structure may be a resin package.
【００１７】さらに、前記機能ブロックを有する前記リ
ードレス構造のパッケージ単独で携帯用装置を構成する
こともできる。Further, a portable device can be constituted by the leadless structure package having the functional blocks alone.
【００１８】さらにまた、予め必要な配線が施された絶
縁性基板の裏面に前記半導体チップが搭載され、この半
導体チップ上の信号入出力用パッドと前記半導体チップ
搭載面に前記半導体チップを囲むように配設されたリー
ドおよび第１のパッドとがそれぞれ金属細線でワイヤボ
ンディングされて電気的に接続され、これら金属配線で
接続された前記パッド下の絶縁性基板にはスルーホール
がそれぞれ形成され、これらのスルーホールで接続され
る前記絶縁性基板の前記半導体チップ搭載面の反対面に
は、前記スルーホールの位置に第２のパッドがそれぞれ
設けられ、この半導体チップがフェイスアップの状態に
なるように絶縁性基板に搭載された状態で、かつこの絶
縁性基板面積と略等面積で上部が開口された樹脂封止パ
ッケージが用いられ、前記開口部に前記機能ブロック搭
載の絶縁性基板が配置され、前記機能ブロックおよび前
記半導体チップ間を接続する第２および第３のパッドが
設けられ、これら第２および第３のパッドが対応する前
記第１および前記第２のパッドとそれぞれ１対１で熱圧
着されたリードレスのパッケージ構造を有する。Further, the semiconductor chip is mounted on the back surface of an insulating substrate on which necessary wiring is provided in advance, and the signal input / output pads on the semiconductor chip and the semiconductor chip mounting surface surround the semiconductor chip. Are electrically connected to each other by wire bonding with fine metal wires, and through holes are formed in the insulating substrate below the pads connected by these metal wires, respectively. On the surface of the insulating substrate connected by these through holes opposite to the semiconductor chip mounting surface, second pads are provided at the positions of the through holes, respectively, so that the semiconductor chip is in a face-up state. A resin-encapsulated package is used which is mounted on an insulating substrate and has an opening at the top with an area approximately equal to the area of the insulating substrate. An insulating substrate on which the functional block is mounted is disposed in the opening, and second and third pads for connecting the functional block and the semiconductor chip are provided, and the second and third pads correspond to each other. It has a leadless package structure which is thermocompression-bonded one-to-one with the first and second pads.
【００１９】本発明の半導体装置の製造方法は、制御用
の半導体チップとこの半導体チップの入出力信号を外部
装置との間で無線で送受信するとともに、受信した信号
を整流して所定の電源電流に変換する手段を有する機能
ブロックとを内蔵することにより、外部装置との入出力
信号用の外部リードを持たないリードレス構造のパッケ
ージをもつ半導体装置の製造方法において、予め所定の
配線が印刷配線で形成され、さらに、後工程で前記半導
体チップが搭載される第１の絶縁性基板の信号入出力用
の第１および第２のパッド対応部分に半田ペーストによ
る第３および第４のパッドを形成した第２の絶縁性基板
に前記機能ブロックを搭載する第１の工程と、前記第２
の絶縁性基板の電気的特性試験をテスターで行い、良品
を選別する第２の工程と、予めウエハ選別試験で電気的
特性が確認され、ペレッタイズを完了した良品の前記半
導体チップが前記第１の絶縁性基板に搭載される第３の
工程と、予め前記第１および前記第２のパッドとスルー
ホール５を介して半田ペーストで第５および第６のパッ
ドが形成された前記第１の絶縁性基板に前記良品の半導
体チップが搭載される第４の工程と、前記半導体チップ
上の信号入出力パッドと前記第１の絶縁性基板上の前記
第１および前記第２のパッドとをそれぞれ金属細線を用
いて電気的接続をする第５の工程と、前記半導体チップ
が搭載された前記第１の絶縁性基板を電気的特性試験に
より良品選別する第６の工程と、前記第１の絶縁性基板
の上部樹脂部にこの絶縁性基板と同じ面積の開口部を開
口するための開口用型が加工された成形型を用いて前記
第１の絶縁性基板をパッケージに樹脂封止する第７の工
程と、樹脂封止された前記パッケージの開口部から樹脂
接着剤を塗布し、その上に前記機能ブロックが搭載され
た前記第２の絶縁性基板をはめ込み、高温加熱によるリ
フローで前記第１および前記第２の絶縁成基板それぞれ
の前記第３および前記第４並びに前記第５および前記６
のパッドを溶融しソルダリングする第８の工程と、予め
用意したカバーの周縁部に接着剤を塗布し、このカバー
を前記機能ブロックに被せて前記パッケージの前記開口
部周縁部に固定する第９の工程と、前記第９の工程完了
後、組立後の外観チェックに続いて電気的特性試験に移
行し、外部の専用測定装置との間で無線により所定信号
を送受信させて前記半導体チップおよび前記機能ブロッ
ク内の各部ブロックの総合動作試験を行う第１０の工程
とを有することを特徴とする。According to the method of manufacturing a semiconductor device of the present invention, a semiconductor chip for control and an input / output signal of the semiconductor chip are wirelessly transmitted / received to / from an external device, and the received signal is rectified to a predetermined power supply current. In a method of manufacturing a semiconductor device having a leadless structure package having no external leads for input / output signals to / from an external device by incorporating a functional block having means for converting Further, third and fourth pads are formed by solder paste on portions corresponding to the first and second pads for signal input / output of the first insulating substrate on which the semiconductor chip is mounted in a later step. A first step of mounting the functional block on the second insulating substrate thus formed;
The electrical characteristics test of the insulating substrate is performed by a tester, and a second step of selecting non-defective products, and the electrical characteristics of the non-defective products which have been confirmed in advance by a wafer selection test and which have been pelletized, are subjected to the first process. A third step of mounting on an insulating substrate; and forming the first and second pads in which fifth and sixth pads are formed in advance with solder paste through the first and second pads and through holes 5. A fourth step of mounting the non-defective semiconductor chip on the substrate, and a signal thin line between the signal input / output pad on the semiconductor chip and the first and second pads on the first insulating substrate. A fifth step of making an electrical connection by using a semiconductor device, a sixth step of selecting a non-defective product from the first insulating substrate on which the semiconductor chip is mounted by an electrical characteristic test, and the first insulating substrate On the upper resin part of A seventh step of resin-sealing the first insulating substrate in a package using a molding die in which an opening die for opening an opening having the same area as the insulating substrate is processed; A resin adhesive is applied from the opening of the package, the second insulating substrate on which the functional block is mounted is fitted thereon, and the first and second insulating substrates are reflowed by high-temperature heating. The third and fourth and the fifth and sixth, respectively,
An eighth step of melting and soldering the pad, and an ninth step of applying an adhesive to a peripheral portion of a previously prepared cover, covering the functional block with the cover, and fixing the cover to the peripheral portion of the opening of the package. After the completion of the ninth step, the process proceeds to an electrical characteristic test following the appearance check after assembly, and a predetermined signal is wirelessly transmitted to and received from an external dedicated measuring device, so that the semiconductor chip and the And a tenth step of performing a comprehensive operation test of each block in the functional block.
【００２０】[0020]
【発明の実施の形態】まず、本発明の一実施の形態を図
面を参照しながら説明する。図１は本発明の半導体装置
の断面図であり、図２は絶縁性基板に半導体チップが搭
載された状態を示す平面図である。図１を参照すると、
予め必要な配線が施された絶縁性基板１の裏面に半導体
チップ２がフェイスアップで搭載され、この半導体チッ
プ２上の信号入出力用のパッド（図２参照））と絶縁性
基板１の裏面に半導体チップ２を囲むように配設された
リード３ａおよびパッド３ｂとが金属細線４でワイヤボ
ンディングされ、これらパッド間の電気的接続がなされ
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device of the present invention, and FIG. 2 is a plan view showing a state where a semiconductor chip is mounted on an insulating substrate. Referring to FIG.
The semiconductor chip 2 is mounted face-up on the back surface of the insulating substrate 1 on which necessary wiring has been previously provided, and the signal input / output pads (see FIG. 2) on the semiconductor chip 2 and the back surface of the insulating substrate 1 The leads 3a and the pads 3b arranged so as to surround the semiconductor chip 2 are wire-bonded with the fine metal wires 4, and the pads are electrically connected.
【００２１】この金属配線４に接続された絶縁基板１上
のパッド下の絶縁基板にはスルーホール５ａ，５ｂがそ
れぞれ形成され、これらのスルーホール５ａ，５ｂと反
対側の面に形成された内部リード（パッド）６ａ，６ｂ
にそれぞれ１対１で接続されている。半導体チップ２
は、例えばＣＰＵ、メモリ、周辺回路を含む１チップの
論理回路素子であり、絶縁性基板１に樹脂接着剤７で接
着される。半導体チップ２の素子形成面にはパッド３ｃ
が千鳥状で２列に形成されている。Through holes 5a and 5b are respectively formed in the insulating substrate below the pads on the insulating substrate 1 connected to the metal wiring 4, and an inner surface formed on a surface opposite to the through holes 5a and 5b. Leads (pads) 6a, 6b
Are connected one-to-one. Semiconductor chip 2
Is a one-chip logic circuit element including, for example, a CPU, a memory, and a peripheral circuit, and is bonded to the insulating substrate 1 with a resin adhesive 7. A pad 3c is formed on the element forming surface of the semiconductor chip 2.
Are staggered and formed in two rows.
【００２２】図２を参照すると、この絶縁性基板１の周
辺部には、半導体チップ２の４辺と対向するようにリー
ド３ａが配設され、これらのリード３ａの絶縁性基板縁
端側の一端には第１のスルーホール５ａが形成されてい
る。さらに、これらのリード３ａと半導体チップ２の４
辺との間にもそれぞれ第２のスルーホール５ｂが形成さ
れている。これらのリード３ａの他端と半導体チップ２
のパッド３ｃのうち、内側の列のパッドとが金属細線４
でワイヤボンディングされている。半導体チップ２のパ
ッドのうち、外側の列のパッドと第２のスルーホールと
の間も金属細線でそれぞれワイヤボンディングされて電
気的接続がなされている。Referring to FIG. 2, leads 3a are arranged on the periphery of the insulating substrate 1 so as to face four sides of the semiconductor chip 2, and these leads 3a are located on the edge side of the insulating substrate. A first through hole 5a is formed at one end. Furthermore, these leads 3a and 4
Second through holes 5b are also formed between the sides. The other ends of these leads 3a and the semiconductor chip 2
Out of the pads 3c, the pads in the inner row
Wire bonding. Of the pads of the semiconductor chip 2, the outer rows of pads and the second through holes are also electrically connected by wire bonding with fine metal wires.
【００２３】この半導体チップ２がフェイスアップの状
態になるように絶縁性基板１に搭載された状態で、かつ
この絶縁性基板１の面積で上部が開口された樹脂封止パ
ッケージ構造を有する。The semiconductor chip 2 has a resin-sealed package structure in which the semiconductor chip 2 is mounted on the insulating substrate 1 so as to be in a face-up state and an upper portion is opened in an area of the insulating substrate 1.
【００２４】絶縁性基板１の半導体チップ搭載面の反対
面には、前述したスルーホール５ａ，５ｂの位置にパッ
ド６ａ，６ｂが設けてある。この半導体チップ搭載面の
反対面には、機能ブロック８が搭載された絶縁性基板９
がブロック搭載面の反対面が互いに対向するように配置
される。On the surface of the insulating substrate 1 opposite to the surface on which the semiconductor chip is mounted, pads 6a and 6b are provided at the positions of the aforementioned through holes 5a and 5b. An insulating substrate 9 on which the functional block 8 is mounted is provided on the surface opposite to the semiconductor chip mounting surface.
Are arranged such that opposite surfaces of the block mounting surface face each other.
【００２５】この機能ブロック搭載面の反対面には、半
導体チップ搭載面の反対面および機能ブロック搭載面の
反対面が互いに対向するように配置されたときに前述し
たスルーホール５ａ，５ｂの対応するホール位置にパッ
ド１０ａ，１０ｂが設けられている。これらのスルーホ
ール５ａ，５ｂに対応したパッド１０ａ，１０ｂは、機
能ブロック８の対応する端子と印刷配線で予め接続され
ている。The opposite surface of the functional block mounting surface corresponds to the aforementioned through holes 5a and 5b when the opposite surface of the semiconductor chip mounting surface and the opposite surface of the functional block mounting surface are arranged so as to face each other. Pads 10a and 10b are provided at the hole positions. The pads 10a and 10b corresponding to the through holes 5a and 5b are connected in advance to the corresponding terminals of the functional block 8 by printed wiring.
【００２６】機能ブロック８は、例えばアンテナを含む
無線受信部と、受信した電源電流信号とデータ信号のう
ち電源電流信号を整流する整流部と、この整流部の出力
する電源電流を蓄電する電池部と、外部装置へデータを
送信する送信部とからなり、データ信号が供給される半
導体チップ２は所定の処理動作を実行する。The functional block 8 includes, for example, a radio receiving unit including an antenna, a rectifying unit for rectifying a power supply current signal out of the received power supply current signal and data signal, and a battery unit for storing the power supply current output from the rectification unit. And a transmission unit for transmitting data to an external device, and the semiconductor chip 2 to which the data signal is supplied executes a predetermined processing operation.
【００２７】つまりこの半導体装置は、電源電流が無線
で供給されるため通常の電池交換の手間が無く、この装
置だけで独立した回路機能を有するとともに、外部リー
ドがないので携帯性がある。That is, this semiconductor device is supplied with power supply current wirelessly, so that there is no need for ordinary battery replacement. This device alone has an independent circuit function and has no external leads, so it is portable.
【００２８】上述した構造を有する半導体装置の製造工
程を示した図３を参照すると、予めこの半導体装置に搭
載する機能ブロック８は絶縁性基板９に搭載される。こ
の絶縁性基板９にはまず所定の配線が印刷配線で形成さ
れ、さらに、半導体チップ２が搭載された絶縁性基板１
のスルーホール５ａ，５ｂの位置に対応するパッド６
ａ，６ｂ，１０ａ，１０ｂ部分に半田ペーストによるパ
ッドを形成されている。機能ブロック８が絶縁性基板９
に搭載された状態で用意され、上述したそれぞれの回路
部の電気的試験をテスターで行い、良品であることを確
認しておく。この確認には後述する検査用テストボード
が共用される。Referring to FIG. 3 showing a manufacturing process of a semiconductor device having the above-described structure, a functional block 8 to be mounted on the semiconductor device is mounted on an insulating substrate 9 in advance. A predetermined wiring is first formed on the insulating substrate 9 by printed wiring, and further, the insulating substrate 1 on which the semiconductor chip 2 is mounted is mounted.
Pad 6 corresponding to the position of through holes 5a and 5b
Pads made of solder paste are formed on the portions a, 6b, 10a and 10b. The function block 8 is an insulating substrate 9
The electrical test of each of the above-mentioned circuit units is performed by a tester to confirm that the circuit units are non-defective. For this confirmation, an inspection test board to be described later is shared.
【００２９】次に、半導体チップ２は、通常のＬＳＩの
製造工程と同様に、ウエハ選別試験で電気的特性が確認
され、ペレッタイズを完了した良品が用意され、絶縁性
基板１に搭載される。Next, in the same manner as in a normal LSI manufacturing process, the semiconductor chip 2 is checked for its electrical characteristics by a wafer selection test, and a non-defective product having been pelletized is prepared and mounted on the insulating substrate 1.
【００３０】絶縁性基板１は、予め前述したリード３ａ
とスルーホール５ａ，５ｂが印刷配線されスルーホール
５ａ部分に半田ペーストでパッド３ｂが、スルーホール
５ｂ部分に半田ペーストでパッド５が形成されており、
この絶縁性基板１の中心部に半導体チップ２が搭載され
る。この半導体チップ２のパッド３ｃと絶縁性基板上の
リード３ａまたは第２のスルーホール５ｂ上のパッド５
とをそれぞれウェッジボンディング法で金属細線４を配
線する。The insulating substrate 1 is provided with the above-described lead 3a.
And the through holes 5a and 5b are printed and wired, and the pad 3b is formed in the through hole 5a portion with solder paste, and the pad 5 is formed in the through hole 5b portion with solder paste.
A semiconductor chip 2 is mounted on a central portion of the insulating substrate 1. The pad 3c of the semiconductor chip 2 and the lead 3a on the insulating substrate or the pad 5 on the second through hole 5b
And a thin metal wire 4 is wired by a wedge bonding method.
【００３１】その後、絶縁性基板１に搭載された半導体
チップ２の選別試験を、図４に示した検査用テストボー
ドを用いて実施し、良品と判断されたパッケージのみが
次工程に投入される。なお、この段階での選別検査は省
略して次工程でまとめて行ってもよい。After that, a sorting test of the semiconductor chip 2 mounted on the insulating substrate 1 is performed using the test board for inspection shown in FIG. 4, and only the packages judged as non-defective are put into the next step. . Note that the sorting inspection at this stage may be omitted, and may be performed collectively in the next step.
【００３２】次に、絶縁性基板１に搭載された半導体チ
ップ２を、通常行われているトランスファモールド法に
より所定の成形型の中で樹脂封止を行う。その際、絶縁
性基板１の上部の樹脂部には絶縁性基板１と同じ面積の
開口部を開けるために、開口用型が加工された成形型が
用いられる。成形された半導体装置は機能ブロック８の
規模にもよるが、約４０ｍｍ×４０ｍｍである。Next, the semiconductor chip 2 mounted on the insulating substrate 1 is sealed with a resin in a predetermined molding die by a usual transfer molding method. At this time, in order to open an opening having the same area as the insulating substrate 1, a molding die processed with an opening die is used for the resin portion above the insulating substrate 1. The molded semiconductor device is approximately 40 mm × 40 mm, depending on the size of the functional block 8.
【００３３】半導体チップ２が樹脂封止された段階で電
気的特性試験を行い良品を選別する。この選別で使用す
る治具として、前述した、絶縁基板上のスルーホール５
ａ，５ｂの位置に合わせ検査用探針１４が植設された検
査用テストボード１３を用いる。このテストボード１３
は各検査用探針１４とテスタを接続する配線群によりテ
ストヘッド部に装着される。なおこのテストボード１３
の検査用探針配置は、機能ブロック８の搭載された絶縁
性基板９および半導体チップ２が搭載された絶縁性基板
１のパッド位置が同一であるから、双方の試験に共用さ
れる。When the semiconductor chip 2 is sealed with a resin, an electrical characteristic test is performed to select non-defective products. As a jig used in this sorting, the above-described through-hole 5 on the insulating substrate is used.
An inspection test board 13 having an inspection probe 14 implanted at the positions a and 5b is used. This test board 13
Are mounted on the test head unit by a group of wires connecting each test probe 14 and the tester. This test board 13
In the inspection probe arrangement described above, the pad positions of the insulating substrate 9 on which the functional block 8 is mounted and the insulating substrate 1 on which the semiconductor chip 2 is mounted are the same, so that they are shared by both tests.
【００３４】次に、樹脂封止された半導体装置の樹脂パ
ッケージ１１の開口部から樹脂接着剤７を塗布し、その
上に機能ブロック８が搭載された絶縁性基板９をはめ込
み、赤外線フロー装置等の高温加熱によるリフローで両
絶縁成基板１，９の半田ペーストによるパッド６ａ，６
ｂ，１０ａ，１０ｂを溶融しソルダリングする。Next, a resin adhesive 7 is applied from the opening of the resin package 11 of the resin-sealed semiconductor device, and an insulating substrate 9 on which a functional block 8 is mounted is fitted thereon, and an infrared flow device or the like is mounted. Pads 6a, 6 of solder insulating paste on both insulating substrates 1, 9 by reflow by high-temperature heating of
b, 10a and 10b are melted and soldered.
【００３５】この後で、予め用意したプラスティックカ
バー１２の周縁部に接着剤を塗布し、このカバー１２を
機能ブロック８に被せて樹脂パッケージ１１の開口部周
縁部に固定する。ここまでの工程により本実施の形態の
半導体装置の組立工程は完了する。Thereafter, an adhesive is applied to the periphery of the plastic cover 12 prepared in advance, and the cover 12 is put on the functional block 8 and fixed to the periphery of the opening of the resin package 11. The steps up to here complete the assembly process of the semiconductor device of the present embodiment.
【００３６】全体の組立が完了した後、組立後の外観チ
ェックに続いて電気的特性試験に移行する。この試験で
は、この半導体装置を動作させる所定の周波数を外部の
専用測定装置から無線により送信させて半導体チップ２
および機能ブロック８内の各部ロック受信部、整流部、
電池部、送信部の総合動作試験を行うとともに、送信部
から発信された信号を専用測定装置で受信し動作を確認
する。After the entire assembly is completed, the process proceeds to the electrical characteristic test following the appearance check after the assembly. In this test, a predetermined frequency for operating this semiconductor device is wirelessly transmitted from an external dedicated measuring device to allow the semiconductor chip 2 to operate.
And a lock receiving section, a rectifying section,
A comprehensive operation test of the battery unit and the transmission unit is performed, and the signal transmitted from the transmission unit is received by the dedicated measuring device to confirm the operation.
【００３７】上述の説明では、１個の樹脂パッケージの
中に、半導体チップ、この例では専用の１チップＬＳＩ
としてそれ自身ＣＰＵ、メモリおよび周辺回路を内蔵し
た場合のパッケージ構造を説明しているが、絶縁性基板
１に搭載する半導体チップはＭＣＭ等の複数のＬＳＩか
ら構成することもできる。In the above description, a semiconductor chip, in this example, a dedicated one-chip LSI, is contained in one resin package.
Although a package structure in which a CPU, a memory, and a peripheral circuit are incorporated is described, the semiconductor chip mounted on the insulating substrate 1 may be composed of a plurality of LSIs such as an MCM.
【００３８】また、上述の例では電源電流を受信電波か
ら整流して得ている例を述べたが、この整流部および電
池部を削除し、通常のボタン電池を収納する構造として
もリードレスのパッケージとすることができる。In the above-described example, the power supply current is obtained by rectifying the received electric wave from the received radio wave. Can be packaged.
【００３９】従って、本実施の形態の半導体装置は、リ
ード部をなくすことにより多ピン対応が容易になり、小
型化ができるので、パッケージ単独で携帯用装置を構成
することが出来る。Therefore, the semiconductor device of the present embodiment can easily cope with a large number of pins by eliminating the lead portion and can be downsized, so that a portable device can be constituted by a package alone.
【００４０】[0040]
【発明の効果】以上説明したように、本発明の半導体装
置は、制御用の半導体チップとこの半導体チップの入出
力信号を外部装置との間で無線で送受信する機能ブロッ
クとを内蔵することにより、外部装置との入出力信号用
の外部リードを持たないリードレス構造のパッケージを
備えるので、パッケージの外部リードを省略でき、複雑
なリード加工が不要になる半導体装置が得られ、従って
小型化ができ、パッケージ単独で携帯用装置を構成する
ことが出来る。As described above, the semiconductor device of the present invention has a built-in semiconductor chip for control and a functional block for wirelessly transmitting and receiving input / output signals of the semiconductor chip to / from an external device. In addition, since a leadless structure package having no external leads for input / output signals with external devices is provided, it is possible to omit the external leads of the package and obtain a semiconductor device which does not require complicated lead processing. The portable device can be constituted by the package alone.
【図１】本発明の半導体装置における一実施の形態の断
面図である。FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention.
【図２】半導体チップ搭載状態の絶縁性基板の平面図で
ある。FIG. 2 is a plan view of an insulating substrate with a semiconductor chip mounted thereon.
【図３】本発明の半導体装置の製造工程説明用の断面図
である。FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor device of the present invention.
【図４】選別試験に用いる検査用テストボードの平面図
である。FIG. 4 is a plan view of an inspection test board used for a screening test.
【図５】従来の半導体装置の一例を示す図である。FIG. 5 is a diagram illustrating an example of a conventional semiconductor device.
１，９，２７ 絶縁性基板 ２，２５ 半導体チップ ３ａ リード ４，２６ 金属細線 ５ａ，５ｂ スルーホール ３ｂ，３ｃ，５，６ａ，６ｂ，１０ａ，１０ｂ パッ
ド ７，３０ 接着剤 ８ 機能ブロック １１ 樹脂パッケージ １２ カバー １３ 検査用テストボード １４ 検査用探針 ２１ キャリア ２２ 側面電極 ２３ 外部リード ２４ キャップ ２８ 半導体装置 ２９ ヒートシンク1,9,27 Insulating substrate 2,25 Semiconductor chip 3a Lead 4,26 Thin metal wire 5a, 5b Through hole 3b, 3c, 5,6a, 6b, 10a, 10b Pad 7,30 Adhesive 8 Functional block 11 Resin package DESCRIPTION OF SYMBOLS 12 Cover 13 Test board for inspection 14 Probe for inspection 21 Carrier 22 Side electrode 23 External lead 24 Cap 28 Semiconductor device 29 Heat sink
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１１年１月２２日[Submission date] January 22, 1999
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
【請求項２】 制御用の半導体チップとこの半導体チッ
プの入出力信号を外部装置との間で無線で送受信する機
能ブロックとを内蔵することにより、外部装置との入出
力信号用の外部リードを持たないリードレス構造のパッ
ケージとする半導体装置において、予め必要な配線が施
された絶縁性基板の裏面に前記半導体チップが搭載さ
れ、この半導体チップ上の信号入出力用パッドと前記半
導体チップ搭載面に前記半導体チップを囲むように配設
されたリードおよび第１のパッドとがそれぞれ金属細線
でワイヤボンディングされて電気的に接続され、これら
金属配線で接続された前記パッド下の絶縁性基板にはス
ルーホールがそれぞれ形成され、これらのスルーホール
で接続される前記絶縁性基板の前記半導体チップ搭載面
の反対面には、前記スルーホールの位置に第２のパッド
がそれぞれ設けられ、この半導体チップがフェイスアッ
プの状態になるように絶縁性基板に搭載された状態で、
かつこの絶縁性基板面積と略等面積で上部が開口された
樹脂封止パッケージが用いられ、前記開口部に前記機能
ブロック搭載の絶縁性基板が配置され、前記機能ブロッ
クおよび前記半導体チップ間を接続する第２および第３
のパッドが設けられ、これら第２および第３のパッドが
対応する前記第１および前記第２のパッドとそれぞれ１
対１で熱圧着されたリードレスのパッケージ構造を有す
ることを特徴とする半導体装置。 2. A control semiconductor chip and a semiconductor chip.
A device that wirelessly transmits and receives input / output signals to and from external devices
Built-in function block allows access to external devices
A leadless structure package without external leads for force signals
In a semiconductor device serving as a cage, the semiconductor chip is mounted on a back surface of an insulating substrate on which necessary wiring is provided in advance , and the signal input / output pads on the semiconductor chip and the semiconductor chip mounting surface surround the semiconductor chip. And the first pads are electrically connected by wire bonding with fine metal wires, and through holes are formed in the insulating substrate below the pads connected by these metal wires. A second pad is provided at the position of the through hole on a surface of the insulating substrate opposite to the semiconductor chip mounting surface connected by these through holes, and the semiconductor chip is in a face-up state. In the state mounted on the insulating substrate as
In addition, a resin-sealed package having an upper portion opened with substantially the same area as the insulating substrate area is used, and the insulating substrate having the functional block is arranged in the opening, and the functional block and the semiconductor chip are connected. Second and third
Are provided, and the second and third pads correspond to the first and second pads respectively corresponding to the first and second pads.
A semiconductor device having a leadless package structure thermocompression-bonded one-to-one.
【請求項３】 制御用の半導体チップとこの半導体チッ
プの入出力信号を外部装置との間で無線で送受信すると
ともに、受信した信号を整流して所定の電源電流に変換
する手段を有する機能ブロックとを内蔵することによ
り、外部装置との入出力信号用の外部リードを持たない
リードレス構造のパッケージをもつ半導体装置の製造方
法は、予め所定の配線が印刷配線で形成され、さらに、
後工程で前記半導体チップが搭載される第１の絶縁性基
板の信号入出力用の第１および第２のパッド対応部分に
半田ペーストによる第３および第４のパッドを形成した
第２の絶縁性基板に前記機能ブロックを搭載する第１の
工程と、前記第２の絶縁性基板の電気的特性試験をテス
ターで行い、良品を選別する第２の工程と、予めウエハ
選別試験で電気的特性が確認され、ペレッタイズを完了
した良品の前記半導体チップが前記第１の絶縁性基板に
搭載される第３の工程と、予め前記第１および前記第２
のパッドとスルーホール５を介して半田ペーストで第５
および第６のパッドが形成された前記第１の絶縁性基板
に前記良品の半導体チップが搭載される第４の工程と、
前記半導体チップ上の信号入出力パッドと前記第１の絶
縁性基板上の前記第１および前記第２のパッドとをそれ
ぞれ金属細線を用いて電気的接続をする第５の工程と、
前記半導体チップが搭載された前記第１の絶縁性基板を
電気的特性試験により良品選別する第６の工程と、前記
第１の絶縁性基板の上部樹脂部にこの絶縁性基板と同じ
面積の開口部を開口するための開口用型が加工された成
形型を用いて前記第１の絶縁性基板をパッケージに樹脂
封止する第７の工程と、樹脂封止された前記パッケージ
の開口部から樹脂接着剤を塗布し、その上に前記機能ブ
ロックが搭載された前記第２の絶縁性基板をはめ込み、
高温加熱によるリフローで前記第１および前記第２の絶
縁成基板それぞれの前記第３および前記第４並びに前記
第５および前記６のパッドを溶融しソルダリングする第
８の工程と、予め用意したカバーの周縁部に接着剤を塗
布し、このカバーを前記機能ブロックに被せて前記パッ
ケージの前記開口部周縁部に固定する第９の工程と、前
記第９の工程完了後、組立後の外観チェックに続いて電
気的特性試験に移行し、外部の専用測定装置との間で無
線により所定信号を送受信させて前記半導体チップおよ
び前記機能ブロック内の各部ブロックの総合動作試験を
行う第１０の工程とを有することを特徴とする半導体装
置の製造方法。 3. A functional block having a semiconductor chip for control and an input / output signal of the semiconductor chip wirelessly transmitted / received to / from an external device, and a means for rectifying the received signal and converting it to a predetermined power supply current. In the method for manufacturing a semiconductor device having a leadless structure package having no external leads for input / output signals with an external device, a predetermined wiring is formed in advance by a printed wiring,
A second insulating property in which third and fourth pads made of a solder paste are formed in portions corresponding to signal input / output first and second pads of a first insulating substrate on which the semiconductor chip is mounted in a later step. A first step of mounting the functional block on the substrate, a second step of performing an electrical characteristic test on the second insulating substrate with a tester and selecting non-defective products, A third step of mounting the non-defective semiconductor chip confirmed and pelletized on the first insulating substrate;
Fifth pad with solder paste through pad and through hole 5
A fourth step of mounting the non-defective semiconductor chip on the first insulating substrate on which the sixth pad is formed, and
A fifth step of electrically connecting the signal input / output pads on the semiconductor chip and the first and second pads on the first insulating substrate using thin metal wires, respectively;
A sixth step of selecting a non-defective product from the first insulating substrate on which the semiconductor chip is mounted by an electrical characteristic test, and forming an opening in the upper resin portion of the first insulating substrate having the same area as the insulating substrate. A seventh step of resin-sealing the first insulating substrate in a package using a molding die in which an opening mold for opening a portion is processed, and a step of resin-sealing the resin-sealed opening in the package. An adhesive is applied, and the second insulating substrate on which the functional block is mounted is fitted thereon.
An eighth step of melting and soldering the third and fourth and fifth and sixth pads of each of the first and second insulating substrates by reflow by high-temperature heating, and a cover prepared in advance A ninth step of applying an adhesive to the peripheral part of the package, covering the functional block with the cover, and fixing the cover to the peripheral part of the opening of the package; and after the completion of the ninth step, an external appearance check after assembly. Then, the process shifts to an electrical characteristic test, and performs a comprehensive operation test of each block in the semiconductor chip and the functional block by transmitting and receiving a predetermined signal wirelessly to and from an external dedicated measuring device. A method for manufacturing a semiconductor device, comprising:
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１５[Correction target item name] 0015
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１５】[0015]
【課題を解決するための手段】本発明の半導体装置は、
制御用の半導体チップを搭載し所定の信号入出力手段に
より外部装置と前記制御用の入出力信号の受け渡しをす
る携帯用装置として樹脂パッケージに一体成形された半
導体装置において、前記所定の入出力手段として、前記
半導体チップの動作電源電流生成用の信号受信と前記入
出力信号の送信および受信とを前記外部装置との間で無
線により行う送受信手段を含む機能ブロックを前記半導
体チップと共に内蔵し、かつ前記パッケージの表面、裏
面および側面のいずれにも前記外部装置との電気的接続
用の外部リードは設けないようにしたリードレス構造の
パッケージとすることを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
Equipped with a control semiconductor chip to serve as predetermined signal input / output means
Transfer of the control input / output signals to / from an external device.
As a portable device integrated into a resin package
In conductor device, transmission and reception performed as the predetermined input unit, by wireless and a transmission and reception of the <br/> semiconductor chip operating power supply current signal received and said input signal for generating in between the external device the semiconductor functional blocks including means
Embedded with the body chip , and the front and back of the package
Electrical connection to the external device on both sides and sides
In a leadless structure in which no external leads are provided .
【手続補正３】[Procedure amendment 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１６】また、制御用の半導体チップとこの半導体
チップの入出力信号を外部装置との間で無線で送受信す
る機能ブロックとを内蔵することにより、外部装置との
入出力信号用の外部リードを持たないリードレス構造の
パッケージとする半導体装置において、予め必要な配線
が施された絶縁性基板の裏面に前記半導体チップが搭載
され、この半導体チップ上の信号入出力用パッドと前記
半導体チップ搭載面に前記半導体チップを囲むように配
設されたリードおよび第１のパッドとがそれぞれ金属細
線でワイヤボンディングされて電気的に接続され、これ
ら金属配線で接続された前記パッド下の絶縁性基板には
スルーホールがそれぞれ形成され、これらのスルーホー
ルで接続される前記絶縁性基板の前記半導体チップ搭載
面の反対面には、前記スルーホールの位置に第２のパッ
ドがそれぞれ設けられ、この半導体チップがフェイスア
ップの状態になるように絶縁性基板に搭載された状態
で、かつこの絶縁性基板面積と略等面積で上部が開口さ
れた樹脂封止パッケージが用いられ、前記開口部に前記
機能ブロック搭載の絶縁性基板が配置され、前記機能ブ
ロックおよび前記半導体チップ間を接続する第２および
第３のパッドが設けられ、これら第２および第３のパッ
ドが対応する前記第１および前記第２のパッドとそれぞ
れ１対１で熱圧着されたリードレスのパッケージ構造を
有する。Also, a control semiconductor chip and this semiconductor chip
Sends and receives chip I / O signals wirelessly to and from external devices
Built-in functional blocks for
Leadless structure without external leads for input / output signals
Wiring required in advance for semiconductor devices to be packaged
The semiconductor chip is mounted on the back of the insulated substrate
And a signal input / output pad on the semiconductor chip and
Arrange on the semiconductor chip mounting surface so as to surround the semiconductor chip.
The lead and the first pad provided are
The wires are wire-bonded and electrically connected.
The insulating substrate below the pad connected by metal wiring
Through holes are formed respectively, and these through holes
Mounting the semiconductor chip on the insulating substrate connected by a
On the surface opposite to the surface, a second package is provided at the position of the through hole.
This semiconductor chip is faced
Mounted on an insulating substrate so that
And the upper part is opened with an area approximately equal to the area of the insulating substrate.
A resin-sealed package is used, and the opening is
An insulating board with a functional block is placed, and the functional block is
A second connecting the lock and the semiconductor chip;
A third pad is provided, and the second and third pads are provided.
And the first and second pads corresponding to the
The leadless package structure is thermocompression-bonded one-to-one.
That Yusuke.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１７[Correction target item name] 0017
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１７】さらに、本発明の半導体装置の製造方法
は、制御用の半導体チップとこの半導体チップの入出力
信号を外部装置との間で無線で送受信するとともに、受
信した信号を整流して所定の電源電流に変換する手段を
有する機能ブロックとを内蔵することにより、外部装置
との入出力信号用の外部リードを持たないリードレス構
造のパッケージをもつ半導体装置の製造方法は、予め所
定の配線が印刷配線で形成され、さらに、後工程で前記
半導体チップが搭載される第１の絶縁性基板の信号入出
力用の第１および第２のパッド対応部分に半田ペースト
による第３および第４のパッドを形成した第２の絶縁性
基板に前記機能ブロックを搭載する第１の工程と、前記
第２の絶縁性基板の電気的特性試験をテスターで行い、
良品を選別する第２の工程と、予めウエハ選別試験で電
気的特性が確認され、ペレッタイズを完了した良品の前
記半導体チップが前記第１の絶縁性基板に搭載される第
３の工程と、予め前記第１および前記第２のパッドとス
ルーホール５を介して半田ペーストで第５および第６の
パッドが形成された前記第１の絶縁性基板に前記良品の
半導体チップが搭載される第４の工程と、前記半導体チ
ップ上の信号入出力パッドと前記第１の絶縁性基板上の
前記第１および前記第２のパッドとをそれぞれ金属細線
を用いて電気的接続をする第５の工程と、前記半導体チ
ップが搭載された前記第１の絶縁性基板を電気的特性試
験により良品選別する第６の工程と、前記第１の絶縁性
基板の上部樹脂部にこの絶縁性基板と同じ面積の開口部
を開口するための開口用型が加工された成形型を用いて
前記第１の絶縁性基板をパッケージに樹脂封止する第７
の工程と、樹脂封止された前記パッケージの開口部から
樹脂接着剤を塗布し、その上に前記機能ブロックが搭載
された前記第２の絶縁性基板をはめ込み、高温加熱によ
るリフローで前記第１および前記第２の絶縁成基板それ
ぞれの前記第３および前記第４並びに前記第５および前
記６のパッドを溶融しソルダリングする第８の工程と、
予め用意したカバーの周縁部に接着剤を塗布し、このカ
バーを前記機能ブロックに被せて前記パッケージの前記
開口部周縁部に固定する第９の工程と、前記第９の工程
完了後、組立後の外観チェックに続いて電気的特性試験
に移行し、外部の専用測定装置との間で無線により所定
信号を送受信させて前記半導体チップおよび前記機能ブ
ロック内の各部ブロックの総合動作試験を行う第１０の
工程とを有することを特徴とする。Further, a method of manufacturing a semiconductor device according to the present invention.
Is the semiconductor chip for control and the input / output of this semiconductor chip.
Transmits and receives signals to and from external devices wirelessly,
Means for rectifying the received signal and converting it to a predetermined power supply current.
External devices by incorporating
Leadless structure without external leads for input / output signals
The manufacturing method of a semiconductor device having a package
Fixed wiring is formed by printed wiring, and furthermore,
Signal input / output of the first insulating substrate on which the semiconductor chip is mounted
Solder paste on first and second pad portions corresponding to force
Second insulation formed with third and fourth pads by the method
A first step of mounting the functional block on a substrate,
An electrical property test of the second insulating substrate is performed by a tester,
In the second step of selecting non-defective products, and beforehand in the wafer selection test
In front of a non-defective product whose temper characteristics have been confirmed and pelletized
A semiconductor chip mounted on the first insulating substrate;
Step 3, and the first and second pads and
The fifth and sixth solder pastes are inserted through the through holes 5.
The non-defective product is provided on the first insulating substrate on which the pad is formed.
A fourth step of mounting a semiconductor chip;
Signal input / output pad on the chip and on the first insulating substrate
The first and second pads are each formed of a thin metal wire;
A fifth step of making an electrical connection by using the semiconductor chip;
The first insulating substrate having the chip mounted thereon is tested for electrical characteristics.
A sixth step of selecting good products by an experiment, and the first insulating property
Opening in the upper resin part of the board with the same area as this insulating board
Using a mold that has an opening mold for opening
A seventh step of resin-sealing the first insulating substrate in a package;
From the opening of the resin-sealed package
Apply resin adhesive and mount the functional block on it
The above-mentioned second insulating substrate is fitted and heated by high temperature.
The first and second insulating substrates by reflow
The third and fourth and the fifth and front respectively
An eighth step of melting and soldering the pad of the above (6);
Apply adhesive to the periphery of the prepared cover, and
Place a bar on the functional block and
A ninth step of fixing to the periphery of the opening, and the ninth step
After completion, after the appearance check after assembly, electrical characteristics test
, And wirelessly communicates with an external dedicated measuring device.
The semiconductor chip and the functional block by transmitting and receiving signals.
Tenth test for comprehensive operation test of each block in the lock
You; and a step.
【手続補正５】[Procedure amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１８[Correction target item name] 0018
【補正方法】削除[Correction method] Deleted
【手続補正６】[Procedure amendment 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１９[Correction target item name] 0019
【補正方法】削除[Correction method] Deleted
Claims (5)
プの入出力信号を外部装置との間で無線で送受信する機
能ブロックとを内蔵することにより、外部装置との入出
力信号用の外部リードを持たないリードレス構造のパッ
ケージとすることを特徴とする半導体装置。A semiconductor chip for control and a functional block for wirelessly transmitting and receiving input / output signals of the semiconductor chip to / from an external device are built in, so that external leads for input / output signals to / from the external device are provided. A semiconductor device having a leadless structure package not provided.
する請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said leadless structure is a resin package.
ス構造のパッケージ単独で携帯用装置を構成する請求項
１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said leadless structure package having said functional block forms a portable device alone.
裏面に前記半導体チップが搭載され、この半導体チップ
上の信号入出力用パッドと前記半導体チップ搭載面に前
記半導体チップを囲むように配設されたリードおよび第
１のパッドとがそれぞれ金属細線でワイヤボンディング
されて電気的に接続され、これら金属配線で接続された
前記パッド下の絶縁性基板にはスルーホールがそれぞれ
形成され、これらのスルーホールで接続される前記絶縁
性基板の前記半導体チップ搭載面の反対面には、前記ス
ルーホールの位置に第２のパッドがそれぞれ設けられ、
この半導体チップがフェイスアップの状態になるように
絶縁性基板に搭載された状態で、かつこの絶縁性基板面
積と略等面積で上部が開口された樹脂封止パッケージが
用いられ、前記開口部に前記機能ブロック搭載の絶縁性
基板が配置され、前記機能ブロックおよび前記半導体チ
ップ間を接続する第２および第３のパッドが設けられ、
これら第２および第３のパッドが対応する前記第１およ
び前記第２のパッドとそれぞれ１対１で熱圧着されたリ
ードレスのパッケージ構造を有する請求項１記載の半導
体装置。4. The semiconductor chip is mounted on a back surface of an insulating substrate on which necessary wiring has been provided in advance, and signal input / output pads on the semiconductor chip and the semiconductor chip mounting surface surround the semiconductor chip. The arranged leads and the first pads are electrically connected by wire bonding with thin metal wires, respectively, and through holes are formed in the insulating substrate below the pads connected by these metal wires, respectively. A second pad is provided at a position of the through-hole on a surface of the insulating substrate opposite to the semiconductor chip mounting surface connected by the through-hole.
In a state where the semiconductor chip is mounted on an insulating substrate so as to be in a face-up state, and a resin-sealed package having an upper portion opened with substantially the same area as the insulating substrate area is used. An insulating substrate on which the functional block is mounted, second and third pads for connecting the functional block and the semiconductor chip are provided,
2. The semiconductor device according to claim 1, wherein said second and third pads have a leadless package structure thermocompression-bonded one-to-one with said corresponding first and second pads.
プの入出力信号を外部装置との間で無線で送受信すると
ともに、受信した信号を整流して所定の電源電流に変換
する手段を有する機能ブロックとを内蔵することによ
り、外部装置との入出力信号用の外部リードを持たない
リードレス構造のパッケージをもつ半導体装置の製造方
法は、予め所定の配線が印刷配線で形成され、さらに、
後工程で前記半導体チップが搭載される第１の絶縁性基
板の信号入出力用の第１および第２のパッド対応部分に
半田ペーストによる第３および第４のパッドを形成した
第２の絶縁性基板に前記機能ブロックを搭載する第１の
工程と、前記第２の絶縁性基板の電気的特性試験をテス
ターで行い、良品を選別する第２の工程と、予めウエハ
選別試験で電気的特性が確認され、ペレッタイズを完了
した良品の前記半導体チップが前記第１の絶縁性基板に
搭載される第３の工程と、予め前記第１および前記第２
のパッドとスルーホール５を介して半田ペーストで第５
および第６のパッドが形成された前記第１の絶縁性基板
に前記良品の半導体チップが搭載される第４の工程と、
前記半導体チップ上の信号入出力パッドと前記第１の絶
縁性基板上の前記第１および前記第２のパッドとをそれ
ぞれ金属細線を用いて電気的接続をする第５の工程と、
前記半導体チップが搭載された前記第１の絶縁性基板を
電気的特性試験により良品選別する第６の工程と、前記
第１の絶縁性基板の上部樹脂部にこの絶縁性基板と同じ
面積の開口部を開口するための開口用型が加工された成
形型を用いて前記第１の絶縁性基板をパッケージに樹脂
封止する第７の工程と、樹脂封止された前記パッケージ
の開口部から樹脂接着剤を塗布し、その上に前記機能ブ
ロックが搭載された前記第２の絶縁性基板をはめ込み、
高温加熱によるリフローで前記第１および前記第２の絶
縁成基板それぞれの前記第３および前記第４並びに前記
第５および前記６のパッドを溶融しソルダリングする第
８の工程と、予め用意したカバーの周縁部に接着剤を塗
布し、このカバーを前記機能ブロックに被せて前記パッ
ケージの前記開口部周縁部に固定する第９の工程と、前
記第９の工程完了後、組立後の外観チェックに続いて電
気的特性試験に移行し、外部の専用測定装置との間で無
線により所定信号を送受信させて前記半導体チップおよ
び前記機能ブロック内の各部ブロックの総合動作試験を
行う第１０の工程とを有することを特徴とする半導体装
置の製造方法。5. A functional block having a semiconductor chip for control and an input / output signal of the semiconductor chip wirelessly transmitted / received to / from an external device, and a means for rectifying the received signal and converting it to a predetermined power supply current. In the method for manufacturing a semiconductor device having a leadless structure package having no external leads for input / output signals with an external device, a predetermined wiring is formed in advance by a printed wiring,
A second insulating property in which third and fourth pads made of a solder paste are formed in portions corresponding to signal input / output first and second pads of a first insulating substrate on which the semiconductor chip is mounted in a later step. A first step of mounting the functional block on the substrate, a second step of performing an electrical characteristic test on the second insulating substrate with a tester and selecting non-defective products, A third step of mounting the non-defective semiconductor chip confirmed and pelletized on the first insulating substrate;
Fifth pad with solder paste through pad and through hole 5
A fourth step of mounting the non-defective semiconductor chip on the first insulating substrate on which the sixth pad is formed, and
A fifth step of electrically connecting the signal input / output pads on the semiconductor chip and the first and second pads on the first insulating substrate using thin metal wires, respectively;
A sixth step of selecting a non-defective product from the first insulating substrate on which the semiconductor chip is mounted by an electrical characteristic test, and forming an opening in the upper resin portion of the first insulating substrate having the same area as the insulating substrate. A seventh step of resin-sealing the first insulating substrate in a package using a molding die in which an opening mold for opening a portion is processed, and a step of resin-sealing the resin-sealed opening in the package. An adhesive is applied, and the second insulating substrate on which the functional block is mounted is fitted thereon.
An eighth step of melting and soldering the third and fourth and fifth and sixth pads of each of the first and second insulating substrates by reflow by high-temperature heating, and a cover prepared in advance A ninth step of applying an adhesive to the peripheral part of the package, covering the functional block with the cover, and fixing the cover to the peripheral part of the opening of the package; and after the completion of the ninth step, an external appearance check after assembly. Then, the process shifts to an electrical characteristic test, and performs a comprehensive operation test of each block in the semiconductor chip and the functional block by transmitting and receiving a predetermined signal wirelessly to and from an external dedicated measuring device. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9294363A JP3001481B2 (en) | 1997-10-27 | 1997-10-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9294363A JP3001481B2 (en) | 1997-10-27 | 1997-10-27 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135712A true JPH11135712A (en) | 1999-05-21 |
| JP3001481B2 JP3001481B2 (en) | 2000-01-24 |
Family
ID=17806749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9294363A Expired - Fee Related JP3001481B2 (en) | 1997-10-27 | 1997-10-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3001481B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005074029A1 (en) * | 2004-01-28 | 2005-08-11 | Matsushita Electric Industrial Co., Ltd. | Module and mounting structure using the same |
| JP2010245289A (en) * | 2009-04-06 | 2010-10-28 | Canon Inc | Method of manufacturing semiconductor device |
| US8647923B2 (en) | 2009-04-06 | 2014-02-11 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
| JP2015515115A (en) * | 2012-01-26 | 2015-05-21 | ジョンソン・アンド・ジョンソン・ビジョン・ケア・インコーポレイテッドＪｏｈｎｓｏｎ ＆ Ｊｏｈｎｓｏｎ Ｖｉｓｉｏｎ Ｃａｒｅ， Ｉｎｃ． | Multiple energy application elements in a stacked monolithic component device |
| US10345620B2 (en) | 2016-02-18 | 2019-07-09 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices |
| US10361404B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Anodes for use in biocompatible energization elements |
| US10361405B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes |
| US10367233B2 (en) | 2014-08-21 | 2019-07-30 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes and cavity structures |
| US10374216B2 (en) | 2014-08-21 | 2019-08-06 | Johnson & Johnson Vision Care, Inc. | Pellet form cathode for use in a biocompatible battery |
| US10381687B2 (en) | 2014-08-21 | 2019-08-13 | Johnson & Johnson Vision Care, Inc. | Methods of forming biocompatible rechargable energization elements for biomedical devices |
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| US10451897B2 (en) | 2011-03-18 | 2019-10-22 | Johnson & Johnson Vision Care, Inc. | Components with multiple energization elements for biomedical devices |
| US10558062B2 (en) | 2014-08-21 | 2020-02-11 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical device |
| US10598958B2 (en) | 2014-08-21 | 2020-03-24 | Johnson & Johnson Vision Care, Inc. | Device and methods for sealing and encapsulation for biocompatible energization elements |
| US10627651B2 (en) | 2014-08-21 | 2020-04-21 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers |
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-
1997
- 1997-10-27 JP JP9294363A patent/JP3001481B2/en not_active Expired - Fee Related
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|---|---|---|---|---|
| WO2005074029A1 (en) * | 2004-01-28 | 2005-08-11 | Matsushita Electric Industrial Co., Ltd. | Module and mounting structure using the same |
| CN100429773C (en) * | 2004-01-28 | 2008-10-29 | 松下电器产业株式会社 | Module and mounting structure using the same |
| US7667974B2 (en) | 2004-01-28 | 2010-02-23 | Panasonic Corporation | Module and mounted structure using the same |
| US7859855B2 (en) | 2004-01-28 | 2010-12-28 | Panasonic Corporation | Module and mounted structure using the same |
| JP2010245289A (en) * | 2009-04-06 | 2010-10-28 | Canon Inc | Method of manufacturing semiconductor device |
| US8647923B2 (en) | 2009-04-06 | 2014-02-11 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
| US10451897B2 (en) | 2011-03-18 | 2019-10-22 | Johnson & Johnson Vision Care, Inc. | Components with multiple energization elements for biomedical devices |
| JP2017199003A (en) * | 2012-01-26 | 2017-11-02 | ジョンソン・アンド・ジョンソン・ビジョン・ケア・インコーポレイテッドＪｏｈｎｓｏｎ ＆ Ｊｏｈｎｓｏｎ Ｖｉｓｉｏｎ Ｃａｒｅ， Ｉｎｃ． | Multiple energization elements in stacked integrated component device |
| US10775644B2 (en) | 2012-01-26 | 2020-09-15 | Johnson & Johnson Vision Care, Inc. | Ophthalmic lens assembly having an integrated antenna structure |
| JP2015515115A (en) * | 2012-01-26 | 2015-05-21 | ジョンソン・アンド・ジョンソン・ビジョン・ケア・インコーポレイテッドＪｏｈｎｓｏｎ ＆ Ｊｏｈｎｓｏｎ Ｖｉｓｉｏｎ Ｃａｒｅ， Ｉｎｃ． | Multiple energy application elements in a stacked monolithic component device |
| US10381687B2 (en) | 2014-08-21 | 2019-08-13 | Johnson & Johnson Vision Care, Inc. | Methods of forming biocompatible rechargable energization elements for biomedical devices |
| US10367233B2 (en) | 2014-08-21 | 2019-07-30 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes and cavity structures |
| US10374216B2 (en) | 2014-08-21 | 2019-08-06 | Johnson & Johnson Vision Care, Inc. | Pellet form cathode for use in a biocompatible battery |
| US10361405B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes |
| US10386656B2 (en) | 2014-08-21 | 2019-08-20 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form separators for biocompatible energization elements for biomedical devices |
| US10361404B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Anodes for use in biocompatible energization elements |
| US10558062B2 (en) | 2014-08-21 | 2020-02-11 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical device |
| US10598958B2 (en) | 2014-08-21 | 2020-03-24 | Johnson & Johnson Vision Care, Inc. | Device and methods for sealing and encapsulation for biocompatible energization elements |
| US10627651B2 (en) | 2014-08-21 | 2020-04-21 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers |
| US10345620B2 (en) | 2016-02-18 | 2019-07-09 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3001481B2 (en) | 2000-01-24 |
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