JPH11111738A - Cob and method for manufacturing the same, semiconductor element and method for manufacturing the same - Google Patents
Cob and method for manufacturing the same, semiconductor element and method for manufacturing the sameInfo
- Publication number
- JPH11111738A JPH11111738A JP29169597A JP29169597A JPH11111738A JP H11111738 A JPH11111738 A JP H11111738A JP 29169597 A JP29169597 A JP 29169597A JP 29169597 A JP29169597 A JP 29169597A JP H11111738 A JPH11111738 A JP H11111738A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- manufacturing
- metal plating
- sealing
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，プリント基板上に
半導体素子（チップ）を直接取り付けたＣＯＢ（Chip O
n Board）及びＣＯＢの製造方法，さらには基板に実装
する半導体素子（チップ）及び該半導体素子の製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a COB (Chip OLED) in which a semiconductor element (chip) is directly mounted on a printed circuit board.
The present invention relates to a method for manufacturing a semiconductor device (chip) mounted on a substrate and a method for manufacturing the semiconductor device.
【０００２】[0002]
【従来の技術】図１５に示したように，従来のＣＯＢ１
００を製造するにあたっては，絶縁樹脂基板１０１の上
に，接着材１０２を塗布した後，半導体素子１０３をボ
ンディングし，その後半導体素子１０３におけるパッド
１０４と，絶縁樹脂基板１０１上に形成したインナーリ
ード１０５における所定の接続部との間を接合用金属細
線１０６で配線する。その後適宜の成形金型材をはめ，
未だ硬化しておらず流動性を有する，例えば溶融状態の
封止用絶縁樹脂１０７を，当該成形金型内のキャビティ
に注入し硬化させて封止した構造を有している。2. Description of the Related Art As shown in FIG.
In manufacturing the semiconductor device 100, an adhesive 102 is applied onto the insulating resin substrate 101, and then the semiconductor element 103 is bonded. Then, the pads 104 on the semiconductor element 103 and the inner leads 105 formed on the insulating resin substrate 101 are formed. Is connected to the predetermined connection portion by a metal thin wire 106 for bonding. Then insert the appropriate mold material,
It has a structure in which a sealing insulating resin 107 that has not yet been cured and has fluidity, for example, in a molten state, is injected into a cavity in the molding die, cured, and sealed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながらこのよう
な従来のＣＯＢ１００の製造方法では，（１）絶縁樹脂
基板１０１上にインナーリード１０５やその他の配線パ
ターンを施して，プリント配線基板を製造する工程と，
（２）当該プリント配線基板に半導体素子１０３を実装
する工程とが分かれているため，工数が多くかかってい
る。しかも，溶融状態の封止用絶縁樹脂１０７の金型内
への注入によるモールディング成形時に，接合用金属細
線１０６が樹脂の注入圧力の影響で押されたり，流れて
しまい（いわゆるワイヤ流れ），接合用金属細線１０６
がインナーリード１０５から剥がれたり，断線するおそ
れがある。However, in such a conventional method of manufacturing the COB 100, there are (1) a process of manufacturing the printed wiring board by forming the inner leads 105 and other wiring patterns on the insulating resin substrate 101; ,
(2) Since the step of mounting the semiconductor element 103 on the printed wiring board is separated, the number of steps is increased. In addition, when molding is performed by injecting the molten sealing insulating resin 107 into the mold, the bonding metal thin wire 106 is pushed or flows under the influence of the injection pressure of the resin (so-called wire flow). Metal wire 106
May be peeled from the inner lead 105 or disconnected.
【０００４】本発明はかかる点に鑑みてなされたもので
あり，絶縁基板上に半導体素子を実装する工程と，プリ
ント配線基板を製造する工程とを連続して一括して行え
るＣＯＢの新規な構造，及び当該ＣＯＢの製造方法を提
供して，前記問題の解決を図ることを第１の目的として
いる。また本発明は，このようなＣＯＢの構造，及びＣ
ＯＢの製造方法を，基板に実装されるチップ自体に応用
した半導体素子，並びに半導体素子の製造工程を提供
し，もってチップの基板への実装を改善することを第２
の目的としている。The present invention has been made in view of the above points, and has a novel structure of a COB in which a process of mounting a semiconductor element on an insulating substrate and a process of manufacturing a printed wiring board can be continuously and collectively performed. It is a first object of the present invention to provide a method for producing the COB and to solve the above problem. The present invention also relates to the structure of the COB,
A second object of the present invention is to provide a semiconductor device in which the OB manufacturing method is applied to a chip itself mounted on a substrate and a process for manufacturing the semiconductor device, thereby improving the mounting of the chip on the substrate.
The purpose is.
【０００５】[0005]
【課題を解決するための手段】前記目的を達成するた
め，請求項１によれば，絶縁基板上に半導体素子が実装
され，かつ該半導体素子の外側が封止用絶縁樹脂で封止
されるＣＯＢにおいて，絶縁基板上に形成された凹部に
半導体素子が埋め込まれ，前記半導体素子の所定の接続
部以外の該半導体素子の表面は，絶縁材によって被覆さ
れ，前記絶縁材上には，前記接続部と電気的に導通して
いる導電性金属メッキによるパターンが形成され，前記
パターンの外部端子部以外は，封止用絶縁樹脂によって
外側から封止されていることを特徴とする，ＣＯＢの構
造が提供される。According to the first aspect of the present invention, a semiconductor device is mounted on an insulating substrate, and the outside of the semiconductor device is sealed with a sealing insulating resin. In the COB, a semiconductor element is embedded in a concave portion formed on an insulating substrate, and the surface of the semiconductor element other than a predetermined connection portion of the semiconductor element is covered with an insulating material. A pattern formed by conductive metal plating that is electrically connected to the portion, and a portion other than the external terminal portion of the pattern is sealed from outside with a sealing insulating resin. Is provided.
【０００６】かかる構造のＣＯＢでは，半導体素子が凹
部内に埋め込まれ，当該接続部に電気的に導通されるパ
ターンは，導電性金属メッキを利用して形成されてい
る。したがって，絶縁基板への半導体素子の実装と絶縁
基板上のプリント配線とが連続して一括に行える。なお
本願において，パターンとは，回路パターン，配線パタ
ーンを含むものである。しかも絶縁基板上のパターンと
半導体素子の所定の接続部（例えばパッド）とは，導電
性金属メッキによって電気的に接続さているので，従来
の金属細線による接続は不要となっている。したがって
ワイヤ流れの問題も生じない。In the COB having such a structure, a pattern in which a semiconductor element is embedded in a concave portion and is electrically connected to the connection portion is formed using conductive metal plating. Therefore, the mounting of the semiconductor element on the insulating substrate and the printed wiring on the insulating substrate can be performed continuously and collectively. In the present application, the pattern includes a circuit pattern and a wiring pattern. In addition, since the pattern on the insulating substrate and the predetermined connection portion (for example, a pad) of the semiconductor element are electrically connected by conductive metal plating, the conventional connection using a thin metal wire is unnecessary. Therefore, there is no problem of wire flow.
【０００７】請求項２では，このようなＣＯＢを製造す
る方法として，絶縁基板上に凹部を形成する工程と，前
記凹部に半導体素子を埋め込む工程と，前記半導体素子
の所定の接続部以外の該半導体素子の表面を，絶縁材に
よって被覆する工程と，少なくとも絶縁基板表面及び前
記接続部表面に導電性金属メッキを施す工程と，前記導
電性金属メッキ部分にパターンを形成する工程と，少な
くとも前記パターンにおける外部端子部以外の部分，並
びに半導体素子表面の絶縁材を，封止用絶縁樹脂によっ
て外側から封止する工程とを有することを特徴としてい
る。According to a second aspect of the present invention, a method of manufacturing such a COB includes a step of forming a concave portion on an insulating substrate, a step of embedding a semiconductor element in the concave portion, and a step of forming a concave portion other than a predetermined connection portion of the semiconductor element. A step of coating the surface of the semiconductor element with an insulating material, a step of applying conductive metal plating to at least the surface of the insulating substrate and the surface of the connection portion, a step of forming a pattern on the conductive metal plated portion, And sealing the insulating material on the surface of the semiconductor element from the outside with a sealing insulating resin.
【０００８】このように，この請求項２の製造方法で
は，先に半導体素子を凹部に搭載したその後，例えば全
体的に導電性金属メッキを施すことによって半導体素子
の接続部に通ずるパターンを形成するようにしているの
で，従来のように，プリント配線基板の製造，半導体素
子の実装，半導体素子とプリント配線との金属細線によ
る電気的接続，封止用絶縁樹脂による封止といったプロ
セスを採っていた製造方法に比べると，工数が減少して
おり，その結果スループットも向上している。また請求
項１のＣＯＢを効率よく製造することができる。As described above, in the manufacturing method according to the second aspect, the semiconductor element is first mounted in the concave portion, and then, for example, a conductive metal plating is applied entirely to form a pattern leading to the connection portion of the semiconductor element. As before, processes such as manufacturing of printed wiring boards, mounting of semiconductor elements, electrical connection of semiconductor elements and printed wiring by thin metal wires, and sealing with insulating resin for sealing were adopted. Compared with the manufacturing method, the man-hour is reduced, and as a result, the throughput is also improved. Further, the COB of the first aspect can be efficiently produced.
【０００９】この場合，半導体素子を埋め込んだ後，該
半導体素子の所定の接続部以外の該半導体素子の表面を
絶縁材によって被覆する工程に代えて，請求項３に記載
したように，少なくとも所定の接続部以外の表面が絶縁
材によって被覆された半導体素子を予め形成しておき，
この予め形成した半導体素子を絶縁基板の凹部に埋め込
むようにしてもよい。In this case, after embedding the semiconductor device, at least a predetermined portion of the semiconductor device is replaced with a step of covering the surface of the semiconductor device other than a predetermined connection portion with the insulating material. A semiconductor element whose surface other than the connection part is covered with an insulating material is formed in advance,
This preformed semiconductor element may be embedded in the concave portion of the insulating substrate.
【００１０】さらにこれらの製造方法において，請求項
４に記載したように，少なくとも絶縁基板表面及び前記
接続部表面に導電性金属メッキを施すにあたり，絶縁基
板裏面にも導電性金属メッキを施すようにすれば，コン
タクトスルータイプのＣＯＢを容易に製造することがで
きる。Further, in these manufacturing methods, at least when the conductive metal plating is applied to at least the surface of the insulating substrate and the surface of the connecting portion, the conductive metal plating is also applied to the back surface of the insulating substrate. Then, a contact-through type COB can be easily manufactured.
【００１１】なおこれらの各製造方法において，外部端
子部を完成させるには，封止用絶縁樹脂で封止されてい
ない部分を，パターンの導電性金属メッキにおける所定
の部分に電気的に導通するように，例えばメッキ等によ
って導電性材料で充填するようにすればよい。In each of these manufacturing methods, in order to complete the external terminal portion, a portion which is not sealed with the sealing insulating resin is electrically connected to a predetermined portion of the conductive metal plating of the pattern. Thus, the conductive material may be filled by plating, for example.
【００１２】本発明の第２の目的を達成するため，請求
項５によれば，基板に実装される半導体素子として，所
定の接続部以外の半導体素子表面が絶縁材によって被覆
され，前記絶縁材上には前記接続部と電気的に導通して
いる導電性金属メッキによるパターンが形成され，前記
パターンにおける外部端子部以外の部分，並びに半導体
素子表面の絶縁材が，封止用絶縁樹脂によって外側から
封止されていることを特徴とする，半導体素子が提供さ
れる。According to a fifth aspect of the present invention, as a semiconductor element mounted on a substrate, a surface of the semiconductor element other than a predetermined connection portion is covered with an insulating material. A pattern made of conductive metal plating that is electrically connected to the connection portion is formed on the upper portion, and portions other than the external terminal portion in the pattern and the insulating material on the surface of the semiconductor element are formed on the outside by a sealing insulating resin. And a semiconductor device characterized by being sealed from the semiconductor device.
【００１３】かかる特徴を有する半導体素子によれば，
外部端子部をハンダや導電テープで基板上の所定の接続
部と接続することによって，面積が小さくかつ高さ（厚
さ）も低くした実装をすることができる。According to the semiconductor device having such characteristics,
By connecting the external terminal portion to a predetermined connection portion on the substrate with solder or conductive tape, mounting with a small area and a low height (thickness) can be performed.
【００１４】請求項６によれば，このような構造の半導
体素子を製造する方法として，分割前のウエハ状態のと
きに，ウエハ上の各半導体素子表面の所定の接続部以外
の部分に対して絶縁材を被覆する工程と，少なくとも前
記絶縁材表面及び前記接続部表面に導電性金属メッキを
施す工程と，前記導電性金属メッキ部分にパターンを形
成する工程と，少なくとも前記パターンにおける外部端
子部以外の部分，並びに半導体素子表面の絶縁材を，封
止用絶縁樹脂によって外側から封止する工程と，前記封
止した後，前記ウエハを各半導体素子ごとに分割する工
程とを有することを特徴とする，半導体素子の製造方法
が提供される。According to a sixth aspect of the present invention, as a method of manufacturing a semiconductor device having such a structure, in a wafer state before division, a portion other than a predetermined connection portion on a surface of each semiconductor device on the wafer is formed. A step of coating an insulating material, a step of applying a conductive metal plating to at least the surface of the insulating material and the surface of the connection portion, a step of forming a pattern on the conductive metal plating portion, and at least a portion other than the external terminal portion in the pattern And a step of sealing the insulating material on the surface of the semiconductor element from the outside with an insulating resin for sealing, and a step of dividing the wafer for each semiconductor element after the sealing. A method for manufacturing a semiconductor device.
【００１５】このような製造方法によれば，ウエハ状態
のときに，請求項５の半導体素子を形成することがで
き，その後ダイシングなどによって各半導体素子ごとに
ウエハを分割することによって，請求項５の半導体素子
を製造できる。したがって，請求項５の半導体素子を効
率よく製造することが可能である。According to such a manufacturing method, the semiconductor device of claim 5 can be formed in a wafer state, and thereafter, the wafer is divided for each semiconductor device by dicing or the like, so that the semiconductor device of claim 5 can be formed. Can be manufactured. Therefore, the semiconductor device according to claim 5 can be manufactured efficiently.
【００１６】[0016]
【発明の実施の形態】以下，本発明の好ましい実施の形
態について説明する。図１は，第１の実施の形態にかか
るＣＯＢの製造方法における製造過程の途中の状態を示
しており，まず図１に示したように，絶縁樹脂基板１に
凹部としての座グリ２を形成する。次いで図２に示した
ように，半導体素子３を接着材４で固定しながら，座グ
リ２内に埋め込む。なお３ａは，半導体素子３のパッド
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. FIG. 1 shows a state in the course of the manufacturing process in the method for manufacturing a COB according to the first embodiment. First, as shown in FIG. I do. Next, as shown in FIG. 2, the semiconductor element 3 is embedded in the spot facing 2 while fixing the semiconductor element 3 with the adhesive 4. 3a is a pad of the semiconductor element 3.
【００１７】次いで図３に示したように，半導体素子３
の少なくとも，パッド３ａ以外の上面を絶縁材５で被覆
する。この場合，半導体素子３を座グリ２内に埋め込む
前に，予めパッド３ａ以外の上面を絶縁膜５で被覆し，
その後接着材４で固定しながら，この半導体素子を座グ
リ２内に埋め込むようにしてもよい。Next, as shown in FIG.
At least the top surface other than the pad 3a is covered with the insulating material 5. In this case, before embedding the semiconductor element 3 in the counterbore 2, the upper surface other than the pad 3a is previously covered with the insulating film 5,
Thereafter, the semiconductor element may be embedded in the spot facing 2 while being fixed with the adhesive 4.
【００１８】次いで図４に示したように，半導体素子３
を搭載した絶縁樹脂基板１の表面全体に例えば銅による
無電解金属メッキ６，並びにニッケルや金による電解金
属メッキ７を順次施す。これによって半導体素子３のパ
ッド３ａと，電解金属メッキ７は電気的に導通している
状態となっている。なお本実施形態では，後にコンタク
トスルーを形成する関係上，図４に示したように，絶縁
樹脂基板１の裏面全体にも無電解金属メッキ６，電解金
属メッキ７を施している。Next, as shown in FIG.
Are sequentially applied to the entire surface of the insulating resin substrate 1 on which is mounted, for example, electroless metal plating 6 made of copper and electrolytic metal plating 7 made of nickel or gold. As a result, the pad 3a of the semiconductor element 3 and the electrolytic metal plating 7 are in a state of electrical conduction. In this embodiment, the electroless metal plating 6 and the electrolytic metal plating 7 are also applied to the entire back surface of the insulating resin substrate 1 as shown in FIG.
【００１９】その後公知技術であるドライフィルムの密
着，露光，現像，エッチングを利用して，図５に示した
ように，無電解金属メッキ６，電解金属メッキ７に対し
て回路パターンの形成を実施する。これによって半導体
素子３のパッド３ａに電気的に導通している回路パター
ンが絶縁樹脂基板１上に形成されることになる。Thereafter, as shown in FIG. 5, a circuit pattern is formed on the electroless metal plating 6 and the electrolytic metal plating 7 by using a known technique of adhesion, exposure, development and etching of a dry film. I do. As a result, a circuit pattern electrically connected to the pads 3a of the semiconductor element 3 is formed on the insulating resin substrate 1.
【００２０】次いで図６に示したように，封止用絶縁樹
脂８を，半導体素子３及び絶縁樹脂基板１上に形成され
ている回路パターン，すなわちエッチングによって残置
している電解金属メッキ７上に供給して硬化させる。す
なわち封止用絶縁樹脂８によって半導体素子３及び回路
パターンを封止する。このとき，電解金属メッキ７上の
外部端子部となる部分には，必要に応じて非封止部８ａ
を残置するように封止する。Next, as shown in FIG. 6, a sealing insulating resin 8 is placed on the circuit pattern formed on the semiconductor element 3 and the insulating resin substrate 1, that is, on the electrolytic metal plating 7 left by etching. Supply and cure. That is, the semiconductor element 3 and the circuit pattern are sealed with the sealing insulating resin 8. At this time, a portion to be an external terminal on the electrolytic metal plating 7 is provided with a non-sealing portion 8a if necessary.
Is sealed.
【００２１】最後に図７に示したように，非封止部８ａ
に対して電解金属メッキ９を施すことで，下層の回路パ
ターンの電解金属メッキ７と電気的に導通する外部端子
部９ａを形成する。この場合も，既述したように，コン
タクトスルーを形成する関係上，裏面側にも同時に電解
金属メッキ９を施している。Finally, as shown in FIG. 7, the unsealed portion 8a
By applying electrolytic metal plating 9, an external terminal portion 9a electrically connected to electrolytic metal plating 7 of the lower circuit pattern is formed. Also in this case, as described above, the electrolytic metal plating 9 is simultaneously applied to the back surface side due to the formation of the contact through.
【００２２】以上のような第１の実施形態にかかるＣＯ
Ｂの製造方法によれば，まず従来と比べてプリント配線
基板の製造工程におけるソルダレジスト塗布工程，半導
体素子３の実装工程における接合用金属細線等での配線
工程が不要である。しかも前記したように，実質的にプ
リント配線基板の製造工程と半導体素子の実装工程を一
括して連続に行っているので，完成品までの工数を従来
より少なくすることが可能であり，従来よりも製造が容
易である。しかも接合用金属細線自体を使用しないか
ら，接合用金属細線での接続後に封止用絶縁樹脂で封止
する際に発生しがちであった，いわゆるワイヤ流れの問
題もおこらない。そのうえ完成品全体の厚みについて
も，接合用金属細線による配線接続に要していた厚み
分，従来よりも薄くすることが可能である。なお絶縁膜
５によって半導体素子３のパッド３ａ以外の部分は，無
電解金属メッキ６，電解金属メッキ７と絶縁されてお
り，信頼性も高いものである。The CO according to the first embodiment as described above
According to the manufacturing method B, the solder resist coating step in the manufacturing step of the printed wiring board and the wiring step using a thin metal wire for bonding in the mounting step of the semiconductor element 3 are not required as compared with the conventional method. In addition, as described above, since the manufacturing process of the printed wiring board and the mounting process of the semiconductor element are substantially and continuously performed in a lump, it is possible to reduce the man-hours required for the finished product. Are also easy to manufacture. In addition, since the bonding metal wire itself is not used, there is no problem of so-called wire flow, which tends to occur when sealing with the sealing insulating resin after connection with the bonding metal wire. In addition, the thickness of the entire finished product can be made smaller than before by the thickness required for wiring connection using the thin metal wires for bonding. The portions of the semiconductor element 3 other than the pads 3a are insulated from the electroless metal plating 6 and the electrolytic metal plating 7 by the insulating film 5, so that the reliability is high.
【００２３】次に本発明の第２の実施形態について説明
する。図８はウエハの状態で半導体素子５１が形成され
ている状態を示しており，８１，９１は同一ウエハに形
成されている他の半導体素子である。またＸは，これら
半導体素子５１，８１，９１をダイシングによって分割
するときの切溝である。この状態から，図９に示したよ
うに，半導体素子５１表面のパッド５１ａ以外の部分に
絶縁膜５２を形成する。このときもちろん他の半導体素
子８１，９１に対しても同時に絶縁膜５２の形成処理を
行っている。Next, a second embodiment of the present invention will be described. FIG. 8 shows a state in which a semiconductor element 51 is formed in a wafer state, and reference numerals 81 and 91 are other semiconductor elements formed in the same wafer. X is a kerf when these semiconductor elements 51, 81, 91 are divided by dicing. From this state, as shown in FIG. 9, an insulating film 52 is formed on a portion of the surface of the semiconductor element 51 other than the pad 51a. At this time, of course, the formation process of the insulating film 52 is simultaneously performed on the other semiconductor elements 81 and 91.
【００２４】次いで図１０に示したように，絶縁膜５２
の表面及びパッド５１ａの表面に無電解金属メッキ５
３，電解金属メッキ５４を施す。すなわちウエハの表面
全体にこれらのメッキを施すことになる。これによって
半導体素子５１のパッド５１ａと，無電解金属メッキ５
３，電解金属メッキ５４とは電気的に導通している状態
となっている。他の半導体素子８１，９１のパッド（図
示せず）についても同様に電気的に導通している。Next, as shown in FIG.
Metal plating 5 on the surface of
3. The electrolytic metal plating 54 is applied. That is, these platings are applied to the entire surface of the wafer. Thereby, the pad 51a of the semiconductor element 51 and the electroless metal plating 5
(3) It is in a state of being electrically connected to the electrolytic metal plating 54. Similarly, the pads (not shown) of the other semiconductor elements 81 and 91 are also electrically conductive.
【００２５】その後公知技術であるドライフィルムの密
着，露光，現像，エッチングを利用して，図１１に示し
たように，無電解金属メッキ５３，電解金属メッキ５４
に対して配線パターンの形成を実施する。この場合，後
で半導体素子の表面の端部となる切溝Ｘの周縁部もエッ
チングしておく。Then, using a known technique such as adhesion, exposure, development and etching of a dry film, the electroless metal plating 53 and the electrolytic metal plating 54 are used as shown in FIG.
, A wiring pattern is formed. In this case, the peripheral edge of the kerf X, which will be the end of the surface of the semiconductor element later, is also etched.
【００２６】次いで図１２に示したように，ウエハ表面
を封止用絶縁樹脂５５で封止する。このとき各半導体素
子５１，８１，９１における外部端子部５６となる部分
には，非封止部５５ａを残置し，対応する電解金属メッ
キ５４の部分を露出させておく。また同図に示したよう
に。切溝Ｘの部分も露出させておくようにしてもよい。
最後に図１３に示したように，ダイシングによって切溝
Ｘから各半導体素子５１，８１，９１に分割する。すな
わち個々の半導体素子の形状に分割する。半導体素子５
１の完成した状態を図１４に示す。Next, as shown in FIG. 12, the wafer surface is sealed with a sealing insulating resin 55. At this time, a non-sealing portion 55a is left in a portion to be the external terminal portion 56 in each of the semiconductor elements 51, 81, and 91, and a corresponding portion of the electrolytic metal plating 54 is exposed. Also as shown in the figure. The portion of the kerf X may also be exposed.
Finally, as shown in FIG. 13, the semiconductor elements 51, 81, and 91 are divided from the kerfs X by dicing. That is, it is divided into individual semiconductor element shapes. Semiconductor element 5
1 is shown in FIG.
【００２７】図１４からわかるように，この半導体素子
５１においては，パッド５１ａ以外の部分は，絶縁膜５
２によって被覆されており，その表面にパッド５１ａと
電気的に導通する無電解金属メッキ５３と電解金属メッ
キ５４によって回路パターンが形成されている。そして
外部端子部５６以外は，全て封止用絶縁樹脂５５で封止
された構造となっている。そのため，この外部端子部５
６と基板（図示せず）上の所定の接続部とをハンダや導
電テープなどによって接続することにより，面積が小さ
く，しかも高さも低い実装状態を実現することが可能で
ある。As can be seen from FIG. 14, in the semiconductor element 51, the portion other than the pad 51a is
2, and a circuit pattern is formed on the surface thereof by electroless metal plating 53 and electrolytic metal plating 54 which are electrically connected to the pads 51a. Except for the external terminal portions 56, the structure is completely sealed with the sealing insulating resin 55. Therefore, the external terminal 5
6 and a predetermined connection portion on a substrate (not shown) are connected by solder, conductive tape, or the like, so that a mounting state having a small area and a low height can be realized.
【００２８】[0028]
【発明の効果】本願請求項１〜４の発明によれば，絶縁
基板への半導体素子の実装と絶縁基板上のプリント配線
とが連続して一括に行えるので，従来よりも効率よくＣ
ＯＢを製造することができる。しかも従来の金属細線に
よる接続は不要であり，ワイヤ流れの問題も生じない。
また請求項５の発明によれば，完成した半導体素子の外
部端子部をハンダや導電テープで基板上の所定の接続部
と接続することによって，面積が小さくかつ高さ（厚
さ）も低くなった実装を実現することができる。さらに
請求項６の発明によれば，請求項５の半導体素子を効率
よく製造することが可能である。According to the first to fourth aspects of the present invention, the mounting of the semiconductor element on the insulating substrate and the printed wiring on the insulating substrate can be performed continuously and collectively, so that the efficiency of C
OB can be manufactured. In addition, the connection using the conventional thin metal wire is unnecessary, and the problem of wire flow does not occur.
According to the fifth aspect of the present invention, the external terminal portion of the completed semiconductor element is connected to a predetermined connecting portion on the substrate with solder or conductive tape, so that the area and the height (thickness) are reduced. Implementation can be realized. Further, according to the invention of claim 6, it is possible to efficiently manufacture the semiconductor device of claim 5.
【図１】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，絶縁基板に凹部
としての座グリを形成した状態を示す縦断面の説明図で
ある。FIG. 1 is an explanatory view of a longitudinal section showing a process of manufacturing a COB according to a manufacturing method according to a first embodiment of the present invention, and showing a state in which counterbores as recesses are formed in an insulating substrate.
【図２】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，座グリに半導体
素子を埋め込んだ状態を示す縦断面の説明図である。FIG. 2 is an explanatory view of a longitudinal section showing a process of manufacturing a COB according to the manufacturing method according to the first embodiment of the present invention, and showing a state in which a semiconductor element is embedded in a spot facing;
【図３】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，座グリに埋め込
んだ半導体素子の表面に絶縁膜を被覆した状態を示す縦
断面の説明図である。FIG. 3 is an explanatory view of a longitudinal section showing a process of manufacturing a COB according to the manufacturing method according to the first embodiment of the present invention, and showing a state where a surface of a semiconductor element embedded in a spot facing is covered with an insulating film; is there.
【図４】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，絶縁膜の表面に
導電性金属メッキを施した状態を示す縦断面の説明図で
ある。FIG. 4 is an explanatory view of a longitudinal section showing a process of manufacturing a COB according to the manufacturing method according to the first embodiment of the present invention, and showing a state where conductive metal plating is applied to a surface of an insulating film.
【図５】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，導電性金属メッ
キに回路パターンを形成した状態を示す縦断面及び要部
を拡大した平面の説明図である。FIG. 5 shows a process of manufacturing a COB according to the manufacturing method according to the first embodiment of the present invention, and illustrates a longitudinal section showing a state in which a circuit pattern is formed on conductive metal plating and a plan view in which main parts are enlarged. FIG.
【図６】本発明の第１の実施形態にかかる製造方法にし
たがってＣＯＢを製造する過程を示し，回路パターン及
び半導体素子の表面を封止用絶縁樹脂で封止した状態を
示す縦断面の説明図である。FIG. 6 is a longitudinal sectional view showing a process of manufacturing a COB according to the manufacturing method according to the first embodiment of the present invention, and showing a state where a surface of a circuit pattern and a semiconductor element is sealed with a sealing insulating resin. FIG.
【図７】本発明の第１の実施形態にかかる製造方法にし
たがって製造されたＣＯＢの縦断面の説明図である。FIG. 7 is an explanatory view of a longitudinal section of the COB manufactured according to the manufacturing method according to the first embodiment of the present invention.
【図８】本発明の第２の実施形態にかかる製造方法にし
たがって半導体素子を製造する過程を示し，ウエハ状態
にあるときの半導体素子の縦断面の説明図である。FIG. 8 is a view illustrating a process of manufacturing a semiconductor device according to a manufacturing method according to a second embodiment of the present invention, and is an explanatory view of a vertical section of the semiconductor device in a wafer state.
【図９】本発明の第２の実施形態にかかる製造方法にし
たがって半導体素子を製造する過程を示し，半導体素子
の表面に絶縁膜を被覆した状態を示す縦断面の説明図で
ある。FIG. 9 is an explanatory view of a longitudinal section showing a process of manufacturing a semiconductor device according to a manufacturing method according to a second embodiment of the present invention, and showing a state where a surface of the semiconductor device is covered with an insulating film.
【図１０】本発明の第２の実施形態にかかる製造方法に
したがって半導体素子を製造する過程を示し，絶縁膜の
表面に導電性金属メッキを施した状態を示す縦断面の説
明図である。FIG. 10 is a longitudinal sectional view showing a process of manufacturing a semiconductor device according to the manufacturing method according to the second embodiment of the present invention, and showing a state where conductive metal plating is applied to the surface of the insulating film.
【図１１】本発明の第２の実施形態にかかる製造方法に
したがって半導体素子を製造する過程を示し，導電性金
属メッキに配線パターンを形成した状態を示す縦断面の
説明図である。FIG. 11 is an explanatory view of a longitudinal section showing a process of manufacturing a semiconductor device according to a manufacturing method according to a second embodiment of the present invention, and showing a state in which a wiring pattern is formed on conductive metal plating.
【図１２】本発明の第２の実施形態にかかる製造方法に
したがって半導体素子を製造する過程を示し，配線パタ
ーン及び半導体素子の表面を封止用絶縁樹脂で封止した
状態を示す縦断面の説明図である。FIG. 12 is a longitudinal sectional view showing a process of manufacturing a semiconductor element according to the manufacturing method according to the second embodiment of the present invention, in which a wiring pattern and a surface of the semiconductor element are sealed with a sealing insulating resin. FIG.
【図１３】本発明の第２の実施形態にかかる製造方法に
したがって半導体素子を製造する過程を示し，各半導体
素子ごとにウエハを分割した状態を示す縦断面の説明図
である。FIG. 13 is an explanatory longitudinal sectional view showing a process of manufacturing a semiconductor device according to the manufacturing method according to the second embodiment of the present invention, and showing a state where a wafer is divided for each semiconductor device.
【図１４】本発明の第２の実施形態にかかる製造方法に
したがって製造された半導体素子の縦断面の説明図であ
る。FIG. 14 is an explanatory view of a longitudinal section of a semiconductor element manufactured according to a manufacturing method according to a second embodiment of the present invention.
【図１５】従来技術にかかるＣＯＢの縦断面の説明図で
ある。FIG. 15 is an explanatory view of a longitudinal section of a COB according to the related art.
１ 絶縁樹脂基板 ２ 座グリ ３ 半導体素子 ３ａ パッド ５ 絶縁膜 ６ 無電界金属メッキ ７ 電解金属メッキ ８ 封止用絶縁樹脂 ９ａ 外部端子部 DESCRIPTION OF SYMBOLS 1 Insulating resin substrate 2 Counterbore 3 Semiconductor element 3a Pad 5 Insulating film 6 Electroless metal plating 7 Electrolytic metal plating 8 Sealing insulating resin 9a External terminal part
Claims (6)
つ該半導体素子の外側が封止用絶縁樹脂で封止されるＣ
ＯＢにおいて，絶縁基板上に形成された凹部に半導体素
子が埋め込まれ，前記半導体素子の所定の接続部以外の
該半導体素子の表面は，絶縁材によって被覆され，前記
絶縁材上には，前記接続部と電気的に導通している導電
性金属メッキによるパターンが形成され，前記パターン
の外部端子部以外は，封止用絶縁樹脂によって外側から
封止されていることを特徴とする，ＣＯＢ。A semiconductor element mounted on an insulating substrate, and the outside of the semiconductor element is sealed with a sealing insulating resin.
In the OB, a semiconductor element is buried in a concave portion formed on an insulating substrate, and the surface of the semiconductor element other than a predetermined connection portion of the semiconductor element is covered with an insulating material. COB, characterized in that a pattern is formed by conductive metal plating that is electrically connected to the portion, and the portion other than the external terminal portion of the pattern is sealed from the outside by a sealing insulating resin.
つ該半導体素子の外側が封止用絶縁樹脂で封止されるＣ
ＯＢを製造する方法であって，絶縁基板上に凹部を形成
する工程と，前記凹部に半導体素子を埋め込む工程と，
前記半導体素子の所定の接続部以外の該半導体素子の表
面を，絶縁材によって被覆する工程と，少なくとも絶縁
基板表面及び前記接続部表面に導電性金属メッキを施す
工程と，前記導電性金属メッキ部分にパターンを形成す
る工程と，少なくとも前記パターンにおける外部端子部
以外の部分，並びに半導体素子表面の絶縁材を，封止用
絶縁樹脂によって外側から封止する工程とを有すること
を特徴とする，ＣＯＢの製造方法。2. A semiconductor device wherein a semiconductor element is mounted on an insulating substrate and the outside of the semiconductor element is sealed with a sealing insulating resin.
A method of manufacturing an OB, comprising: forming a recess on an insulating substrate; embedding a semiconductor element in the recess;
Covering a surface of the semiconductor element other than a predetermined connection portion of the semiconductor element with an insulating material, applying a conductive metal plating to at least an insulating substrate surface and the connection portion surface, Forming a pattern on the surface of the semiconductor device, and sealing the insulating material on the surface of the semiconductor element from the outside with a sealing insulating resin. Manufacturing method.
つ該半導体素子の外側が封止用絶縁樹脂で封止されるＣ
ＯＢを製造する方法であって，絶縁基板上に凹部を形成
する工程と，少なくとも所定の接続部以外の表面が絶縁
材によって被覆された半導体素子を，前記凹部に埋め込
む工程と，少なくとも前記絶縁基板表面及び前記接続部
表面に導電性金属メッキを施す工程と，前記導電性金属
メッキ部分にパターンを形成する工程と，少なくとも前
記パターンにおける外部端子部以外の部分，並びに半導
体素子表面の絶縁材を，封止用絶縁樹脂によって外側か
ら封止する工程とを有することを特徴とする，ＣＯＢの
製造方法。3. A semiconductor device wherein a semiconductor element is mounted on an insulating substrate and the outside of the semiconductor element is sealed with a sealing insulating resin.
A method of manufacturing an OB, wherein a step of forming a recess on an insulating substrate, a step of embedding a semiconductor element whose surface other than at least a predetermined connection portion is covered with an insulating material in the recess, Applying a conductive metal plating to the surface and the connection portion surface; forming a pattern on the conductive metal plating portion; and removing at least portions of the pattern other than the external terminal portions and the insulating material on the semiconductor element surface. A step of sealing from outside with a sealing insulating resin.
表面に導電性金属メッキを施すにあたり，絶縁基板裏面
に対しても導電性金属メッキを施すことを特徴とする，
請求項２又は３に記載のＣＯＢの製造方法。4. A method for applying conductive metal plating to at least the surface of an insulating substrate and the surface of the connecting portion, wherein the conductive metal plating is also applied to the back surface of the insulating substrate.
The method for producing COB according to claim 2.
所定の接続部以外の半導体素子表面が絶縁材によって被
覆され，前記絶縁材上には前記接続部と電気的に導通し
ている導電性金属メッキによるパターンが形成され，前
記パターンにおける外部端子部以外の部分，並びに半導
体素子表面の絶縁材が，封止用絶縁樹脂によって外側か
ら封止されていることを特徴とする，半導体素子。5. A semiconductor device mounted on a substrate, comprising:
The surface of the semiconductor element other than the predetermined connection portion is covered with an insulating material, and a pattern of conductive metal plating electrically connected to the connection portion is formed on the insulating material. A semiconductor element, wherein an insulating material on the surface of the semiconductor element and the surface of the semiconductor element are sealed with an insulating resin for sealing.
方法であって，分割前のウエハ状態のときに，ウエハ上
の各半導体素子表面の所定の接続部以外の部分に対して
絶縁材を被覆する工程と，少なくとも前記絶縁材表面及
び前記接続部表面に導電性金属メッキを施す工程と，前
記導電性金属メッキ部分にパターンを形成する工程と，
少なくとも前記パターンにおける外部端子部以外の部
分，並びに半導体素子表面の絶縁材を，封止用絶縁樹脂
によって外側から封止する工程と，前記封止した後，前
記ウエハを各半導体素子ごとに分割する工程とを有する
ことを特徴とする，半導体素子の製造方法。6. A method of manufacturing a semiconductor device mounted on a substrate, wherein an insulating material is applied to portions other than predetermined connection portions on the surface of each semiconductor device on the wafer in a wafer state before division. A step of coating, a step of applying a conductive metal plating to at least the surface of the insulating material and the surface of the connection portion, and a step of forming a pattern on the conductive metal plating portion.
A step of sealing at least a portion other than the external terminal portion in the pattern and an insulating material on the surface of the semiconductor element from the outside with a sealing insulating resin; and, after the sealing, dividing the wafer into individual semiconductor elements. And a method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29169597A JPH11111738A (en) | 1997-10-07 | 1997-10-07 | Cob and method for manufacturing the same, semiconductor element and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29169597A JPH11111738A (en) | 1997-10-07 | 1997-10-07 | Cob and method for manufacturing the same, semiconductor element and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11111738A true JPH11111738A (en) | 1999-04-23 |
Family
ID=17772213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29169597A Withdrawn JPH11111738A (en) | 1997-10-07 | 1997-10-07 | Cob and method for manufacturing the same, semiconductor element and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11111738A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217337A (en) * | 2000-01-31 | 2001-08-10 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2002009448A (en) * | 2000-06-23 | 2002-01-11 | Ibiden Co Ltd | Multilayer printed-wiring board and its manufacturing method |
| JP2002246507A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002246505A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Printed wiring board |
| JP2002246504A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Method for producing multilayer printed wiring board incorporating semiconductor element |
| KR100726769B1 (en) * | 2001-04-06 | 2007-06-11 | 삼성테크윈 주식회사 | The process to make cavity on a metal frame for TBGA semiconductor package by |
| US7855342B2 (en) | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US8438727B2 (en) | 2000-02-25 | 2013-05-14 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
-
1997
- 1997-10-07 JP JP29169597A patent/JPH11111738A/en not_active Withdrawn
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217337A (en) * | 2000-01-31 | 2001-08-10 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US8438727B2 (en) | 2000-02-25 | 2013-05-14 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
| JP2002009448A (en) * | 2000-06-23 | 2002-01-11 | Ibiden Co Ltd | Multilayer printed-wiring board and its manufacturing method |
| US7855342B2 (en) | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7893360B2 (en) | 2000-09-25 | 2011-02-22 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US8959756B2 (en) | 2000-09-25 | 2015-02-24 | Ibiden Co., Ltd. | Method of manufacturing a printed circuit board having an embedded electronic component |
| US9245838B2 (en) | 2000-09-25 | 2016-01-26 | Ibiden Co., Ltd. | Semiconductor element |
| JP2002246507A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002246505A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Printed wiring board |
| JP2002246504A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Method for producing multilayer printed wiring board incorporating semiconductor element |
| JP4618919B2 (en) * | 2000-12-15 | 2011-01-26 | イビデン株式会社 | Method for manufacturing multilayer printed wiring board incorporating semiconductor element |
| KR100726769B1 (en) * | 2001-04-06 | 2007-06-11 | 삼성테크윈 주식회사 | The process to make cavity on a metal frame for TBGA semiconductor package by |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20041207 |