JPH1093093A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH1093093A JPH1093093A JP24628996A JP24628996A JPH1093093A JP H1093093 A JPH1093093 A JP H1093093A JP 24628996 A JP24628996 A JP 24628996A JP 24628996 A JP24628996 A JP 24628996A JP H1093093 A JPH1093093 A JP H1093093A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor layer
- gate electrode
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 abstract description 21
- 230000001681 protective effect Effects 0.000 abstract description 12
- 230000006866 deterioration Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 84
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 58
- 229910052710 silicon Inorganic materials 0.000 description 58
- 239000010703 silicon Substances 0.000 description 58
- 239000000758 substrate Substances 0.000 description 33
- 229910052581 Si3N4 Inorganic materials 0.000 description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 22
- 238000002955 isolation Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 108090000030 T-Type Calcium Channels Proteins 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＳ型トランジ
スタを有する半導体装置およびその製造方法に関する。The present invention relates to a semiconductor device having a MOS transistor and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、コンピューターや通信機器の重要
部分には、多数のトランジスタや抵抗等を電気回路を達
成するようにむすびつけ、１チップ上に集積化して形成
した大規模集積回路（ＬＳＩ）が多用されている。この
ため、機器全体の性能は、ＬＳＩ単体の性能と大きく結
び付いている。2. Description of the Related Art In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like to achieve an electric circuit are integrated in an important part of a computer or a communication device. It is heavily used. For this reason, the performance of the entire device is greatly related to the performance of the LSI alone.
【０００３】ＬＳＩ単体の性能向上は、集積度を高める
こと、つまり、素子の微細化により実現できる。このよ
うな導体装置の高集積化、素子の微細化に伴い、近年、
素子間分離領域の面積の微細化も必要となってきてい
る。[0003] The performance of an LSI alone can be improved by increasing the degree of integration, that is, by miniaturizing elements. With the increasing integration of such conductor devices and miniaturization of elements, in recent years,
It is also necessary to reduce the area of the element isolation region.
【０００４】従来より用いられてきた素子分離方法の一
つとしてＬＯＣＯＳ法（選択酸化法）があるが、この方
法は、バーズビークと呼ばれる寸法変換差が生じてしま
うことと、分離幅の狭いところで分離用酸化膜が薄くな
ってしまうこと（フィールドシンニング効果）のため、
素子分離領域の微細化に向かない。A LOCOS method (selective oxidation method) has been used as one of the element isolation methods conventionally used. However, this method has a problem that a dimensional conversion difference called a bird's beak occurs and the separation is performed in a narrow isolation width. Because the oxide film used for thinning (field thinning effect)
Not suitable for miniaturization of element isolation regions.
【０００５】他の素子分離方法として代表的なものにト
レンチ分離法がある。この方法では、通常、半導体層に
溝を形成して、この溝に絶縁物を埋め込むことによって
素子分離を実現する。A typical element isolation method is a trench isolation method. In this method, usually, a groove is formed in a semiconductor layer, and an insulator is buried in the groove to realize element isolation.
【０００６】また、ＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉ
ｎｓｕｌａｔｏｒ）基板を用いれば、埋込み酸化膜８２
に達するトレンチ溝を形成するだけで、絶縁物を埋め込
まずに素子分離を行なうこともできる（メサ型素子分
離）。これらトレンチ分離法を用いれば、変換差が小さ
く、微細化に適した素子分離を実現できる。In addition, SOI (Silicon On I)
If an nsulator substrate is used, the buried oxide film 82
, It is possible to perform element isolation without embedding an insulator (mesa element isolation). If these trench isolation methods are used, a conversion difference is small, and element isolation suitable for miniaturization can be realized.
【０００７】図２２に、従来のＳＯＩ基板に形成され、
トレンチ分離されたＭＯＳＦＥＴのチャネル幅方向に平
行な断面図を示す。支持基板８１上には埋込み酸化膜８
２を介して凸型島状のシリコン層８３が形成されてい
る。この凸型島状のシリコン層８３にＭＯＳゲート構造
が形成されている。FIG. 22 shows a conventional SOI substrate.
FIG. 3 shows a cross-sectional view of a MOSFET separated by a trench, which is parallel to a channel width direction. A buried oxide film 8 is formed on the support substrate 81.
2, a convex island silicon layer 83 is formed. A MOS gate structure is formed on the convex island silicon layer 83.
【０００８】ここで、シリコン層８３は、ＳＯＩ層上に
酸化膜からなるエッチングマスクを形成した後、上記Ｓ
ＯＩ層をＲＩＥ（リアクティブ・イオン・エッチング）
により異方性エッチングして形成したものである。Here, after forming an etching mask made of an oxide film on the SOI layer,
RIE (reactive ion etching) on OI layer
Formed by anisotropic etching.
【０００９】ゲート絶縁膜８６は、上記エッチングマス
クやエッチング副生成物を除去した後に形成される。こ
の除去は、通常、ＨＦ（フッ酸）系のウェットエッチン
グにより行なう。このとき、埋込み酸化膜８２もエッチ
ングされ、シリコン層８３の下部に窪み８７が形成さ
れ、シリコン層８３の下部にコーナー部分８５が露出す
る。また、シリコン層８３の上部にもコーナー部分８５
が露出する。The gate insulating film 86 is formed after removing the etching mask and the etching by-product. This removal is usually performed by HF (hydrofluoric acid) wet etching. At this time, the buried oxide film 82 is also etched, so that a depression 87 is formed below the silicon layer 83, and a corner portion 85 is exposed below the silicon layer 83. Further, a corner portion 85 is also provided above the silicon layer 83.
Is exposed.
【００１０】この結果、コーナー部分８５のゲート絶縁
膜８４で電界が集中し、ゲート耐圧が劣化したり、サブ
スレショルド特性の劣化（寄生トランジスタ）等の問題
が生じる。As a result, an electric field is concentrated on the gate insulating film 84 at the corner portion 85, and problems such as deterioration of the gate breakdown voltage and deterioration of the sub-threshold characteristic (parasitic transistor) occur.
【００１１】コーナー部８５を酸化して丸めたり、コー
ナー部８５を絶縁物で覆い隠したりする提案はいくつも
なされているが、工程が複雑になる等の問題がある。ま
た、ゲート電極８４の形成工程で、窪み８７にゲート材
料が残留する。このような残留ゲート材料は、素子分離
幅が狭くなると配線間ショートの原因となる。Various proposals have been made to oxidize and round the corner portion 85 or to cover and cover the corner portion 85 with an insulator, but there are problems such as a complicated process. In the step of forming the gate electrode 84, the gate material remains in the depression 87. Such a residual gate material causes a short circuit between wirings when the element isolation width is reduced.
【００１２】一方、凸型島状のシリコン層のコーナー部
や側面部の寄生トランジスタを積極的に使う提案もある
（例えば、K. Hieda, et al "Effects of New Trench-i
solated Transistor Using Side wall Gates", IEEE Tr
ans. Electron Devices, vol.36, p.1615, (1959））。On the other hand, there is also a proposal to actively use parasitic transistors at corners and side surfaces of a convex island silicon layer (for example, K. Hieda, et al "Effects of New Trench-i").
solated Transistor Using Side wall Gates ", IEEE Tr
ans. Electron Devices, vol. 36, p. 1615, (1959)).
【００１３】これは、図２３に示すように、凸部島状の
シリコン層９３のコーナー部９９や側面部９８にもＭＯ
Ｓゲート構造を形成し、シリコン層９３を完全空乏化す
ることにより、全体として基板バイアス効果の小さいト
ランジスタを実現するというものである。As shown in FIG. 23, the corner portions 99 and the side portions 98 of the island-shaped silicon layer 93 are also formed by MO.
By forming an S-gate structure and completely depleting the silicon layer 93, a transistor with a small body effect is realized as a whole.
【００１４】なお、ここでのシリコン層９３はＳＯＩ層
をエッチングして形成したものではなく、シリコン基板
９１にトレンチ溝を掘って形成したものである。このト
レンチ溝にはトレンチ分離のために素子分離用絶縁膜９
２が埋め込まれている。Here, the silicon layer 93 is not formed by etching the SOI layer, but is formed by digging a trench in the silicon substrate 91. In this trench, an insulating film 9 for element isolation is used for trench isolation.
2 is embedded.
【００１５】しかしながら、この種のＭＯＳＦＥＴには
以下のような問題があった。すなわち、側面部９８のト
ランジスタを大きくしようとしてトレンチ溝を深くする
と、シリコン層９３の下部側壁にゲート材料９５が残留
する。このような残留したゲート材料９５は、配線間シ
ョートの原因となる。However, this type of MOSFET has the following problems. That is, when the trench is deepened to increase the size of the transistor on the side surface portion 98, the gate material 95 remains on the lower side wall of the silicon layer 93. The remaining gate material 95 causes a short circuit between wirings.
【００１６】また、ゲート電極９４となる導電膜のエッ
チング時間を長くして、シリコン層９３の下部にゲート
材料９５が残留するのを防止しようとすると、ソース・
ドレイン領域のシリコン層９３上のゲート絶縁膜９６が
除去され、ソース・ドレイン領域のシリコン層９３がエ
ッチングされて消滅する恐れがある。In order to prevent the gate material 95 from remaining under the silicon layer 93 by extending the etching time of the conductive film serving as the gate electrode 94, the
The gate insulating film 96 on the silicon layer 93 in the drain region may be removed, and the silicon layer 93 in the source / drain region may be etched and disappear.
【００１７】また、コーナー部９９のゲート耐圧確保に
は、コーナー部９９を酸化して丸める等の工夫がどうし
ても必要で、工程が複雑になる等の問題が生じる。ま
た、丸めることにより寸法変換差の増大が避けられない
という問題もある。Further, in order to ensure the gate breakdown voltage of the corner portion 99, it is absolutely necessary to devise a method such as oxidizing and rounding the corner portion 99, which causes problems such as a complicated process. In addition, there is a problem that an increase in dimensional conversion difference cannot be avoided by rounding.
【００１８】[0018]
【発明が解決しようとする課題】上述の如く、凸部島状
のシリコン層の側面にＭＯＳゲート構造が形成されたＭ
ＯＳＦＥＴは、ゲート電極の形成工程で、シリコン層の
下部に配線間ショートの原因となるゲート材料が残留す
るという問題があった。これを解決するために、シリコ
ン層の下部にゲート材料が残留しないように長時間エッ
チングを行なう方法があるが、これにはソース・ドレイ
ン領域のシリコン層がエッチングされ消滅する可能性が
あるという問題があった。As described above, an M gate having a MOS gate structure formed on a side surface of a silicon layer having a convex island shape.
The OSFET has a problem that a gate material that causes a short circuit between wirings remains under a silicon layer in a process of forming a gate electrode. To solve this, there is a method of performing etching for a long time so that the gate material does not remain under the silicon layer. However, this method has a problem that the silicon layer in the source / drain region may be etched and disappear. was there.
【００１９】また露出したコーナー部分にゲート絶縁膜
が形成されるため、ゲート耐圧の劣化やサブスレショル
ド特性の劣化が起こり、素子性能が劣化するという問題
があった。これを解決するために、コーナー部のゲート
絶縁膜を酸化して丸める方法があるが、これには工程が
複雑になる等の問題があった。Further, since the gate insulating film is formed at the exposed corners, the gate breakdown voltage and the sub-threshold characteristics are deteriorated, and there is a problem that the element performance is deteriorated. In order to solve this, there is a method of oxidizing and rounding the gate insulating film in the corner portion, but this has a problem that the process becomes complicated.
【００２０】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、上記ゲート材料の残留
問題や、上記素子特性の劣化問題の解決が可能となる半
導体層の側面にＭＯＳゲート構造が形成されたＭＯＳＦ
ＥＴを備えた半導体装置およびその製造方法を提供する
ことにある。The present invention has been made in consideration of the above circumstances, and has as its object to solve the problem of the remaining gate material and the problem of deterioration of the device characteristics on the side surface of the semiconductor layer, which can solve the above problem. MOSF with MOS gate structure formed
An object of the present invention is to provide a semiconductor device provided with ET and a method of manufacturing the same.
【００２１】[0021]
［概要］上記目的を達成するために、本発明に係る半導
体装置（請求項１）は、絶縁層上に選択的に形成された
半導体層と、この半導体層の上面に形成された被覆絶縁
膜と、前記半導体層の一つの側面から、前記被覆絶縁
膜、前記側面に対向する前記半導体層の他の側面に跨が
って形成されたゲート電極と、前記ゲート電極と前記各
側面との間にそれぞれ設けられたゲート絶縁膜と、前記
各側面の表面にそれぞれ形成され、前記ゲート電極を介
して対向する１対のソース・ドレイン領域とを備えたこ
とを特徴とする。[Summary] To achieve the above object, a semiconductor device according to the present invention (Claim 1) includes a semiconductor layer selectively formed on an insulating layer, and a covering insulating film formed on an upper surface of the semiconductor layer. A gate electrode formed so as to extend from one side surface of the semiconductor layer to the other side surface of the semiconductor layer facing the covering insulating film and the side surface; and between the gate electrode and each of the side surfaces. And a pair of source / drain regions formed on the surface of each of the side surfaces and facing each other with the gate electrode interposed therebetween.
【００２２】また、本発明に係る他の半導体装置（請求
項２）は、上記半導体装置（請求項１）において、前記
被覆絶縁膜が、前記ゲート電極の下部にあり、前記ソー
ス・ドレイン領域が形成された側面で挟まれた領域の前
記半導体層の上面に存在しないことを特徴とする。In another semiconductor device according to the present invention (claim 2), in the semiconductor device (claim 1), the covering insulating film is below the gate electrode, and the source / drain region is It does not exist on the upper surface of the semiconductor layer in a region sandwiched between the formed side surfaces.
【００２３】また、本発明に係る他の半導体装置（請求
項３）は、上記半導体装置（請求項１）において、前記
被覆絶縁膜が、前記ゲート電極よりもエッチング速度が
遅いもの、前記ゲート絶縁膜よりも厚いもの、または前
記ゲート電極よりもエッチング速度が遅くかつ前記ゲー
ト絶縁膜よりも厚いものであることを特徴とする。According to another aspect of the present invention, there is provided a semiconductor device according to the present invention, wherein the coating insulating film has a lower etching rate than the gate electrode. It is characterized by being thicker than a film, or slower in etching rate than the gate electrode and thicker than the gate insulating film.
【００２４】また、本発明に係る他の半導体装置（請求
項４）は、上記半導体装置（請求項１）において、前記
ゲート絶縁膜が設けられた部分の前記側面が（１００）
面であることを特徴とする。Further, in another semiconductor device according to the present invention (claim 4), in the semiconductor device (claim 1), the side surface of the portion provided with the gate insulating film is (100).
Surface.
【００２５】また、本発明に係る他の半導体装置（請求
項５）は、上記半導体装置（請求項１）において、前記
半導体層の厚さが、前記対向する二つの側面間の距離よ
りも大きいこと特徴とする。In another semiconductor device according to the present invention (claim 5), in the semiconductor device (claim 1), the thickness of the semiconductor layer is larger than the distance between the two opposing side surfaces. It is characterized.
【００２６】本発明に係る半導体装置の製造方法（請求
項６）は、下地が絶縁層である半導体層の全面に被覆絶
縁膜を形成する工程と、前記被覆絶縁膜と前記半導体層
との積層膜を相対する二つの側面を有する凸状にパター
ニングする工程と、前記各側面にそれぞれゲート絶縁膜
を形成する工程と、全面に導電膜を形成した後、前記被
覆絶縁膜を前記半導体層のエッチング保護膜に用いて、
前記導電膜をエッチングして前記ゲート絶縁膜に隣接し
てゲート電極を形成する工程と、前記各側面にそれぞれ
前記ゲート電極を介して対向する１対のソース・ドレイ
ン領域を形成する工程とを有することを特徴とする。According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a coating insulating film on the entire surface of a semiconductor layer whose base is an insulating layer; A step of patterning the film into a convex shape having two opposing side surfaces, a step of forming a gate insulating film on each of the side surfaces, and forming a conductive film on the entire surface, and then etching the covering insulating film by etching the semiconductor layer. Used for protective film,
Forming a gate electrode adjacent to the gate insulating film by etching the conductive film; and forming a pair of source / drain regions on each of the side surfaces facing each other via the gate electrode. It is characterized by the following.
【００２７】また、本発明に係る他の半導体装置の製造
方法（請求項７）は、上記半導体装置の製造方法（請求
項５）において、前記半導体層として絶縁膜上に形成さ
れた半導体層を用い、この半導体層に前記絶縁膜に達す
るトレンチ溝を形成するか、または前記半導体層として
半導体基板を用い、この半導体層の表面にトレンチ溝を
形成し、このトレンチ溝内に絶縁膜を埋め込むことによ
り素子分離を行なうことを特徴とする。According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the semiconductor layer formed on an insulating film is used as the semiconductor layer. Forming a trench in the semiconductor layer to reach the insulating film, or using a semiconductor substrate as the semiconductor layer, forming a trench in the surface of the semiconductor layer, and embedding the insulating film in the trench. Is used to perform element isolation.
【００２８】本発明においては、被覆絶縁膜はゲート絶
縁膜よりも誘電率が小さいことが好ましい。 ［作用］本発明によれば、例えば、半導体層の上面全面
に保護絶縁縁膜を設ければ、ゲート電極を形成する際の
エッチング工程で、上記半導体層の下部に配線間ショー
トの原因となるゲート材料が残らない程度の長時間エッ
チングしても、上記半導体層がエッチングされるのを効
果的に防止できる。したがって、本発明によれば、ソー
ス・ドレイン領域の上記半導体層のエッチングを招かず
に、上記半導体層の下部のゲート材料を除去できるよう
になる。In the present invention, the coating insulating film preferably has a smaller dielectric constant than the gate insulating film. [Operation] According to the present invention, for example, if a protective insulating film is provided on the entire upper surface of a semiconductor layer, it causes a short circuit between wirings under the semiconductor layer in an etching step when forming a gate electrode. Even if the etching is performed for a long time so that the gate material does not remain, the etching of the semiconductor layer can be effectively prevented. Therefore, according to the present invention, the gate material under the semiconductor layer can be removed without causing the etching of the semiconductor layer in the source / drain regions.
【００２９】また、この場合、上記半導体層の上部のコ
ーナー部分の露出が減るので、ゲート耐圧の劣化やサブ
スレショルド特性等の素子特性の劣化を防止できるよう
になる。Also, in this case, since the exposure of the upper corner portion of the semiconductor layer is reduced, it is possible to prevent the deterioration of the gate breakdown voltage and the deterioration of the device characteristics such as the sub-threshold characteristics.
【００３０】また、本発明（請求項４）によれば、側面
が（１００）面なので、ゲート絶縁膜と側面との界面の
界面準位密度を十分に小さくできるようになる。また、
本発明では、半導体層の対向する２側面にゲート絶縁膜
を介してゲート電極が設けられているため、二つのＭＯ
Ｓゲートにより半導体層を挟んだサンドイッチ構造、い
わゆるダブルゲートＭＯＳＦＥＴが形成されている。According to the present invention (claim 4), since the side surface is the (100) surface, the interface state density at the interface between the gate insulating film and the side surface can be sufficiently reduced. Also,
In the present invention, two gate electrodes are provided on two opposing side surfaces of the semiconductor layer with a gate insulating film interposed therebetween.
A sandwich structure in which a semiconductor layer is sandwiched between S gates, that is, a so-called double gate MOSFET is formed.
【００３１】したがって、本発明（請求項５）のよう
に、半導体層の厚さを、対向する二つの側面間の距離よ
りも大きくすれば、つまり、半導体層の幅を狭くすれ
ば、半導体層を完全空乏化できるようになるので、トラ
ンジスタの性能を向上させることができる。また、二つ
の側面間の距離を短くすることにより、トランジスタの
占有面積を小さくできるようになる。Therefore, as in the present invention (claim 5), if the thickness of the semiconductor layer is made larger than the distance between the two opposing side surfaces, that is, if the width of the semiconductor layer is made smaller, the semiconductor layer becomes thinner. Can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced.
【００３２】なお、微細化を進めることで素子領域の占
有面積が減少し、ソース・ドレイン領域とこれに接続す
る電極とのコンタクト抵抗が上昇する傾向がしばしば見
受けられるが、本発明の場合、半導体層の高さを大きく
してやることで、コンタクト抵抗の上昇を防止できるよ
うになる。It is often observed that the occupied area of the element region is reduced and the contact resistance between the source / drain region and the electrode connected thereto is increased by the miniaturization. Increasing the height of the layer can prevent an increase in contact resistance.
【００３３】[0033]
【発明の実施の形態】以下、図面を参照しながら本発明
の実施の形態（以下、実施形態という）を説明する。 （第１の実施形態）図１は本発明の第１の実施形態に係
わるＭＯＳＦＥＴを示す平面図である。また、図２は図
１のＭＯＳＦＥＴのＡ−Ａ′断面図、図３は図１のＭＯ
ＳＦＥＴのＢ−Ｂ′断面図、図４は図１のＭＯＳＦＥＴ
のＣ−Ｄ−Ｅ−Ｆ領域の断面斜視図である。なお、図１
において、２はＳＯＩ基板、３は素子分離領域、５は素
子領域を示している。Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a MOSFET according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the MOSFET of FIG.
FIG. 4 is a sectional view of the SFET taken along the line BB 'of FIG.
FIG. 3 is a cross-sectional perspective view of the CDEF region of FIG. FIG.
In the figures, 2 indicates an SOI substrate, 3 indicates an element isolation region, and 5 indicates an element region.
【００３４】図５〜図１１は、本実施形態のＭＯＳＦＥ
Ｔの製造方法を示す断面図である。これらの各図
（ａ）、図（ｂ）はそれぞれ図１のＭＯＳＦＥＴの製造
途中におけるＡ−Ａ′断面図、Ｂ−Ｂ′断面図である。FIGS. 5 to 11 show the MOSFE of this embodiment.
It is sectional drawing which shows the manufacturing method of T. These figures (a) and (b) are a sectional view taken along the line AA 'and a sectional view taken along the line BB' during the manufacture of the MOSFET of FIG. 1, respectively.
【００３５】まず、図５に示すように、支持基板９、埋
込み酸化膜８およびシリコン層１０からなるＳＯＩ基板
を用意する。このＳＯＩ基板はＳＩＭＯＸ法により形成
したものである。なお、ＳＯＩ基板は貼り合わせ法によ
り形成しても良い。また、ＳＯＳのように埋込み酸化膜
がないＳＯＩ基板を用いても良い。First, as shown in FIG. 5, an SOI substrate including a support substrate 9, a buried oxide film 8, and a silicon layer 10 is prepared. This SOI substrate is formed by the SIMOX method. Note that the SOI substrate may be formed by a bonding method. Further, an SOI substrate having no buried oxide film such as SOS may be used.
【００３６】次に図６に示すように、熱酸化によって厚
さ１０ｎｍのバッファ酸化膜１２をシリコン層１０の表
面に形成する。このとき、必要であれば、ＭＯＳＦＥＴ
のしきい値電圧を調整するためのイオン注入を行なう。Next, as shown in FIG. 6, a buffer oxide film 12 having a thickness of 10 nm is formed on the surface of the silicon layer 10 by thermal oxidation. At this time, if necessary, MOSFET
Is performed to adjust the threshold voltage of.
【００３７】なお、図には一つのＭＯＳＦＥＴしか示し
てないが、ＣＭＯＳのようにｎ型チャネルＭＯＳＦＥ
Ｔ、ｐ型チャネルＭＯＳＦＥＴを同時に形成する場合で
あれば、上記イオン注入は、ｎ型チャネルＭＯＳＦＥ
Ｔ、ｐ型チャネルＭＯＳＦＥＴそれぞれ別々に行なう。Although only one MOSFET is shown in the figure, an n-channel MOSFET such as a CMOS is used.
If the T and p-type channel MOSFETs are formed simultaneously, the ion implantation is performed by using the n-type channel MOSFET.
T and p-type channel MOSFETs are performed separately.
【００３８】その後、同図に示すように、バッファ酸化
膜１２上に保護絶縁膜（エッチングマスク）として例え
ば厚さ１５０ｎｍのシリコン窒化膜１３を形成する。保
護絶縁膜としては後工程で形成するゲート絶縁膜よりも
誘電率の低いものであることが好ましい。Thereafter, as shown in FIG. 1, a silicon nitride film 13 having a thickness of, for example, 150 nm is formed on the buffer oxide film 12 as a protective insulating film (etching mask). The protective insulating film preferably has a lower dielectric constant than a gate insulating film formed in a later step.
【００３９】次に図７に示すように、ＥＢ描画やフォト
リソグラフィによるパターンニングによりシリコン窒化
膜１３上にフォトレジストパターン１５を形成した後、
このフォトレジストパターン１５をマスクとして、埋込
み酸化膜８の表面が露出するまで、シリコン窒化膜１
３、バッファ酸化膜１２、シリコン層１０をＲＩＥ法に
より連続的にエッチングし、シリコン窒化膜１３、バッ
ファ酸化膜１２、シリコン層１０を島状に加工する。Next, as shown in FIG. 7, after forming a photoresist pattern 15 on the silicon nitride film 13 by patterning by EB drawing or photolithography,
Using the photoresist pattern 15 as a mask, the silicon nitride film 1 is exposed until the surface of the buried oxide film 8 is exposed.
3. The buffer oxide film 12 and the silicon layer 10 are continuously etched by RIE, and the silicon nitride film 13, the buffer oxide film 12, and the silicon layer 10 are processed into an island shape.
【００４０】基本的に、これだけの工程で、素子分離工
程は終了であり、非常に工程数が少なく容易で、半導体
装置の量産に有利である。しかも、変換差のないトレン
チ分離なので、微細化に適している。Basically, the element isolation step is completed with only these steps, and the number of steps is very small and easy, which is advantageous for mass production of semiconductor devices. Moreover, since the trench is separated without any conversion difference, it is suitable for miniaturization.
【００４１】次に図８に示すように、フォトレジストパ
ターン１５を除去した後、熱酸化によってシリコン層１
０の側面に厚さ６ｎｍのゲート絶縁膜１１を形成する。
次に同図に示すように、ゲート電極４となる厚さ１５０
ｎｍのポリシリコン膜、厚さ１００ｎｍのタングステン
シリサイド膜（またはタングステン膜）をそれぞれＬＰ
ＣＶＤ法とスパッタ法で積層形成する。Next, as shown in FIG. 8, after removing the photoresist pattern 15, the silicon layer 1 is thermally oxidized.
A gate insulating film 11 having a thickness of 6 nm is formed on the side surface of the zero.
Next, as shown in FIG.
a 100 nm thick polysilicon film and a 100 nm thick tungsten silicide film (or tungsten film)
The layers are formed by a CVD method and a sputtering method.
【００４２】上記ポリシリコン膜には成膜後にイオン注
入により不純物をドーピングしておく。なお、ポリシリ
コン膜の代わりにＴｉＮ膜などの金属膜を用いた場合に
は、前記（同ページで述べた）しきい値電圧調整用のイ
オン注入は不要である。The polysilicon film is doped with impurities by ion implantation after film formation. In the case where a metal film such as a TiN film is used instead of the polysilicon film, the ion implantation for adjusting the threshold voltage (described on the same page) is unnecessary.
【００４３】この図８の工程では、シリコン窒化膜１
３、バッファ酸化膜１２を除去せずに残すので、ゲート
絶縁膜１１の形成直前に、シリコン窒化膜１３、バッフ
ァ酸化膜１２を除去するためのＣＤＥ（ケミカル・ドラ
イ・エッチング）やＨＦ系溶液によるエッチング処理は
行なわれない。In the process of FIG. 8, the silicon nitride film 1
3. Since the buffer oxide film 12 is left without being removed, a CDE (chemical dry etching) or HF-based solution for removing the silicon nitride film 13 and the buffer oxide film 12 immediately before the gate insulating film 11 is formed. No etching is performed.
【００４４】したがって、図２２に示したような窪み８
７は形成され難く、シリコン層１０（素子領域）のエッ
ジ部の上下コーナー部分は露出しない。これにより、ゲ
ート絶縁膜１１の耐圧が向上し、サブスレショルド特性
のハンプは抑えられる構造になる。Therefore, the depression 8 as shown in FIG.
7 is difficult to be formed, and the upper and lower corner portions of the edge portion of the silicon layer 10 (element region) are not exposed. Thereby, the withstand voltage of the gate insulating film 11 is improved, and a hump of the sub-threshold characteristic is suppressed.
【００４５】また、シリコンの結晶面方位を調節して、
島状のシリコン層１０の側面の少なくとも一部に（１０
０）面が露出するようにすると、シリコン層１０の側面
に界面準位が少ないゲート絶縁膜１１を形成できるよう
になる。Further, by adjusting the crystal plane orientation of silicon,
At least a part of the side surface of the island-shaped silicon layer 10 has (10
When the 0) plane is exposed, the gate insulating film 11 having a small interface state can be formed on the side surface of the silicon layer 10.
【００４６】次に図９に示すように、ＥＢ描画やフォト
リソグラフィーによるパターンニングによりフォトレジ
ストパターン（不図示）をマスクとしてとＲＩＥ法によ
り上記ポリシリコン膜およびタングステンシリサイド膜
（またはタングステン膜）の積層膜をエッチングして、
ゲート電極４を形成する。この後、上記フォトレジスト
パターンを除去し、ゲート電極４の表面を軽く酸化して
薄い（５ｎｍ程度）酸化膜（不図示）を形成する。Next, as shown in FIG. 9, the polysilicon film and the tungsten silicide film (or tungsten film) are laminated by RIE using a photoresist pattern (not shown) as a mask by patterning by EB drawing or photolithography. Etch the film,
The gate electrode 4 is formed. Thereafter, the photoresist pattern is removed, and the surface of the gate electrode 4 is lightly oxidized to form a thin (about 5 nm) oxide film (not shown).
【００４７】ここで、ゲート電極４となる上記積層膜の
下には、埋込み酸化膜８または保護絶縁膜（エッチング
マスク）のシリコン窒化膜１３が存在する。したがっ
て、シリコン層１０の下部側面にゲート材料が残留しな
いように、上記積層膜を長時間エッチングしても、ソー
ス・ドレイン領域のシリコン層１０がエッチングされる
ことはない。Here, a buried oxide film 8 or a silicon nitride film 13 as a protective insulating film (etching mask) exists below the above-mentioned laminated film to be the gate electrode 4. Therefore, even if the laminated film is etched for a long time so that the gate material does not remain on the lower side surface of the silicon layer 10, the silicon layer 10 in the source / drain region is not etched.
【００４８】また、ゲート材料の残留をさらに完全に防
ぐには、トレンチ角度にわずかなテーパー（鉛直面に対
して７度以下。深いところでトレンチの幅が狭くなる方
向）を与えることが有効である。In order to further completely prevent the gate material from remaining, it is effective to give the trench angle a slight taper (7 degrees or less with respect to the vertical plane, a direction in which the width of the trench becomes narrow at a deep position). .
【００４９】次に図１０に示すように、ソース・ドレイ
ン拡散層を形成するために、不純物イオン１４を斜めに
イオン注入した後、アニールを行なう。ここで、ｎ型チ
ャネルＭＯＳＦＥＴの場合であればＡｓ、ｐ型チャネル
ＭＯＳＦＥＴの場合であればＢＦ2 を１×１０15／ｃｍ
2 程度のドーズ量でイオン注入する。Next, as shown in FIG. 10, in order to form a source / drain diffusion layer, annealing is performed after ion implantation of the impurity ions 14 at an angle. Here, As is used for an n-type channel MOSFET, and BF 2 is set to 1 × 10 15 / cm for a p-type channel MOSFET.
Ion implantation is performed at a dose of about 2 .
【００５０】次に図１１に示すように、全面に層間絶縁
膜７を形成する。この後、通常のＭＯＳＦＥＴの製造工
程に従う。すなわち、図１〜図４に示すようにゲート、
ソース・ドレインの各領域にコンタクトホール１G ，１
SDを開孔し、ゲート電極４、２つのソース・ドレイン拡
散層にそれぞれ接続する引出し配線１６，１７，１８を
形成する。Next, as shown in FIG. 11, an interlayer insulating film 7 is formed on the entire surface. Thereafter, the normal MOSFET manufacturing process is followed. That is, as shown in FIGS.
Contact holes 1 G , 1
The SD is opened, and lead wirings 16, 17, and 18 connected to the gate electrode 4 and the two source / drain diffusion layers are formed.
【００５１】なお、微細化を進めることで素子領域の占
有面積が減少しても、シリコン層１０の厚さを大きくす
ることで（トレンチ溝の深さを大きくすることで）、一
方のソース・ドレイン層と引出し配線１７とのコンタク
ト部分の寄生抵抗および他方のソース・ドレイン層と引
出し配線１８とのコンタクト部分の寄生抵抗を低減で
き、コンタクト抵抗の上昇を防止できるようになる。Even if the area occupied by the element region is reduced by miniaturization, by increasing the thickness of the silicon layer 10 (by increasing the depth of the trench groove), The parasitic resistance at the contact portion between the drain layer and the lead-out wiring 17 and the parasitic resistance at the contact portion between the other source / drain layer and the lead-out wiring 18 can be reduced, and an increase in the contact resistance can be prevented.
【００５２】なお、図４におけて引出し配線１７，１８
は省略されている。この引出し配線１７，１８は、シリ
コン層１０の側面でもコンタクトをとることができるの
で、コンタクト面積が増える。Note that, in FIG.
Has been omitted. Since the lead wirings 17 and 18 can make contact with the side surface of the silicon layer 10, the contact area increases.
【００５３】また、本実施形態では、半導体層１０の対
向する２側面にゲート絶縁膜１１を介してゲート電極４
が設けられているため、二つのＭＯＳゲートにより半導
体層３を挟んだサンドイッチ構造、いわゆるダブルゲー
トＭＯＳＦＥＴが形成されている。In the present embodiment, the gate electrode 4 is formed on two opposing side surfaces of the semiconductor layer 10 via the gate insulating film 11.
Is provided, a sandwich structure in which the semiconductor layer 3 is sandwiched between two MOS gates, that is, a so-called double-gate MOSFET is formed.
【００５４】したがって、半導体層１０の厚さｄを、対
向する二つの側面間の距離よりも大きくすれば、つま
り、半導体層１０の幅ｗを狭くすれば（例えば４０ｎｍ
程度）、半導体層１０を完全空乏化できるようになるの
で、トランジスタの性能を向上させることができる。ま
た、二つの側面間の距離を短くすることにより、トラン
ジスタの占有面積を小さくできるようになる。 （第２の実施形態）本実施形態のＭＯＳＦＥＴの特徴
は、第１の実施形態のＭＯＳＦＥＴにおいて、ソース・
ドレイン拡散層が形成された側面間のシリコン層１０上
の保護絶縁膜としてのシリコン窒化膜１３を除去した構
成になっていることになる。Therefore, if the thickness d of the semiconductor layer 10 is made larger than the distance between the two opposing side surfaces, that is, if the width w of the semiconductor layer 10 is made smaller (for example, 40 nm).
Degree), the semiconductor layer 10 can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced. (Second Embodiment) The feature of the MOSFET of this embodiment is that the MOSFET of the first embodiment has
This means that the silicon nitride film 13 as a protective insulating film on the silicon layer 10 between the side surfaces where the drain diffusion layer is formed is removed.
【００５５】このような構成のＭＯＳＦＥＴは、例え
ば、図９の工程でゲートを加工した後、ソース・ドレイ
ン拡散層が形成される側面間のシリコン層１０上のシリ
コン窒化膜１３をＲＩＥ（反応性イオンエッチング）に
より除去し、図１０に示すように、ソース・ドレイン拡
散層形成のためのイオン注入を行なう。シリコン窒化膜
がないため、半導体層１０にイオン注入しやすい。次い
で図１１に示すように全面に層間絶縁膜７を形成する。
この後は、第１の実施形態と同様の通常のＭＯＳＦＥＴ
の製造工程に従う。 （第３の実施形態）図１２〜図２０は、第３の実施形態
に係わるＭＯＳＦＥＴの製造方法を示す断面図である。
平面図は図１のそれに示すものと同じであり、各図
（ａ）、図（ｂ）はそれぞれ図１の平面図のＡ−Ａ′断
面図、Ｂ−Ｂ′断面図に相当する。In the MOSFET having such a structure, for example, after processing the gate in the step of FIG. 9, the silicon nitride film 13 on the silicon layer 10 between the side surfaces where the source / drain diffusion layers are formed is subjected to RIE (reactive Then, as shown in FIG. 10, ion implantation for forming source / drain diffusion layers is performed. Since there is no silicon nitride film, ions can be easily implanted into the semiconductor layer 10. Next, as shown in FIG. 11, an interlayer insulating film 7 is formed on the entire surface.
Thereafter, a normal MOSFET similar to that of the first embodiment is used.
According to the manufacturing process. (Third Embodiment) FIGS. 12 to 20 are sectional views showing a method for manufacturing a MOSFET according to a third embodiment.
The plan view is the same as that shown in FIG. 1, and each figure (a) and FIG. (B) correspond to the AA 'sectional view and the BB' sectional view of the plan view in FIG. 1, respectively.
【００５６】本実施形態は、ＳＯＩ基板ではなく通常の
シリコン基板を用いた例である。すなわち、本実施形態
は、本発明に係る実施形態ではないが、本発明と同様な
効果が得られる。This embodiment is an example using a normal silicon substrate instead of an SOI substrate. That is, the present embodiment is not an embodiment according to the present invention, but has the same effects as the present invention.
【００５７】まず、図１２に示すように、シリコン基板
２１を用意し、次いで熱酸化によって厚さ１０ｎｍのバ
ッファ酸化膜２２をシリコン基板２１の表面に形成す
る。このとき、必要であれば、ＭＯＳＦＥＴのしきい値
電圧を調整するためのイオン注入を行なう。First, as shown in FIG. 12, a silicon substrate 21 is prepared, and then a buffer oxide film 22 having a thickness of 10 nm is formed on the surface of the silicon substrate 21 by thermal oxidation. At this time, if necessary, ion implantation for adjusting the threshold voltage of the MOSFET is performed.
【００５８】なお、図には一つのＭＯＳＦＥＴしか示し
てないが、ＣＭＯＳのようにｎ型チャネルＭＯＳＦＥ
Ｔ、ｐ型チャネルＭＯＳＦＥＴを同時に形成する場合で
あれば、上記イオン注入は、ｎ型チャネルＭＯＳＦＥ
Ｔ、ｐ型チャネルＭＯＳＦＥＴそえぞれ別々に行なう。Although only one MOSFET is shown in the figure, an n-type channel MOSFET such as a CMOS is used.
If the T and p-type channel MOSFETs are formed simultaneously, the ion implantation is performed by using the n-type channel MOSFET.
T and p-type channel MOSFETs are performed separately.
【００５９】その後、同図に示すように、バッファ酸化
膜２２上に保護絶縁膜（エッチングマスク）として例え
ば厚さ１５０ｎｍのシリコン窒化膜２３を形成する。次
に図１３に示すように、ＥＢ描画やフォトリソグラフィ
によるパターンニングによりシリコン窒化膜２３上にフ
ォトレジストパターン２４を形成した後、このフォトレ
ジストパターン２４をマスクとして、シリコン窒化膜２
３、バッファ酸化膜２２、シリコン基板２１をＲＩＥ法
により連続的にエッチングし、例えば深さ２５０ｎｍの
トレンチ溝を形成し、シリコン窒化膜２３、バッファ酸
化膜２２、シリコン基板２１を島状に加工する。Thereafter, as shown in FIG. 6, a silicon nitride film 23 having a thickness of, for example, 150 nm is formed on the buffer oxide film 22 as a protective insulating film (etching mask). Next, as shown in FIG. 13, after forming a photoresist pattern 24 on the silicon nitride film 23 by patterning by EB drawing or photolithography, the silicon nitride film 2 is formed using the photoresist pattern 24 as a mask.
3. The buffer oxide film 22 and the silicon substrate 21 are continuously etched by the RIE method to form a trench having a depth of, for example, 250 nm, and the silicon nitride film 23, the buffer oxide film 22, and the silicon substrate 21 are processed into an island shape. .
【００６０】次に図１４に示すように、フォトレジスト
パターン２４を除去した後、全面に厚さ３５０ｎｍの酸
化膜２５を形成した後、図１５に示すように、シリコン
窒化膜２３をストッパに用いて、酸化膜２５の表面をＣ
ＭＰ（chemical mechanicalpolish）法により研磨して
平坦化する。Next, as shown in FIG. 14, after removing the photoresist pattern 24, an oxide film 25 having a thickness of 350 nm is formed on the entire surface. Then, as shown in FIG. 15, the silicon nitride film 23 is used as a stopper. The surface of the oxide film 25
It is polished and flattened by an MP (chemical mechanical polish) method.
【００６１】次に図１６に示すように、シリコン窒化膜
２３がエッチングされず、酸化膜２５が選択的にエッチ
ングされる条件のもとで、全面をＲＩＥ法によりエッチ
ングすることにより、酸化膜２５をトレンチ溝の底部に
１２５ｎｍだけ残置させる。Next, as shown in FIG. 16, the entire surface is etched by the RIE method under the condition that the silicon nitride film 23 is not etched and the oxide film 25 is selectively etched. Is left at the bottom of the trench groove by 125 nm.
【００６２】基本的に、以上の工程で、素子分離工程は
終了する。絶縁膜埋め込みトレンチ分離なので、変換差
が小さく、微細化に適している。次に図１７に示すよう
に、熱酸化によって島状のシリコン基板２１の側面に厚
さ６ｎｍのゲート絶縁膜２６を形成した後、ゲート電極
２７となる厚さ１５０ｎｍのポリシリコン膜、厚さ１０
０ｎｍのタングステンシリサイド膜（またはタングステ
ン膜）をそれぞれＬＰＣＶＤ法とスパッタ法で積層形成
する。Basically, the element isolation step ends with the above steps. Since the insulating film is buried in the trench, the conversion difference is small, which is suitable for miniaturization. Next, as shown in FIG. 17, a 6-nm-thick gate insulating film 26 is formed on the side surface of the island-shaped silicon substrate 21 by thermal oxidation, and then a 150-nm-thick polysilicon film serving as the gate electrode 27 is formed.
A 0-nm-thick tungsten silicide film (or tungsten film) is formed by lamination using the LPCVD method and the sputtering method, respectively.
【００６３】上記ポリシリコン膜には成膜後にイオン注
入により不純物をドーピングしておく。なお、ポリシリ
コン膜の代わりにＴｉＮ膜などの金属膜を用いた場合に
は、前ページで述べたしきい値電圧調整用のイオン注入
は不要である。After the film formation, the polysilicon film is doped with impurities by ion implantation. When a metal film such as a TiN film is used instead of the polysilicon film, the ion implantation for adjusting the threshold voltage described on the previous page is unnecessary.
【００６４】この図１７の工程では、シリコン窒化膜２
３、バッファ酸化膜２２を除去せずに残すので、ゲート
絶縁膜２６の形成直前に、シリコン窒化膜２３、バッフ
ァ酸化膜２２を除去するためのＣＤＥ（ケミカル・ドラ
イ・エッチング）やＨＦ系溶液によるエッチング処理は
行なわれない。In the step of FIG. 17, the silicon nitride film 2
3. Since the buffer oxide film 22 is left without being removed, a CDE (chemical dry etching) or HF-based solution for removing the silicon nitride film 23 and the buffer oxide film 22 immediately before forming the gate insulating film 26 is used. No etching is performed.
【００６５】したがって、図２２に示したような窪み８
７は形成され難く、島状のシリコン基板２１（素子領
域）のエッジ部の上部コーナー部分は露出しない。これ
により、ゲート絶縁膜２６の耐圧が向上し、サブスレシ
ョルド特性のハンプは抑えられる構造になる。Therefore, the depression 8 as shown in FIG.
7 is difficult to be formed, and the upper corner portion of the edge portion of the island-shaped silicon substrate 21 (element region) is not exposed. As a result, the breakdown voltage of the gate insulating film 26 is improved, and a hump of the sub-threshold characteristic is suppressed.
【００６６】また、シリコンの結晶面方位を調節して、
島状のシリコン基板２１の側面の少なくとも一部に（１
００）面が露出するようにすると、シリコン基板２１の
側面に界面準位が少ないゲート絶縁膜２６を形成できる
ようになる。Further, by adjusting the crystal plane orientation of silicon,
At least a part of the side surface of the island-shaped silicon substrate 21 has (1
When the (00) plane is exposed, the gate insulating film 26 with a small interface state can be formed on the side surface of the silicon substrate 21.
【００６７】次に図１８に示すように、ＥＢ描画やフォ
トリソグラフィーによるパターンニングによりフォトレ
ジストパターン（不図示）をマスクとしてとＲＩＥ法に
より上記ポリシリコン膜およびタングステンシリサイド
膜（またはタングステン膜）の積層膜をエッチングし
て、ゲート電極２７を形成する。この後、上記フォトレ
ジストパターンを除去し、ゲート電極２７の表面を軽く
酸化して薄い（５ｎｍ程度）酸化膜（不図示）を形成す
る。Next, as shown in FIG. 18, the polysilicon film and the tungsten silicide film (or tungsten film) are laminated by RIE using a photoresist pattern (not shown) as a mask by patterning by EB drawing or photolithography. The gate electrode 27 is formed by etching the film. Thereafter, the photoresist pattern is removed, and the surface of the gate electrode 27 is lightly oxidized to form a thin (about 5 nm) oxide film (not shown).
【００６８】ここで、ゲート電極２７となる上記積層膜
の下には、酸化膜２５または保護絶縁膜（エッチングマ
スク）のシリコン窒化膜２３が存在する。したがって、
島状のシリコン基板２１の下部側面にゲート材料が残留
しないように、上記積層膜を長時間エッチングしても、
ソース・ドレイン領域の島状のシリコン基板２１がエッ
チングされることはない。Here, an oxide film 25 or a silicon nitride film 23 as a protective insulating film (etching mask) exists under the above-mentioned laminated film to be the gate electrode 27. Therefore,
Even if the laminated film is etched for a long time so that the gate material does not remain on the lower side surface of the island-shaped silicon substrate 21,
The island-shaped silicon substrate 21 in the source / drain region is not etched.
【００６９】また、ゲート材料の残留をさらに完全に防
ぐには、トレンチ角度にわずかなテーパー（鉛直面に対
して７度以下。深いところでトレンチの幅が狭くなる方
向）を与えることが有効である。In order to further completely prevent the gate material from remaining, it is effective to give the trench angle a slight taper (7 degrees or less with respect to the vertical plane, a direction in which the width of the trench becomes smaller at a deeper angle). .
【００７０】次に図１９に示すように、二つのソース・
ドレイン拡散層を形成するために、不純物イオン２８を
斜めにイオン注入した後、アニールを行なう。ここで、
ｎ型チャネルＭＯＳＦＥＴの場合であればＡｓ、ｐ型チ
ャネルＭＯＳＦＥＴの場合であればＢＦ2 を１×１０15
／ｃｍ2 程度のドーズ量でイオン注入する。Next, as shown in FIG.
In order to form a drain diffusion layer, annealing is performed after oblique ion implantation of impurity ions 28. here,
As for an n-channel MOSFET, BF 2 is 1 × 10 15 for a p-channel MOSFET.
Ions are implanted at a dose of about / cm 2 .
【００７１】次に図２０に示すように、全面に層間絶縁
膜２９を形成した後、通常のＭＯＳＦＥＴの製造工程に
従って、ゲート、ソース、ドレインの各領域にコンタク
トホール３０を開孔し、ゲート電極２７、二つのソース
・ドレイン拡散層にそれぞれ接続する引出し配線３１，
３２，３３を形成する。Next, as shown in FIG. 20, after an interlayer insulating film 29 is formed on the entire surface, contact holes 30 are opened in each of the gate, source and drain regions in accordance with a normal MOSFET manufacturing process. 27, extraction wirings 31 respectively connected to the two source / drain diffusion layers,
32 and 33 are formed.
【００７２】なお、微細化を進めることで素子領域の占
有面積が減少しても、前述したＳＯＩ基板に形成した場
合と同様に島状のシリコン基板２１の厚さを大きくする
ことで（トレンチ溝の深さを大きくすることで）、ソー
ス・ドレイン層と引出し配線３２，３３とのコンタクト
部分の寄生抵抗を低減でき、コンタクト抵抗の上昇を防
止できるようになる。これは島状シリコンの側面でもコ
ンタクトを取れるようになるからである。Even if the occupied area of the element region is reduced by miniaturization, by increasing the thickness of the island-shaped silicon substrate 21 (trench groove) as in the case of forming the SOI substrate described above. In this case, the parasitic resistance at the contact portions between the source / drain layers and the lead wirings 32 and 33 can be reduced, and the contact resistance can be prevented from increasing. This is because a contact can be made even on the side surface of the island-shaped silicon.
【００７３】また、本実施形態では、島状のシリコン基
板２１の対向する２側面にゲート絶縁膜２６を介してゲ
ート電極２７が設けられているため、二つのＭＯＳゲー
トにより島状のシリコン基板２１を挟んだサンドイッチ
構造、いわゆるダブルゲートＭＯＳＦＥＴが形成されて
いる。In this embodiment, since the gate electrode 27 is provided on the two opposing side surfaces of the island-shaped silicon substrate 21 via the gate insulating film 26, the island-shaped silicon substrate 21 is formed by two MOS gates. , A so-called double-gate MOSFET is formed.
【００７４】したがって、島状のシリコン基板２１の厚
さｄを、対向する二つの側面間の距離よりも大きくすれ
ば、つまり、島状のシリコン基板２１の幅ｗを例えば４
０ｎｍ程度に狭くすれば、島状のシリコン基板２１を完
全空乏化できるようになるので、トランジスタの性能を
向上させることができる。また、二つの側面間の距離を
短くすることにより、トランジスタの占有面積を小さく
できるようになる。Therefore, if the thickness d of the island-shaped silicon substrate 21 is made larger than the distance between the two opposing side surfaces, that is, the width w of the island-shaped silicon
If the thickness is reduced to about 0 nm, the island-shaped silicon substrate 21 can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced.
【００７５】なお、本発明は上述した実施形態に限定さ
れるものではない。例えば、微細化を進めて島状のシリ
コン層やシリコン基板（素子領域）の幅が狭くなり、ソ
ース・ドレインのコンタクトホールの位置合わせが困難
になった場合には、図２１に示すように、ソース・ドレ
インのコンタクトホール１SDの直径Ｄ１を素子領域の幅
Ｄ２よりも大きくすれば、コンタクトホール１SDの位置
合わせずれによるコンタクト抵抗の上昇を防止できるよ
うになる。The present invention is not limited to the embodiment described above. For example, in the case where the width of an island-shaped silicon layer or a silicon substrate (element region) is narrowed due to the progress of miniaturization, and it becomes difficult to align the source / drain contact holes, as shown in FIG. if greater than the width D2 of the source-drain element region a contact hole 1 SD diameter D1 of, it becomes possible to prevent an increase in contact resistance due to misalignment of the contact hole 1 SD.
【００７６】また、上記実施形態では、保護絶縁膜とし
てシリコン窒化膜を用いたが他の絶縁膜を用いても良
い。要は、保護絶縁膜として、ゲート電極よりもエッチ
ング速度が遅いもの、ゲート絶縁膜よりも厚いもの、ま
たはゲート電極よりもエッチング速度が遅くかつゲート
絶縁膜よりも厚いものを用いることにより、ゲート電極
となる導電膜を長時間エッチングする際にソース・ドレ
イン領域上のシリコン層がエッチングされ消滅されない
ようにすれば良い。その他、本発明の要旨を逸脱しない
範囲で、種々変形して実施できる。In the above embodiment, the silicon nitride film is used as the protective insulating film, but another insulating film may be used. The point is that as the protective insulating film, a material having a lower etching rate than the gate electrode, a material having a thickness larger than the gate insulating film, or a material having a lower etching rate than the gate electrode and having a thickness larger than the gate insulating film is used. It is sufficient to prevent the silicon layer on the source / drain region from being etched and lost when the conductive film to be etched is etched for a long time. In addition, various modifications can be made without departing from the scope of the present invention.
【００７７】[0077]
【発明の効果】以上詳述したように本発明によれば、半
導体層の側面にＭＯＳゲート構造が形成されたＭＯＳＦ
ＥＴを備えた半導体装置において、ゲート材料の残留問
題や、素子特性の劣化問題を解決できるようになる。As described above in detail, according to the present invention, a MOSF in which a MOS gate structure is formed on a side surface of a semiconductor layer.
In a semiconductor device provided with ET, the problem of remaining gate material and the problem of deterioration of element characteristics can be solved.
【図１】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す平面図FIG. 1 is a MOSFET according to a first embodiment of the present invention.
A plan view showing
【図２】図１のＭＯＳＦＥＴのＡ−Ａ′断面図FIG. 2 is a cross-sectional view of the MOSFET of FIG.
【図３】図１のＭＯＳＦＥＴのＢ−Ｂ′断面図FIG. 3 is a cross-sectional view of the MOSFET of FIG.
【図４】図１のＭＯＳＦＥＴのＣ−Ｄ−Ｅ−Ｆ領域の断
面斜視図4 is a sectional perspective view of a CDEF region of the MOSFET of FIG. 1;
【図５】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す断面図FIG. 5 is a MOSFET according to the first embodiment of the present invention.
Cross section showing
【図６】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す断面図FIG. 6 is a MOSFET according to the first embodiment of the present invention.
Cross section showing
【図７】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す断面図FIG. 7 is a MOSFET according to the first embodiment of the present invention.
Cross section showing
【図８】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す断面図FIG. 8 is a MOSFET according to the first embodiment of the present invention.
Cross section showing
【図９】本発明の第１の実施形態に係わるＭＯＳＦＥＴ
を示す断面図FIG. 9 is a MOSFET according to the first embodiment of the present invention.
Cross section showing
【図１０】本発明の第１の実施形態に係わるＭＯＳＦＥ
Ｔを示す断面図FIG. 10 is a diagram showing a MOSFE according to the first embodiment of the present invention;
Sectional view showing T
【図１１】本発明の第１の実施形態に係わるＭＯＳＦＥ
Ｔを示す断面図FIG. 11 is a diagram showing a MOSFE according to the first embodiment of the present invention;
Sectional view showing T
【図１２】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 12 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図１３】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 13 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図１４】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 14 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図１５】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 15 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図１６】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 16 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T
【図１７】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 17 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T
【図１８】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 18 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T
【図１９】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 19 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図２０】本発明の第３の実施形態に係わるＭＯＳＦＥ
Ｔの製造方法を示す断面図FIG. 20 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T
【図２１】コンタクトホールの位置合わせずれを防止す
る方法を説明するための平面図FIG. 21 is a plan view for explaining a method for preventing misalignment of a contact hole.
【図２２】従来のＭＯＳＦＥＴを示す断面図FIG. 22 is a sectional view showing a conventional MOSFET.
【図２３】従来のＭＯＳＦＥＴを示す断面斜視図FIG. 23 is a sectional perspective view showing a conventional MOSFET.
１G ，１SD…コンタクトホール ２…ＳＯＩ基板 ３…素子分離領域 ４…ゲート電極 ５…素子領域 ７…層間絶縁膜 ８…埋込み酸化膜 ９…支持基板 １０…シリコン層 １１…ゲート絶縁膜 １２…バッファ酸化膜 １３…シリコン窒化膜（保護絶縁膜） １４…不純物イオン １５…フォトレジストパターン １６…引出し配線 １７…引出し配線 １８…引出し配線 ２１…シリコン基板 ２２…バッファ酸化膜 ２３…シリコン窒化膜（保護絶縁膜） ２４…フォトレジストパターン ２５…酸化膜 ２６…ゲート絶縁膜 ２７…ゲート電極 ２８…不純物イオン ２９…層間絶縁膜 ３０G ，３０SD…コンタクトホール ３１…引出し配線 ３２…引出し配線 ３３…引出し配線DESCRIPTION OF SYMBOLS 1 G , 1 SD ... Contact hole 2 ... SOI substrate 3 ... Element isolation region 4 ... Gate electrode 5 ... Element region 7 ... Interlayer insulating film 8 ... Buried oxide film 9 ... Support substrate 10 ... Silicon layer 11 ... Gate insulating film 12 ... Buffer oxide film 13 Silicon nitride film (protective insulating film) 14 Impurity ions 15 Photoresist pattern 16 Lead wiring 17 Lead wiring 18 Lead wiring 21 Silicon substrate 22 Buffer oxide film 23 Silicon nitride film (protection) 24 ... photoresist pattern 25 ... oxide film 26 ... gate insulating film 27 ... gate electrode 28 ... impurity ions 29 ... interlayer insulating film 30G , 30SD ... contact hole 31 ... lead-out wiring 32 ... lead-out wiring 33 ... lead-out wiring
Claims (7)
側面に対向する前記半導体層の他の側面に跨がって形成
されたゲート電極と、 前記ゲート電極と前記各側面との間にそれぞれ設けられ
たゲート絶縁膜と、 前記各側面の表面にそれぞれ形成され、前記ゲート電極
を介して対向する１対のソース・ドレイン領域とを具備
してなることを特徴とする半導体装置。A semiconductor layer formed on an insulating layer; a coating insulating film formed on an upper surface of the semiconductor layer; and a coating insulating film formed on one side of the semiconductor layer. A gate electrode formed over the other side surface of the semiconductor layer facing the gate electrode; a gate insulating film provided between the gate electrode and each of the side surfaces; and a gate electrode formed on the surface of each of the side surfaces, respectively. And a pair of source / drain regions facing each other with the gate electrode interposed therebetween.
にあり、前記ソース・ドレイン領域が形成された側面で
挟まれた領域の前記半導体層の上面に存在しないことを
特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein said coating insulating film is located below said gate electrode and does not exist on an upper surface of said semiconductor layer in a region sandwiched between side surfaces on which said source / drain regions are formed. 2. The semiconductor device according to 1.
エッチング速度が遅いもの、前記ゲート絶縁膜よりも厚
いもの、または前記ゲート電極よりもエッチング速度が
遅くかつ前記ゲート絶縁膜よりも厚いものであることを
特徴とする請求項１に記載の半導体装置。3. The coating insulating film has a lower etching rate than the gate electrode, is thicker than the gate insulating film, or has a lower etching rate than the gate electrode and is thicker than the gate insulating film. The semiconductor device according to claim 1, wherein
側面は（１００）面であることを特徴とする請求項１に
記載の半導体装置。4. The semiconductor device according to claim 1, wherein said side surface of a portion where said gate insulating film is provided is a (100) plane.
の側面間の距離よりも大きいことを特徴とする請求項１
に記載の半導体装置。5. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is larger than a distance between the two opposing side surfaces.
3. The semiconductor device according to claim 1.
絶縁膜を形成する工程と、 前記被覆絶縁膜と前記半導体層との積層膜を相対する二
つの側面を有するように凸状にパターニングする工程
と、 前記各側面にそれぞれゲート絶縁膜を形成する工程と、 全面に導電膜を形成した後、前記被覆絶縁膜を前記半導
体層のエッチング保護膜に用いて、前記導電膜をエッチ
ングして前記ゲート絶縁膜に隣接してゲート電極を形成
する工程と、 前記各側面にそれぞれ前記ゲート電極を介して対向する
１対のソース・ドレイン領域を形成する工程とを有する
ことを特徴とする半導体装置の製造方法。6. A step of forming a coating insulating film over the entire surface of a semiconductor layer whose underlying layer is an insulating layer; Patterning; forming a gate insulating film on each of the side surfaces; forming a conductive film on the entire surface; and etching the conductive film using the coating insulating film as an etching protection film for the semiconductor layer. Forming a pair of source / drain regions on the respective side surfaces via the gate electrode by forming a gate electrode adjacent to the gate insulating film. Device manufacturing method.
面間の前記半導体層上の前記被覆絶縁膜を除去して、前
記被覆絶縁膜を前記ゲート電極の下部に選択的に残置さ
せることを特徴とする請求項６に記載の半導体装置の製
造方法。7. The semiconductor device according to claim 7, wherein the insulating film on the semiconductor layer between the side surfaces on which the source / drain regions are formed is removed, and the insulating film is selectively left under the gate electrode. The method for manufacturing a semiconductor device according to claim 6.
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|---|---|---|---|
| JP24628996A JP3607431B2 (en) | 1996-09-18 | 1996-09-18 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24628996A JP3607431B2 (en) | 1996-09-18 | 1996-09-18 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1093093A true JPH1093093A (en) | 1998-04-10 |
| JP3607431B2 JP3607431B2 (en) | 2005-01-05 |
Family
ID=17146340
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24628996A Expired - Fee Related JP3607431B2 (en) | 1996-09-18 | 1996-09-18 | Semiconductor device and manufacturing method thereof |
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