JPH1079570A - Method of electrically jointing electronic element chip to wiring circuit - Google Patents
Method of electrically jointing electronic element chip to wiring circuitInfo
- Publication number
- JPH1079570A JPH1079570A JP26902896A JP26902896A JPH1079570A JP H1079570 A JPH1079570 A JP H1079570A JP 26902896 A JP26902896 A JP 26902896A JP 26902896 A JP26902896 A JP 26902896A JP H1079570 A JPH1079570 A JP H1079570A
- Authority
- JP
- Japan
- Prior art keywords
- projections
- terminal
- needle
- aluminum
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、端子がファインピッチ
に形成された半導体チップ、コンデンサーチップ等の電
子素子チップを微細配線回路に低コストで信頼性高く、
電気的に接合できるようにする接合方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a low-cost, highly reliable electronic element chip such as a semiconductor chip or a capacitor chip having terminals formed at a fine pitch.
The present invention relates to a bonding method that enables electrical bonding.
【0002】[0002]
【従来の技術】従来より、半導体チップを配線回路に接
合するいわゆるチップマウント方法としては、ワイヤー
ボンディングおよび半田を使ったフリップチップ法が広
く用いられている。前者の方法では、半導体チップが配
線基板に銀ペーストなどで固定され、チップの入出力端
子と配線回路とが金線あるいはアルミニウム線等のワイ
ヤーで接続されているが、この様な半導体チップの入出
力端子は通常アルミニウム系金属から形成されているた
めに次のような問題が発生している。2. Description of the Related Art Conventionally, as a so-called chip mounting method for bonding a semiconductor chip to a wiring circuit, a flip chip method using wire bonding and solder has been widely used. In the former method, the semiconductor chip is fixed to the wiring board with silver paste or the like, and the input / output terminals of the chip and the wiring circuit are connected by a wire such as a gold wire or an aluminum wire. Since the output terminal is usually formed of an aluminum-based metal, the following problem occurs.
【0003】すなわち、ワイヤーボンディング法では、 入出力端子を構成しているアルミニウム系金属と金ワ
イヤーとの接合部分に金属間化合物が生成し、接合信頼
性が低下するという問題。 ALパッド/AL線、ALパッド/Au線間の耐蝕
性、密着強度が経時的に劣化する問題。これは、LSI
をレジンで封止したとき、樹脂の中の水分、樹脂を通し
て水分の拡散、樹脂の中の塩素分等が耐蝕性を劣化させ
るといわれている。これを防ぐためには、セラミックパ
ッケージに真空封入する必要があり、これは極めて高価
である。また、ワイヤーボンディング法そのものにも次
のような問題がある。 ワイヤーボンディングでは近年の高密度実装化に対応
することが困難となっている。 ボンディングワイヤーとする金ワイヤーが高価なため
に、接合コストが非常に高くなるという問題。また、 入出力端子と配線回路との接続距離が長くなるため
に、信号の応答速度が遅くなるという問題。That is, in the wire bonding method, an intermetallic compound is generated at a joint portion between an aluminum-based metal and a gold wire forming an input / output terminal, and the joint reliability is reduced. The problem that the corrosion resistance and adhesion strength between the AL pad / AL line and the AL pad / Au line deteriorates with time. This is LSI
Is sealed with a resin, it is said that moisture in the resin, diffusion of moisture through the resin, chlorine content in the resin, and the like deteriorate the corrosion resistance. In order to prevent this, it is necessary to vacuum-enclose in a ceramic package, which is extremely expensive. In addition, the wire bonding method itself has the following problem. With wire bonding, it is difficult to cope with recent high-density mounting. The problem that the bonding cost is extremely high because the gold wire used as the bonding wire is expensive. In addition, since the connection distance between the input / output terminal and the wiring circuit is increased, the response speed of the signal is reduced.
【0004】そこで、チップマウント方法としては、金
ワイヤーを使用することなく、ダイレクトに基板に半導
体チップを半田で接合するフリップチップも採用される
ようになっているが、この方法では、半導体チップの入
出力端子上に、チタン、ニッケル、銅、クロム等のバリ
アメタル層をスパッタ法あるいは蒸着法等の真空法で形
成することが必須不可欠になっている。これは半導体チ
ップの入出力端子を形成しているアルミニウム系金属は
本来表面に酸化膜が存在するために、そのままで、半田
付け性が悪く、導通不良を起こしやすいためである。し
かしながら、半導体チップの入出力端子に真空法でバリ
アメタル層を形成するための製造工程は複雑でしかも製
造設備も大掛かりとなり、また生産性も低くなるので、
フリップチップは結果的には実装コストが高くなるとい
う問題が起こっている。以上のような経緯に鑑み、本発
明者らは従来のバリアメタル層にかえてメッキ法でN
i,あるいはNiの上にさらにAuを順次形成する方法
を開発し、すでに出願(特開平7−263493号)し
ている。この方法はアルミニウム入出力端子部表面に下
地メッキとしてPdを浸漬メッキして無電解Niメッキ
する方法、あるいは無電解Ni後、無電解Auメッキす
る方法で、これにより従来のバリアメタル層のコストを
大巾に低減できたが、湿式メッキを使用するための後処
理の問題、および更なるコスト低減の問題は依然として
残されている。Therefore, as a chip mounting method, a flip chip in which a semiconductor chip is directly joined to a substrate by soldering without using a gold wire has been adopted. It is indispensable to form a barrier metal layer of titanium, nickel, copper, chromium or the like on the input / output terminal by a vacuum method such as a sputtering method or a vapor deposition method. This is because the aluminum-based metal forming the input / output terminals of the semiconductor chip originally has an oxide film on its surface, and as such, has poor solderability and easily causes poor conduction. However, the manufacturing process for forming the barrier metal layer on the input / output terminals of the semiconductor chip by a vacuum method is complicated, the manufacturing equipment is large, and the productivity is low.
The flip chip has a problem that the mounting cost is increased as a result. In view of the circumstances described above, the present inventors have replaced the conventional barrier metal layer with a N2 plating method.
A method for sequentially forming Au on i or Ni has been developed, and an application has been filed (Japanese Patent Application Laid-Open No. Hei 7-263493). This method is a method in which Pd is immersion-plated as a base plating on the surface of an aluminum input / output terminal to perform electroless Ni plating, or a method in which electroless Ni is applied and then electroless Au plating, thereby reducing the cost of a conventional barrier metal layer. Although significant reductions have been made, the problems of post-treatment for using wet plating and further cost reduction remain.
【0005】[0005]
【発明が解決する課題】本発明は以上の状況に鑑みてな
されたもので、後処理不要で、アルミニウム端子の上に
直接接合することができる強度に優れ、高電流を流すこ
とができる新規な接合方法を提供せんとするものであ
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and requires no post-treatment, has a high strength which can be directly bonded onto an aluminum terminal, and has a novel ability to flow a high current. It does not provide a joining method.
【0006】[0006]
【問題を解決するための手段】本発明者らは、鋭意研究
を行った結果次の知見を得た。すなわち、 1.電子素子チップの金属端子と配線回路をで電気的に
接合するに際して、該導電性フィラーとして多数の針状
突起を有する硬質金属の粉末を使用し、接合時加圧して
該針状突起で端子金属表面の酸化膜を破壊して端子金属
に埋入させると、高電流を流すことができる強固な電気
的接合が得られることを見出だした。そして、 2.上記硬質金属は、Ni系金属からなる粉末に金メッ
キされた構造で、該Ni系金属粉末は多数の針状突起を
有する構造のものが最も好ましいこと。 3.上記金属端子は軟質金属端子の場合最も効果的であ
ること。 4.そして軟質金属端子がアルミニウム端子の場合最も
効果的であること。 以上の知見を得た。本発明は以上の知見をもとになされ
たものである。Means for Solving the Problems The present inventors have conducted intensive studies and obtained the following findings. That is, 1. When electrically connecting the metal terminal of the electronic element chip and the wiring circuit by using a hard metal powder having a large number of needle-shaped protrusions as the conductive filler, pressurizing at the time of bonding and applying a metal to the terminal metal with the needle-shaped protrusions. It has been found that when the oxide film on the surface is destroyed and buried in the terminal metal, a strong electric junction through which a high current can flow can be obtained. And 2. Preferably, the hard metal has a structure in which a Ni-based metal powder is plated with gold, and the Ni-based metal powder has a structure having a large number of needle-like projections. 3. The above metal terminals are most effective in the case of soft metal terminals. 4. And it is most effective when the soft metal terminal is an aluminum terminal. The above findings were obtained. The present invention has been made based on the above findings.
【0007】[0007]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。図1は、本発明の代表的な
態様を説明した模式図である。本発明で使用する導電性
フィラーは数ミクロン〜数十ミクロンの大きさの針状突
起を持った粒子であるが、図1では説明を分かりやすく
するために針状突起を大きく拡大して表現した。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic diagram illustrating a typical embodiment of the present invention. The conductive filler used in the present invention is a particle having needle-like protrusions having a size of several microns to several tens of microns, but in FIG. 1, the needle-like protrusions are greatly enlarged for easy understanding of the description. .
【0008】すなわち、図1は、電子素子チップ(LS
I)1のアルミニウムからなる電極端子2と配線基板3
の銅回路4を電気的に接続する方法を模式的に説明した
図である。接続は導電性フィラーが分散した異方性導電
性接着剤で接続する。フィラーには多数の針状突起を有
する硬質金属粒子5を使用する。電子素子チップ1のア
ルミニウムからなる電極端子2と配線基板3の銅回路4
の間に導電性フィラーが分散した異方性導電性接着剤6
を挟み両方を重ね合わせて加圧しながら加熱して接着剤
を硬化させる。加圧によって、突起がアルミニウム端子
表面の酸化膜7を破壊してアルミニウム地金の中にささ
ってめり込む。また銅回路にもささってめり込む。アル
ミニウム地金、銅回路に食い込んだ突起は接着剤の硬化
と相俟ってアルミニウム端子と銅回路を強度的にも電気
的にも強固に接続することとなる。電気的には数アンペ
アの電流を許容できる接続が達成される。なおここで突
起は銅回路にささってめり込むことは必須条件ではな
い。銅回路表面は、通常図のように金メッキされている
ので突起が金メッキ面に接触するだけで十分な電気的接
続が得られる。FIG. 1 shows an electronic device chip (LS)
I) The electrode terminal 2 made of aluminum and the wiring board 3
FIG. 4 is a diagram schematically illustrating a method of electrically connecting the copper circuits 4 of FIG. The connection is made with an anisotropic conductive adhesive in which a conductive filler is dispersed. Hard metal particles 5 having a large number of needle-like projections are used as the filler. Electrode terminal 2 made of aluminum of electronic element chip 1 and copper circuit 4 of wiring board 3
Anisotropic conductive adhesive 6 having a conductive filler dispersed therein
The adhesive is cured by heating while pressurizing the adhesive. Due to the pressure, the projections break the oxide film 7 on the surface of the aluminum terminal and dig into the aluminum base metal. In addition, I dig into the copper circuit. The protrusions that have penetrated the aluminum base metal and copper circuit, together with the hardening of the adhesive, firmly connect the aluminum terminal and the copper circuit both in terms of strength and electrical. Electrically, a connection that can tolerate a current of several amps is achieved. Here, it is not an essential condition that the protrusion be pressed into the copper circuit. Since the copper circuit surface is usually gold-plated as shown in the figure, a sufficient electrical connection can be obtained only by contacting the protrusion with the gold-plated surface.
【0009】フィラーには多数の針状突起を有する硬質
金属の粒子を使用することが必須であるが、硬質金属と
してはNi、Ni合金、Co.Co合金が好ましく、表
面にAuメッキしたものが最も好適である。なおフィラ
ーはすべて針状突起粒子であってもよいが、直径1ミク
ロン以下の通常の導電性粒子8も1〜40%の範囲で適
宜混合した方がより好適である。As the filler, it is essential to use hard metal particles having a large number of needle-like projections. Ni, Ni alloy, Co. A Co alloy is preferable, and an Au plating on the surface is most preferable. All the fillers may be needle-shaped projection particles, but it is more preferable that the usual conductive particles 8 having a diameter of 1 micron or less are appropriately mixed in a range of 1 to 40%.
【0010】異方性導電性接着剤の接着剤成分は、エポ
キシ系樹脂を使用したものが最も好ましい。樹脂の硬化
形態には特別な制約はなく、加熱硬化、紫外線硬化、あ
るいは熱・紫外線併用型等、通常の加熱形態はすべて適
宜選択使用できる。接着剤成分としてエポキシ系樹脂を
主成分とする加熱硬化型樹脂を使用する場合、加熱温度
と時間は、150℃で80〜120秒、200℃で20
〜30秒となる。The adhesive component of the anisotropic conductive adhesive most preferably uses an epoxy resin. There is no particular limitation on the curing form of the resin, and any ordinary heating form such as heat curing, ultraviolet curing, or combined use of heat and ultraviolet can be appropriately selected and used. When a thermosetting resin mainly composed of an epoxy resin is used as an adhesive component, the heating temperature and time are 80 to 120 seconds at 150 ° C and 20 at 200 ° C.
3030 seconds.
【0011】圧力は、フィラーの突起ですくなくともア
ルミニウムの酸化膜を破壊しアルミニウム地金に圧入さ
せる必要があり、概ね2kg/cm2以上の圧力が必要
である。下限値未満ではアルミニウムの酸化膜の破壊と
アルミニウム地金への突起の圧入が十分でない。上限値
を越える圧力はLSIの破壊、基板の変形を招く。As for the pressure, it is necessary to break at least the aluminum oxide film at the protrusions of the filler and press-fit the aluminum ingot, and a pressure of about 2 kg / cm 2 or more is required. If it is less than the lower limit, the destruction of the aluminum oxide film and the press-fitting of the projection into the aluminum base metal are not sufficient. A pressure exceeding the upper limit causes LSI destruction and substrate deformation.
【0012】なお、ここで使用する半導体チップ1自体
にはとくに制限はなく、表面にパッシベーション膜(図
では、PIQ.SIN+PSG)が形成されている一般
的な半導体チップを使用することができ、とくに電極端
子がファインピッチに形成されているものも使用でき
る。端子材料はアルミニウム、アルミニウム合金に限定
されるものではない。その他の銅、銀、金等の軟質金属
金属全般を使用できるが、これらの中でとりわけアルミ
ニウム系金属からなるものを好ましく使用できる。The semiconductor chip 1 used here is not particularly limited, and a general semiconductor chip having a passivation film (in the figure, PIQ.SIN + PSG) formed on its surface can be used. Those having electrode terminals formed at a fine pitch can also be used. The terminal material is not limited to aluminum and aluminum alloy. Other soft metal metals such as copper, silver, and gold can be used in general, and among them, those made of aluminum-based metal can be preferably used.
【0013】 なお、本発明で接合するチップの端子は
半導体チップの入出力端子に限られない。本発明の方法
は、ICチップ、トランジスター、ダイオードチップ等
の半導体チップのほか、コンデンサーチップ、抵抗チッ
プ、等種々のチップの信号の入出力端子電源端子、グラ
ンドアース端子等の接合に適用することができる。The terminals of the chip to be joined in the present invention are not limited to the input / output terminals of the semiconductor chip. The method of the present invention can be applied to bonding of semiconductor chips such as IC chips, transistors and diode chips, as well as input / output terminals of various chips such as capacitor chips and resistance chips, power supply terminals, and ground earth terminals. it can.
【0014】[0014]
【実施例】本発明を実施例に基づいて詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on embodiments.
【0015】実施例1 Al端子がついた多数のLSIチップがのったシリコン
ウエハー全面に、針状突起を有するNi系金属粉末に金
メッキした導電フィラー(3μm以上の大きさ)を含有
する異方性導電性接着剤(ハイソール(株)製)を塗布
し、90℃で3時間加熱してBステージ硬化させた。次
にこれを各自の大きさにダイシングした後、リジッドな
ガラス配線基板の電極基板と位置あわせして重ね合わ
せ、圧力2kg/cm2で加圧して端子表面のアルミニ
ウム酸化膜を破壊してフィラーを端子地金に突き立てて
侵入させ、温度100℃で熱硬化させて両者を接合して
基板に実装を行った。密着強度、シェアー強度も強かっ
た。端子には2Aの電流を流しても異常に発熱すること
はなかった。低抵抗の電気的接合が得られたことが確認
できた。Example 1 Anisotropically containing a conductive filler (having a size of 3 μm or more) gold-plated on a Ni-based metal powder having needle-like protrusions over the entire surface of a silicon wafer on which a large number of LSI chips having Al terminals are mounted. A conductive adhesive (manufactured by Hysole Co., Ltd.) was applied and heated at 90 ° C. for 3 hours to cure the B stage. Next, after dicing this into its own size, it is positioned and overlapped with the electrode substrate of the rigid glass wiring substrate, and pressurized at a pressure of 2 kg / cm 2 to break the aluminum oxide film on the terminal surface and remove the filler. They were pushed into the terminal base metal and penetrated, thermally cured at a temperature of 100 ° C., joined together, and mounted on a substrate. Adhesion strength and shear strength were also strong. No abnormal heat generation occurred even when a current of 2 A was applied to the terminals. It was confirmed that a low-resistance electrical junction was obtained.
【0016】[0016]
【発明の効果】以上詳記したように本発明は,電子素子
チップのアルミニウム端子の表面を直接配線回路に低抵
抗、高強度で、しかも低コストで接合できる特徴を有
し、半導体実装技術の信頼性の向上と実装コストの低減
に多大な貢献をなすものである。As described above in detail, the present invention has a feature that the surface of an aluminum terminal of an electronic element chip can be directly joined to a wiring circuit with low resistance, high strength and at low cost. It greatly contributes to improving reliability and reducing mounting costs.
【図1】 図1は、本発明の説明図であり、異方性導電
性接着剤の針状突起を持つフィラーがアルミニウム端子
の酸化膜を破壊して地金の中に侵入する状況を説明した
図である。BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an explanatory view of the present invention, illustrating a situation in which a filler having needle-like projections of an anisotropic conductive adhesive breaks an oxide film of an aluminum terminal and penetrates a base metal. FIG.
1 電子素子チップ(LSI) 2 電極端子 3 配線基板 4 銅回路 5 硬質金属粒子 6 異方性導
電性接着剤 7 酸化膜 8 導電性粒
子DESCRIPTION OF SYMBOLS 1 Electronic element chip (LSI) 2 Electrode terminal 3 Wiring board 4 Copper circuit 5 Hard metal particle 6 Anisotropic conductive adhesive 7 Oxide film 8 Conductive particle
Claims (4)
電性フィラーが分散した異方性導電性接着剤で電気的に
接合するに際して、該導電性フィラーとして多数の針状
突起を有する硬質金属の粉末を使用し、接合時加圧して
該針状突起で端子金属表面の酸化膜を破壊して端子金属
に埋入させることを特徴とする電子素子チップと配線回
路の電気的接合方法。When a metal terminal of an electronic element chip and a wiring circuit are electrically joined with an anisotropic conductive adhesive in which a conductive filler is dispersed, a hard metal having a large number of needle-like projections as the conductive filler. A method for electrically connecting an electronic element chip and a wiring circuit, comprising using the powder of (1) and applying pressure at the time of bonding to break an oxide film on the surface of the terminal metal with the needle-like projections and bury the oxide film in the terminal metal.
に金メッキされた構造で、該Ni系金属粉末は多数の針
状突起を有する構造である請求項1に記載の電気的接合
方法。2. The electrical joining method according to claim 1, wherein said hard metal has a structure in which a powder of Ni-based metal is plated with gold, and said Ni-based metal powder has a structure having a large number of needle-like projections.
1あるいは2に記載の電気的接合方法。3. The method according to claim 1, wherein the metal terminal is a soft metal terminal.
3に記載の電気的接合方法。4. The method according to claim 3, wherein the soft metal is aluminum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26902896A JPH1079570A (en) | 1996-09-03 | 1996-09-03 | Method of electrically jointing electronic element chip to wiring circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26902896A JPH1079570A (en) | 1996-09-03 | 1996-09-03 | Method of electrically jointing electronic element chip to wiring circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1079570A true JPH1079570A (en) | 1998-03-24 |
Family
ID=17466678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26902896A Pending JPH1079570A (en) | 1996-09-03 | 1996-09-03 | Method of electrically jointing electronic element chip to wiring circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1079570A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009099708A (en) * | 2007-10-16 | 2009-05-07 | Osaka Univ | Connecting method for terminal, bonding structure for terminal, and resin for connection |
US9914855B2 (en) | 2012-08-14 | 2018-03-13 | Henkel Ag & Co. Kgaa | Curable compositions comprising composite particles |
-
1996
- 1996-09-03 JP JP26902896A patent/JPH1079570A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009099708A (en) * | 2007-10-16 | 2009-05-07 | Osaka Univ | Connecting method for terminal, bonding structure for terminal, and resin for connection |
US9914855B2 (en) | 2012-08-14 | 2018-03-13 | Henkel Ag & Co. Kgaa | Curable compositions comprising composite particles |
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