JPH1064855A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH1064855A JPH1064855A JP21485696A JP21485696A JPH1064855A JP H1064855 A JPH1064855 A JP H1064855A JP 21485696 A JP21485696 A JP 21485696A JP 21485696 A JP21485696 A JP 21485696A JP H1064855 A JPH1064855 A JP H1064855A
- Authority
- JP
- Japan
- Prior art keywords
- cutting
- semiconductor substrate
- semiconductor device
- groove
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関するものであり、特に半導体装置の切削方法に使
用されるものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for cutting a semiconductor device.
【０００２】[0002]
【従来の技術】ウェハ上に形成された多数の半導体装置
を個々に切り離す場合、ブレードダイサーを用いて分離
領域を切削する切削工程で行っている。従来から用いら
れているブレードダイサーの刃先９の断面図を図３に示
す。この様な形状をした刃先９のブレードダイサーでウ
ェハを切削する方法の従来例を、図４（ａ）〜（ｃ）を
用いて説明する。2. Description of the Related Art A large number of semiconductor devices formed on a wafer are individually cut in a cutting step of cutting a separation region using a blade dicer. FIG. 3 is a cross-sectional view of a blade edge 9 of a conventionally used blade dicer. A conventional example of a method of cutting a wafer with a blade dicer having a blade edge 9 having such a shape will be described with reference to FIGS.
【０００３】図４（ａ）は、半導体装置が形成されてい
る、切削する前のウェハの断面図を示すものである。ウ
ェハにはその半導体基板１の表面に半導体装置を構成す
る物質膜３の領域と、物質膜３でカバーされていない半
導体装置間のスクラブライン５という分離領域がある。FIG. 4A is a cross-sectional view of a wafer on which a semiconductor device has been formed before cutting. The wafer has a region of the material film 3 constituting the semiconductor device on the surface of the semiconductor substrate 1 and a separation region called a scrub line 5 between the semiconductor devices not covered by the material film 3.
【０００４】まず第１の切削工程にて、このスクライブ
ライン５の中央部（幅Ｗ７）を、図３で示した刃先９を
備えたブレードダイサーで、半導体基板１の表面から深
さＤ７まで切削する（図４（ｂ））。First, in a first cutting step, a central portion (width W7) of the scribe line 5 is cut from a surface of the semiconductor substrate 1 to a depth D7 by a blade dicer having a cutting edge 9 shown in FIG. (FIG. 4B).
【０００５】次に第１の切削工程にて切削された溝の中
央付近（幅Ｗ９）を、第２の切削工程にて同じブレード
ダイサーで半導体基板１の裏面まで切削し半導体装置を
分離する（図４（ｃ））。この第２の切削工程における
切削深さをＤ９とする。Next, the vicinity of the center of the groove (width W9) cut in the first cutting step is cut to the back surface of the semiconductor substrate 1 by the same blade dicer in the second cutting step to separate the semiconductor device ( FIG. 4 (c)). The cutting depth in this second cutting step is D9.
【０００６】従来の切削方法の特徴は、Ｗ７よりもＷ９
を小さくし、Ｄ７をウェハ厚の半分程度にするところで
あり、デュアルダイシングと呼ばれている。このよう
に、図３で示した刃先９を備えたブレードダイサーでス
クライブライン５をデュアルダイシングすることによっ
て、切削刃の歪による切削端の切り欠けの発生を防ごう
としている。[0006] The feature of the conventional cutting method is that W9 is better than W7.
Is reduced, and D7 is reduced to about half of the wafer thickness, which is called dual dicing. As described above, by performing dual dicing of the scribe line 5 with the blade dicer having the cutting edge 9 shown in FIG. 3, it is attempted to prevent the cut end from being cut out due to the distortion of the cutting blade.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
切削方法では、第１及び第２の切削工程で切削された切
削端にある、略９０°の角度を持ったコーナー１１に各
切削工程でのストレスが加わり、結晶の欠け（以下、チ
ップ欠けと呼ぶ）が生じやすいという欠点がある。この
チップ欠けの一部は半導体装置の表面に付着して傷を付
けるなど、信頼性の問題を引き起こす可能性がある。特
に、ＣＣＤのようなイメージセンサにおいては、このチ
ップ欠けの付着が発生すると画質劣化を生じる。However, according to the conventional cutting method, a corner 11 having an angle of about 90 ° at a cutting end cut in the first and second cutting steps is formed in each cutting step. There is a drawback that stress is applied and crystal chipping (hereinafter referred to as chip chipping) is likely to occur. A part of the chip chip may cause a reliability problem such as being attached to the surface of the semiconductor device and damaging it. In particular, in the case of an image sensor such as a CCD, the image quality is degraded when the chip is attached.
【０００８】本発明は、このような従来の問題に鑑みて
なされたものであり、その目的とするところは、切削工
程におけるチップ欠けを生じにくくし、信頼性を向上さ
せることができる半導体装置の製造方法を提供すること
にある。The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a semiconductor device which can reduce chipping in a cutting process and improve reliability. It is to provide a manufacturing method.
【０００９】[0009]
【課題を解決するための手段】上述した目的を達成する
ため、本発明の第１の発明の特徴は、半導体基板の表面
上に形成された個々の半導体装置を、該半導体装置間の
分離領域で切削分離する際に、前記半導体基板の結晶面
と略平行な面が一部露出する溝を、前記分離領域内に形
成する第１の切削工程と、前記溝の結晶面と略平行な面
を横切り、かつ前記半導体基板の裏面まで切削し、前記
個々の半導体装置を切削分離する第２の切削工程とを有
することである。In order to achieve the above-mentioned object, a first feature of the present invention is to separate an individual semiconductor device formed on a surface of a semiconductor substrate into an isolation region between the semiconductor devices. A first cutting step of forming, in the separation region, a groove partially exposed in a plane substantially parallel to a crystal plane of the semiconductor substrate when cutting and separating the semiconductor substrate in a plane substantially parallel to a crystal plane of the groove; And cutting to the back surface of the semiconductor substrate to cut and separate the individual semiconductor devices.
【００１０】この第１の発明によれば、第１の切削工程
で半導体基板の結晶面と略平行な面を露出させているの
で、第２の切削工程時にストレスが加わっても切削端部
でのチップ欠けが生じにくくなり、半導体装置の信頼性
を向上させることができる。According to the first aspect of the present invention, the surface substantially parallel to the crystal plane of the semiconductor substrate is exposed in the first cutting step. Chip chipping hardly occurs, and the reliability of the semiconductor device can be improved.
【００１１】第２の発明の特徴は、上記第１の発明にお
いて、半導体基板の結晶面と略平行な面を露出させる形
状を有した切削刃を用いて溝を形成することである。A feature of the second invention is that, in the first invention, the groove is formed by using a cutting blade having a shape exposing a plane substantially parallel to the crystal plane of the semiconductor substrate.
【００１２】この第２の発明によれば、半導体基板の結
晶方位に応じた断面形状、例えばＶ字型や台形などの切
削刃を用いることにより、結晶面と略平行な面が露出す
る溝を形成することができる。According to the second aspect of the present invention, by using a cross-sectional shape corresponding to the crystal orientation of the semiconductor substrate, for example, a V-shaped or trapezoidal cutting blade, a groove whose surface substantially parallel to the crystal surface is exposed is formed. Can be formed.
【００１３】第３の発明の特徴は、上記第１の発明にお
いて、半導体基板の結晶面と略平行な面が露出する溝
を、薬品によるエッチングで形成することである。A feature of the third invention is that, in the first invention, a groove exposing a surface substantially parallel to a crystal plane of the semiconductor substrate is formed by etching with a chemical.
【００１４】この第３の発明によれば、分離領域以外を
酸化膜、窒化膜等のパッシベーション膜でカバーし、水
酸化カリウムの様な薬品を用いることによって分離領域
のみをエッチングすることができる。According to the third aspect, it is possible to cover only the isolation region with a passivation film such as an oxide film or a nitride film and to etch only the isolation region by using a chemical such as potassium hydroxide.
【００１５】第４の発明の特徴は、上記第１乃至第３の
発明において、前記第１の切削工程及び第２の切削工程
を繰り返し行うことである。A feature of the fourth invention is that, in the first to third inventions, the first cutting step and the second cutting step are repeatedly performed.
【００１６】この第４の発明によれば、各工程を繰り返
し行った時、第２の切削工程での切削溝の深さを浅くす
ることにより、チップ欠けの程度を更に軽減することが
できる。According to the fourth aspect, when each step is repeatedly performed, the degree of chip chipping can be further reduced by reducing the depth of the cutting groove in the second cutting step.
【００１７】[0017]
【発明の実施の形態】以下、本発明の一実施形態を図面
を用いて説明する。図中、従来の技術で説明したものと
同一のものには同一番号を付した。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In the figure, the same components as those described in the related art are denoted by the same reference numerals.
【００１８】図１（ａ）は、図４（ａ）と同様に半導体
装置が形成されている、切削する前のウェハの断面図を
示すものである。半導体基板１の表面には、半導体装置
とそれをカバーするための物質膜３の領域と、物質膜３
の間の分離領域となるスクライブライン５が形成されて
いる。FIG. 1A is a cross-sectional view of a wafer before cutting, on which semiconductor devices are formed as in FIG. 4A. On the surface of the semiconductor substrate 1, a region of the semiconductor device and the material film 3 for covering the semiconductor device,
A scribe line 5 is formed as a separation area between the scribe lines.
【００１９】図１（ｂ）は、第１の切削工程を説明する
ための断面図である。図に示すように、第１の切削工程
において、先端の断面形状がＶ字型となっている切削刃
７を用いてスクライブライン５の中央部（幅Ｗ１）を切
削し、表面の幅がＷ１になるＶ字型の溝を形成する。こ
の際、切削されてできたＶ字型溝の面は半導体基板１の
結晶面と略平行な面であり、Ｖ字型溝と半導体基板１の
表面とのなす角度φは結晶方位で決まる角度にほぼ等し
い。切削刃７は、このようなＶ字型溝を形成できる形状
をしている。FIG. 1B is a sectional view for explaining a first cutting step. As shown in the figure, in the first cutting step, the central part (width W1) of the scribe line 5 is cut using a cutting blade 7 having a V-shaped cross section at the tip, and the width of the surface becomes W1. A V-shaped groove is formed. At this time, the surface of the V-shaped groove formed by cutting is substantially parallel to the crystal plane of the semiconductor substrate 1, and the angle φ between the V-shaped groove and the surface of the semiconductor substrate 1 is an angle determined by the crystal orientation. Is approximately equal to The cutting blade 7 has a shape capable of forming such a V-shaped groove.
【００２０】例えば（１００）シリコン結晶において
は、ウェハのオリフラ方向が（０１１）の場合、φ＝５
４．７°とすると面方位（１１１）が表れる。For example, in the case of (100) silicon crystal, when the orientation flat direction of the wafer is (011), φ = 5
When the angle is set to 4.7 °, a plane orientation (111) appears.
【００２１】第２の切削工程では、第１の切削工程で形
成されたＶ字型溝の中央部を、幅Ｗ１より狭い幅Ｗ３で
裏面まで切削して半導体装置を分離する（図１
（ｃ））。In the second cutting step, the semiconductor device is separated by cutting the center of the V-shaped groove formed in the first cutting step to the back surface with a width W3 smaller than the width W1 (FIG. 1).
(C)).
【００２２】このように、第１の切削工程でＶ字型の溝
を形成し、半導体基板１の結晶面と略平行な面を露出さ
せることにより、各切削工程においてストレスが加わっ
ても、チップ欠けが生じにくくなる。As described above, the V-shaped groove is formed in the first cutting step, and the surface substantially parallel to the crystal plane of the semiconductor substrate 1 is exposed. Chipping is less likely to occur.
【００２３】上述した実施形態では、第１の切削工程で
Ｖ字型の溝を形成する切削方法を説明したが、本発明は
半導体基板１の結晶面と略平行な面を露出させることが
できれば、Ｖ字型の溝に限る必要はない。例えば、図２
のように、底部の幅がＷ５となるような台形の溝を第１
の切削工程で形成しても良いものである。但し、溝と半
導体基板１の表面とのなす角度φは結晶方位で決まる角
度にほぼ等しく、底部における幅Ｗ５は第２の切削工程
の切削幅Ｗ３よりも小さくなければいけない。すなわ
ち、テーパ面で切削すればよい。In the above-described embodiment, the cutting method for forming a V-shaped groove in the first cutting step has been described. However, the present invention is not limited to the case where a plane substantially parallel to the crystal plane of the semiconductor substrate 1 can be exposed. , V-shaped grooves need not be limited. For example, FIG.
The first trapezoidal groove having a width of W5 as shown in FIG.
May be formed in the cutting step. However, the angle φ between the groove and the surface of the semiconductor substrate 1 is almost equal to the angle determined by the crystal orientation, and the width W5 at the bottom must be smaller than the cutting width W3 in the second cutting step. That is, cutting may be performed on the tapered surface.
【００２４】なお、第１の切削工程における溝の切削方
法は、図１（ｂ）で示したようなテーパ角を持った切削
刃７で形成してもよいが、水酸化カリウムの様な薬品を
用いて結晶面（１１１）が露出するエッチング手法を用
いてもよい。この場合、スクライブライン５以外を酸化
膜、窒化膜等のパッシベーション膜でカバーしておけば
耐薬品性がありエッチングされず、スクライブライン５
のみエッチングされ所望の形状にすることができる。The groove may be cut in the first cutting step by using a cutting blade 7 having a taper angle as shown in FIG. 1B. May be used to expose the crystal plane (111). In this case, if the portion other than the scribe line 5 is covered with a passivation film such as an oxide film or a nitride film, the scribe line 5 is not etched because of chemical resistance.
Only a desired shape can be formed by etching.
【００２５】また、第１及び第２の切削工程は、各１回
づつ行って半導体装置を分離しても良いが、それぞれの
工程を組み合わせて繰り返すことで半導体装置の分離を
行っても良いものである。各工程を繰り返し行った時、
第２の切削工程での切削溝の深さを浅くすることによ
り、チップ欠けの程度を更に軽減することができる。The first and second cutting steps may be performed once each to separate the semiconductor device, but the semiconductor device may be separated by repeating the respective steps in combination. It is. When each process is repeated,
By reducing the depth of the cutting groove in the second cutting step, the degree of chip chipping can be further reduced.
【００２６】[0026]
【発明の効果】本発明によれば、第１の切削工程で半導
体基板の結晶面と略平行な面を露出する溝を形成してい
るので、第２の切削工程時に切削刃の歪によるストレス
があっても切削端部でのチップ欠けが生じにくくなり、
半導体装置の信頼性を向上させることができる。According to the present invention, since the grooves which expose the plane substantially parallel to the crystal plane of the semiconductor substrate are formed in the first cutting step, the stress caused by the distortion of the cutting blade during the second cutting step is reduced. Chips are less likely to occur at the cutting end,
The reliability of the semiconductor device can be improved.
【図１】本発明の切削方法における一実施形態を説明す
るための工程断面図。FIG. 1 is a process sectional view for explaining one embodiment of a cutting method of the present invention.
【図２】本発明の他の実施形態を説明するための工程断
面図。FIG. 2 is a process cross-sectional view for explaining another embodiment of the present invention.
【図３】従来の切削工程で用いられているブレードダイ
サーの刃先を示す断面図。FIG. 3 is a sectional view showing a cutting edge of a blade dicer used in a conventional cutting process.
【図４】従来の切削方法を説明するための工程断面図。FIG. 4 is a process sectional view for explaining a conventional cutting method.
１ 半導体基板 ３ 物質膜 ５ スクライブライン ７ 切削刃 ９ 刃先 １１ コーナー Ｗ１，Ｗ２，Ｗ３，Ｗ５，Ｗ７，Ｗ９ 切削幅 Ｄ７，Ｄ９ 切削深さ φ 切削溝と基板表面とのなす角度 Reference Signs List 1 semiconductor substrate 3 material film 5 scribe line 7 cutting blade 9 cutting edge 11 corner W1, W2, W3, W5, W7, W9 cutting width D7, D9 cutting depth φ angle between cutting groove and substrate surface
Claims (4)
半導体装置を、該半導体装置間の分離領域で切削分離す
る際に、 前記半導体基板の結晶面と略平行な面が一部露出する溝
を、前記分離領域内に形成する第１の切削工程と、 前記溝の結晶面と略平行な面を横切り、かつ前記半導体
基板の裏面まで切削し、前記個々の半導体装置を切削分
離する第２の切削工程とを有することを特徴とする半導
体装置の製造方法。When a semiconductor device formed on a surface of a semiconductor substrate is cut and separated in a separation region between the semiconductor devices, a surface substantially parallel to a crystal plane of the semiconductor substrate is partially exposed. A first cutting step of forming a groove in the separation region, a step of cutting across the plane substantially parallel to the crystal plane of the groove and cutting to the back surface of the semiconductor substrate, and cutting and separating the individual semiconductor devices. 2. A method for manufacturing a semiconductor device, comprising:
板の結晶面と略平行な面を露出させる形状を有した切削
刃を用いて溝を形成することを特徴とする請求項１記載
の半導体装置の製造方法。2. The semiconductor according to claim 1, wherein in the first cutting step, a groove is formed using a cutting blade having a shape exposing a plane substantially parallel to a crystal plane of the semiconductor substrate. Device manufacturing method.
板の結晶面と略平行な面が露出する溝を、薬品によるエ
ッチングで形成することを特徴とする請求項１記載の半
導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein in the first cutting step, a groove exposing a plane substantially parallel to a crystal plane of the semiconductor substrate is formed by etching with a chemical. .
を繰り返し行うことを特徴とする請求項１乃至３記載の
半導体装置の製造方法。4. The method according to claim 1, wherein the first cutting step and the second cutting step are repeatedly performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21485696A JPH1064855A (en) | 1996-08-14 | 1996-08-14 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21485696A JPH1064855A (en) | 1996-08-14 | 1996-08-14 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1064855A true JPH1064855A (en) | 1998-03-06 |
Family
ID=16662692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21485696A Pending JPH1064855A (en) | 1996-08-14 | 1996-08-14 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1064855A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002335030A (en) * | 2001-05-10 | 2002-11-22 | Sony Corp | Semiconductor laser and method of manufacturing it |
| JP2004279630A (en) * | 2003-03-14 | 2004-10-07 | Miyota Kk | Method for manufacturing liquid crystal display panel |
| JP2006157872A (en) * | 2004-10-28 | 2006-06-15 | Seiko Instruments Inc | Piezoelectric vibrator, manufacturing method thereof, oscillator, electronic apparatus, and radio clock |
| JP2006156926A (en) * | 2004-08-19 | 2006-06-15 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2007068113A (en) * | 2005-09-02 | 2007-03-15 | Nippon Dempa Kogyo Co Ltd | Method for manufacturing quartz resonator |
| KR100980096B1 (en) | 2008-03-14 | 2010-09-07 | 박태석 | Wafer level chip size package for IC devices using dicing process and method for manufacturing the same |
| US8358018B2 (en) | 2008-05-07 | 2013-01-22 | Panasonic Corporation | Resin sealing structure for electronic component and resin sealing method for electronic component |
| US8697558B2 (en) | 2004-08-19 | 2014-04-15 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2016031967A (en) * | 2014-07-28 | 2016-03-07 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
-
1996
- 1996-08-14 JP JP21485696A patent/JPH1064855A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002335030A (en) * | 2001-05-10 | 2002-11-22 | Sony Corp | Semiconductor laser and method of manufacturing it |
| JP2004279630A (en) * | 2003-03-14 | 2004-10-07 | Miyota Kk | Method for manufacturing liquid crystal display panel |
| JP2006156926A (en) * | 2004-08-19 | 2006-06-15 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method therefor |
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