JPH10553A - Chemical and mechanical polishing method and device thereof, and manufacture of semiconductor device - Google Patents
Chemical and mechanical polishing method and device thereof, and manufacture of semiconductor deviceInfo
- Publication number
- JPH10553A JPH10553A JP14890496A JP14890496A JPH10553A JP H10553 A JPH10553 A JP H10553A JP 14890496 A JP14890496 A JP 14890496A JP 14890496 A JP14890496 A JP 14890496A JP H10553 A JPH10553 A JP H10553A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- insulating film
- chemical
- substrate
- mechanical polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Grinding-Machine Dressing And Accessory Apparatuses (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路等
を有する半導体基板を製造するための基板上に形成され
る絶縁膜、金属膜等の表面を平坦に化学的・機械的な研
磨加工をする研磨加工方法及びその装置並びに半導体集
積回路等を有する半導体基板を製造する半導体基板の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical and mechanical polishing process for flattening the surface of an insulating film, a metal film and the like formed on a substrate for manufacturing a semiconductor substrate having a semiconductor integrated circuit and the like. The present invention relates to a polishing method and an apparatus therefor, and a method of manufacturing a semiconductor substrate having a semiconductor integrated circuit and the like.
【０００２】[0002]
【従来の技術】基板の外周部を平坦に研磨する化学的・
機械的な研磨加工をするＣＭＰ（Chemical Mechanical
Polishing）技術について、米国特許第4954142号の明細
書及び図面において知られている。この従来技術は、研
磨定盤上に支持され、研磨剤を塗布した研磨パッドに上
記電子部品の表面を押しつける際に、基板の外周部に設
置するリングを研磨パッドに押し付けて化学的・機械的
な研磨加工をするＣＭＰ（Chemical Mechanical Polish
ing）である。2. Description of the Related Art Chemical polishing for polishing the outer peripheral portion of a substrate flat.
CMP (Chemical Mechanical) for mechanical polishing
Polishing) technology is known in the specification and drawings of US Pat. No. 4,954,142. According to this conventional technique, when a surface of the electronic component is pressed against a polishing pad, which is supported on a polishing platen and is coated with an abrasive, a ring installed on an outer peripheral portion of the substrate is pressed against the polishing pad to perform chemical and mechanical CMP (Chemical Mechanical Polish)
ing).
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術（ＣＭ
Ｐ）では、化学的・機械的な研磨加工中にリングが研磨
パッドを押し付けることによる、研磨パッドの摩滅に伴
う研磨能率の被加工物の表面内での変動に対する配慮が
なされていないため、被加工物上の表面内の絶縁膜等の
研磨量の分布を制御できず絶縁膜などの厚さを均一にで
きないという課題を有していた。The above prior art (CM)
In P), no consideration is given to fluctuations in the polishing efficiency in the surface of the workpiece due to the wear of the polishing pad due to the ring pressing the polishing pad during the chemical / mechanical polishing, so that the polishing is not performed. There is a problem that the distribution of the polishing amount of the insulating film or the like in the surface on the workpiece cannot be controlled, and the thickness of the insulating film or the like cannot be made uniform.
【０００４】また、被加工物とリングとの隙間での研磨
パッドの変形に対する配慮がなされていないため、被加
工物の外周部の研磨量の分布を制御できず絶縁膜などの
厚さを均一にできないという課題を有していた。Further, since no consideration is given to the deformation of the polishing pad in the gap between the workpiece and the ring, the distribution of the amount of polishing on the outer peripheral portion of the workpiece cannot be controlled, and the thickness of the insulating film or the like becomes uniform. There was a problem that it could not be done.
【０００５】また、化学的・機械的な研磨加工中にリン
グが研磨パッドを押し付けることによる、被加工物の表
面内での研磨圧力変動に対する配慮がなされていないた
め、被加工物上の表面内の絶縁膜等の研磨量の分布を制
御できず絶縁膜などの厚さを均一にできないという課題
を有していた。In addition, since no consideration is given to fluctuations in the polishing pressure within the surface of the workpiece due to the ring pressing against the polishing pad during the chemical / mechanical polishing, the internal surface of the workpiece is not considered. However, there is a problem that the distribution of the polishing amount of the insulating film or the like cannot be controlled and the thickness of the insulating film or the like cannot be made uniform.
【０００６】本発明の目的は、上記課題を解決すべく、
基板上に形成された絶縁膜の厚さを均一に研磨加工でき
るようにした化学的・機械的な研磨加工方法及びその装
置を提供することにある。[0006] An object of the present invention is to solve the above problems.
An object of the present invention is to provide a chemical / mechanical polishing method and apparatus capable of uniformly polishing the thickness of an insulating film formed on a substrate.
【０００７】また本発明の目的は、半導体基板上におけ
る層間絶縁膜の表面に微小凹凸がなく、しかも大きな段
差を有しない平坦な化学的・機械的な研磨加工を施して
その上にたとえば０．２５μm以下の極微細配線を形成
できるようにした化学的・機械的な研磨加工方法及びそ
の装置を提供することにある。Another object of the present invention is to provide a flat chemical / mechanical polishing process which does not have minute unevenness on the surface of an interlayer insulating film on a semiconductor substrate and does not have a large step. An object of the present invention is to provide a chemical / mechanical polishing method and apparatus capable of forming ultra-fine wiring of 25 μm or less.
【０００８】また本発明の目的は、配線幅が、たとえば
０．２５μm以下の極微細配線を有する多層配線を形成
した半導体基板を簡略化して製造するようにした半導体
基板の製造方法を提供することにある。It is another object of the present invention to provide a method of manufacturing a semiconductor substrate in which a semiconductor substrate on which a multilayer wiring having an extremely fine wiring having a wiring width of, for example, 0.25 μm or less is formed in a simplified manner. It is in.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、基板の外周部分の研磨圧力を制御して上
記基板面に対して化学的・機械的な研磨加工を行うこと
を特徴とする化学的・機械的な研磨加工方法である。In order to achieve the above object, the present invention provides a method for controlling the polishing pressure on the outer peripheral portion of a substrate to perform chemical and mechanical polishing on the substrate surface. This is a feature of chemical and mechanical polishing.
【００１０】また、本発明は、基板の外周部分に隣接し
て設けた砥石を研磨パッドに押し付ける圧力を制御して
基板の外周部分の研磨圧力を制御して上記基板面に対し
て化学的・機械的な研磨加工を行うことを特徴とする化
学的・機械的な研磨加工方法である。Further, the present invention provides a method for controlling a polishing pressure on an outer peripheral portion of a substrate by controlling a pressure of pressing a grindstone provided adjacent to an outer peripheral portion of the substrate against a polishing pad to chemically and chemically control a polishing surface of the substrate. This is a chemical / mechanical polishing method characterized by performing mechanical polishing.
【００１１】また、本発明は、基板の外周部分に隣接し
て設けられ樹脂または弾性体等の縦弾性係数が基板より
小さい材料で構成されたリングを研磨パッドに押し付け
る圧力を制御して基板の外周部分の研磨圧力を制御し、
上記リングの外周に設置した砥石を研磨パッドに押し付
けて上記基板面に対して化学的・機械的な研磨加工を行
うことを特徴とする化学的・機械的な研磨加工方法であ
る。Further, the present invention provides a method for controlling a pressure of a ring, which is provided adjacent to an outer peripheral portion of a substrate and is made of a material having a smaller longitudinal elastic modulus than a substrate, such as a resin or an elastic body, against a polishing pad. Control the polishing pressure on the outer periphery,
A chemical / mechanical polishing method characterized by performing a chemical / mechanical polishing process on the substrate surface by pressing a grindstone provided on an outer periphery of the ring against a polishing pad.
【００１２】また、本発明は、基板の外周部分に隣接し
て設けた砥石を研磨パッドに押し付けて研磨パッドを目
立てて上記基板面に対して化学的・機械的な研磨加工を
行うことを特徴とする化学的・機械的な研磨加工方法で
ある。The present invention is also characterized in that a grindstone provided adjacent to the outer peripheral portion of the substrate is pressed against the polishing pad to sharpen the polishing pad and to perform chemical and mechanical polishing on the substrate surface. Chemical and mechanical polishing method.
【００１３】また、本発明は、基板の外周部分に隣接し
て設けた砥石及びリングに加える圧力を研磨圧力と独立
して設定して化学的・機械的な研磨加工を行うことを特
徴とする化学的・機械的な研磨加工方法である。Further, the present invention is characterized in that chemical and mechanical polishing is performed by setting a pressure applied to a grindstone and a ring provided adjacent to an outer peripheral portion of the substrate independently of a polishing pressure. This is a chemical and mechanical polishing method.
【００１４】以上説明したように、本発明によれば、た
とえば半導体装置における層間絶縁膜の厚さを均一にで
きるので、半導体装置の高信頼化と高集積化を実現する
ことができる。即ち、半導体集積回路は多層配線層を形
成するため、下層配線と上層配線の間に層間絶縁膜が存
在し、この層間絶縁膜の表面を、たとえば研磨量ばらつ
きを±３％以下の精度でしかも微小凹凸を０．１μm以
下を実現することができ、その結果層間絶縁膜の上に均
一な厚さの配線膜を形成でき、しかも露光における焦点
マージンが拡大して容易に配線幅が０．２５μm以下の
配線を形成することができる。As described above, according to the present invention, for example, the thickness of an interlayer insulating film in a semiconductor device can be made uniform, so that high reliability and high integration of the semiconductor device can be realized. That is, since a semiconductor integrated circuit forms a multilayer wiring layer, an interlayer insulating film exists between the lower wiring and the upper wiring, and the surface of the interlayer insulating film is polished with a polishing amount variation of ± 3% or less. Fine irregularities of 0.1 μm or less can be realized. As a result, a wiring film having a uniform thickness can be formed on the interlayer insulating film. The following wirings can be formed.
【００１５】また本発明によれば、層間絶縁膜に形成さ
れたコンタクトホールにタングステン等の導電体をコン
タクトスタッドとして選択ＣＶＤで形成する際、上記層
間絶縁膜上の微小の欠陥を核として成長したタングステ
ン等の導電膜が完全に除去することができ、層間絶縁膜
上に高信頼度を有する配線を形成することができる効果
がある。According to the present invention, when a conductor such as tungsten is formed as a contact stud in a contact hole formed in an interlayer insulating film by selective CVD, the defect is grown with a micro defect on the interlayer insulating film as a nucleus. There is an effect that a conductive film such as tungsten can be completely removed, and a highly reliable wiring can be formed over the interlayer insulating film.
【００１６】また本発明によれば、絶縁膜または金属膜
の表面において高い平坦度を得ることができるので、た
とえば露光工程において焦点ずれを防止して精度の高い
解像度の露光を実現し、高集積化を達成することができ
る。Further, according to the present invention, high flatness can be obtained on the surface of the insulating film or the metal film. Therefore, for example, defocusing can be prevented in the exposure step to realize exposure with high resolution and high integration. Can be achieved.
【００１７】[0017]
【発明の実施の形態】発明の実施の形態について図面を
用いて説明する。Embodiments of the present invention will be described with reference to the drawings.
【００１８】本発明に係る化学的・機械的な研磨加工装
置の一実施形態を示す全体構成および研磨加工要領を、
図１を参照して説明する。図１は化学的・機械的な研磨
加工装置の概念図である。図１において、半導体基板１
（ウェーハ）は、チャック４に支持されたベース３上に
貼り付けた支持体２に取り付けられている。研磨定盤１
３の上に、平坦化を良くするために酸やアルカリに強く
耐摩耗性に優れた例えば硬質発泡ポリウレタン系の研磨
パッド１４が取り付けられている。研磨パッド１４の上
に、アルカリを含む溶液にＳｉＯ２の砥粒を入れたもの
や、酸を含む溶液にアルミナや酸化セリウムの砥粒を入
れた研磨剤１６が研磨剤供給管１５から供給される。An embodiment of the chemical and mechanical polishing apparatus according to the present invention, which is an overall configuration and polishing procedure, is as follows.
This will be described with reference to FIG. FIG. 1 is a conceptual diagram of a chemical and mechanical polishing apparatus. In FIG. 1, a semiconductor substrate 1
The (wafer) is attached to a support 2 attached to a base 3 supported by a chuck 4. Polishing surface plate 1
A polishing pad 14 of, for example, a hard polyurethane foam, which is resistant to acids and alkalis and has excellent abrasion resistance, is mounted on the surface 3 to improve flatness. A polishing pad 16 in which SiO 2 abrasive grains are put in a solution containing alkali or an abrasive 16 in which abrasive grains of alumina or cerium oxide are put in a solution containing acid is supplied from a polishing agent supply pipe 15 onto a polishing pad 14. .
【００１９】化学的・機械的な研磨加工は、図１に示す
ように研磨機基部２５上に固定されたモータ２８によっ
て回転する研磨パッド１４の上に研磨剤供給管１５から
研磨剤１６を供給しながら、チャック４で支持した被加
工物１を研磨パッド１４に接触させ、さらにモータ２２
によって回転するチャック４に研磨荷重を加えて矢印３
３で示すように研磨定盤１３の半径方向に研磨定盤１３
との間で相対的に往復運動させると、絶縁膜の表面は上
記研磨剤１６に含まれるアルカリ溶液との間で化学反応
が行われながら上記研磨剤１６に含まれるＳｉＯ２等の
砥粒によって機械的な研磨が行われて化学的・機械的な
研磨加工が進行し、段差が０．１μm以下に平坦化され
た、絶縁膜厚さのばらつきが±３％以下の所望の膜厚を
有する層間絶縁膜を得ることができる。In the chemical and mechanical polishing process, as shown in FIG. 1, an abrasive 16 is supplied from an abrasive supply pipe 15 onto a polishing pad 14 which is rotated by a motor 28 fixed on a base 25 of the polishing machine. The workpiece 1 supported by the chuck 4 is brought into contact with the polishing pad 14 while
Polishing load is applied to the chuck 4 rotating by
3, the polishing platen 13 is arranged in the radial direction of the polishing platen 13.
The surface of the insulating film is mechanically reacted with the alkaline solution contained in the polishing agent 16 by the abrasive grains such as SiO 2 contained in the polishing agent 16 while performing a chemical reaction with the alkaline solution contained in the polishing agent 16. Polishing is performed, chemical and mechanical polishing proceeds, the step is flattened to 0.1 μm or less, and the variation of the insulating film thickness is ± 3% or less. An insulating film can be obtained.
【００２０】なお、金属膜に対する化学的・機械的な研
磨加工の場合には、研磨剤１６としてはアルカリを含む
溶液にＳｉＯ２の砥粒を入れたものや、酸を含む溶液に
アルミナや酸化セリウム等の砥粒を入れたものが用いら
れる。In the case of chemical / mechanical polishing of a metal film, the abrasive 16 may be a solution containing an alkali containing a SiO2 abrasive, or a solution containing an acid may be made of alumina or cerium oxide. What contains abrasive grains such as is used.
【００２１】研磨機基部２５に取り付けられた、矢印３
３で示すように研磨定盤１３の半径方向に可動する往復
テーブル３０にベース２９が取り付けられている。該ベ
ース２９には、エアシリンダ２４が取り付けられてお
り、該エアシリンダ２４には、矢印２３で示すように研
磨定盤１３に垂直な方向に駆動可能なエアシリンダ軸２
３が取り付けられている。ベース２９にはエアシリンダ
２７が取り付けられており、矢印３２に示すように研磨
定盤１３の半径方向に可動し、対向する位置に設置した
ストッパ２６と共にベース２３を固定可能なストッパ２
６が取り付けられている。エアシリンダ軸２３に取り付
けられたチャック回転用モータ及び減速機２２には研磨
定盤１３と垂直な方向に回転可能なチャック回転軸２１
が取り付けられている。該チャック回転軸２１にはチャ
ック４が取り付けられている。チャック４に設けられた
窪みＡ５には袋Ａ６が設置されており、該袋Ａ６には剛
体３が取り付けられている。該剛体３には支持体２が貼
り付けられており、該支持体２には半導体基板１が支持
されている。スリップリング２０から気体を導入し気体
供給通路１７を介して袋Ａ６に供給される。また、チャ
ック４の窪みＡ５の外周に設けられた窪みＢ７には袋Ｂ
８が設置されており、該袋Ｂ８にはリング１１が取り付
けられている。スリップリング２０から気体を導入し気
体供給通路１８を介して袋Ｂ８に供給される。また、窪
み７の外周に設けられた窪みＣ９には袋Ｃ１０が設置さ
れており、該袋Ｃ１０には砥石１２が取り付けられてい
る。スリップリング２０から気体を導入し気体供給通路
１９を介して袋Ｃ１０に供給される。半導体基板１を支
持体２に取り付け、エアシリンダ軸２３を定盤１３の方
向に駆動し半導体基板１が研磨パッド１４に接した時点
でエアシリンダ軸２３の駆動を停止しストッパ２６をエ
アシリンダ２３の方向に駆動してエアシリンダ２３を固
定する。そして、袋Ａ６に気体を供給して半導体基板１
に研磨圧力を与える。また、袋Ｂに気体を供給してリン
グ１１によって研磨パッド１４を押圧する。また、袋Ｃ
に気体を供給して砥石１２によって研磨パッド１４を押
圧する。The arrow 3 attached to the polishing machine base 25
As shown by 3, a base 29 is attached to a reciprocating table 30 that moves in the radial direction of the polishing table 13. An air cylinder 24 is attached to the base 29. The air cylinder 24 is driven by an air cylinder shaft 2 that can be driven in a direction perpendicular to the polishing platen 13 as indicated by an arrow 23.
3 is attached. An air cylinder 27 is attached to the base 29 and is movable in the radial direction of the polishing platen 13 as shown by an arrow 32, and the stopper 2 is capable of fixing the base 23 together with the stopper 26 installed at an opposing position.
6 is attached. A chuck rotating shaft 21 rotatable in a direction perpendicular to the polishing platen 13 is provided on a chuck rotating motor and a speed reducer 22 mounted on an air cylinder shaft 23.
Is attached. The chuck 4 is attached to the chuck rotating shaft 21. A bag A6 is installed in a depression A5 provided in the chuck 4, and the rigid body 3 is attached to the bag A6. A support 2 is attached to the rigid body 3, and the semiconductor substrate 1 is supported on the support 2. Gas is introduced from the slip ring 20 and supplied to the bag A6 via the gas supply passage 17. Further, a bag B is provided in a recess B7 provided on the outer periphery of the recess A5 of the chuck 4.
8 is installed, and a ring 11 is attached to the bag B8. Gas is introduced from the slip ring 20 and supplied to the bag B8 via the gas supply passage 18. Further, a bag C10 is provided in a depression C9 provided on the outer periphery of the depression 7, and a grindstone 12 is attached to the bag C10. Gas is introduced from the slip ring 20 and supplied to the bag C10 via the gas supply passage 19. The semiconductor substrate 1 is mounted on the support 2, and the air cylinder shaft 23 is driven in the direction of the surface plate 13. When the semiconductor substrate 1 comes into contact with the polishing pad 14, the driving of the air cylinder shaft 23 is stopped and the stopper 26 is moved to the air cylinder 23. And the air cylinder 23 is fixed. Then, a gas is supplied to the bag A6 and the semiconductor substrate 1
To the polishing pressure. Further, gas is supplied to the bag B, and the polishing pad 14 is pressed by the ring 11. In addition, bag C
, And the polishing pad 14 is pressed by the grindstone 12.
【００２２】次に、チャック４によるウェーハ外周部の
研磨圧力分布制御と、ドレッシングについて図２を用い
て説明する。図２は、チャック４の外周部分の断面拡大
図である。チャック４において、１２Ａは砥石台、１２
Ｂは砥石台１２Ａに支持された砥石、１２Ｃは砥石１２
Ｂの表面に固定されている砥粒である。圧力ＰＡが剛体
３に加えられると、半導体基板１と研磨パッド１４との
間に生じる研磨圧力はＰＡとなる。圧力ＰＢがリング１
１に加えられると、リング１１と研磨パッド１４との間
に生じる圧力はＰｒとなる。圧力ＰＣがリング砥石台１
２Ａに加えられると、砥粒１２Ｃと研磨パッド１４との
間に生じる圧力はＰｄとなる。リング１１を圧力Ｐｒで
研磨パッド１４を押圧することにより、半導体基板１の
外周部の研磨パッド１４を定盤１３の方向に変形させる
ことになる。そして研磨パッドの１４の変形量を適切に
することにより、半導体基板１の外周部の研磨圧力を変
化させることができる。また、砥粒１２Ｃを圧力Ｐｄで
研磨パッド１４に押圧することにより、砥粒１２Ｃが研
磨パッド１４に切り込み、研磨パッド１４の表面が目立
てられることになる。Next, the control of the polishing pressure distribution on the outer peripheral portion of the wafer by the chuck 4 and the dressing will be described with reference to FIG. FIG. 2 is an enlarged cross-sectional view of the outer peripheral portion of the chuck 4. In the chuck 4, 12A is a grindstone base, 12A
B is a grindstone supported by a grindstone base 12A, and 12C is a grindstone 12
The abrasive grains fixed to the surface of B. When the pressure PA is applied to the rigid body 3, the polishing pressure generated between the semiconductor substrate 1 and the polishing pad 14 becomes PA. Pressure PB is ring 1
When applied to 1, the pressure generated between the ring 11 and the polishing pad 14 becomes Pr. Pressure PC is ring whetstone 1
When applied to 2A, the pressure generated between the abrasive grains 12C and the polishing pad 14 becomes Pd. By pressing the polishing pad 14 with the pressure Pr with the ring 11, the polishing pad 14 on the outer peripheral portion of the semiconductor substrate 1 is deformed in the direction of the platen 13. The polishing pressure at the outer peripheral portion of the semiconductor substrate 1 can be changed by appropriately adjusting the amount of deformation of the polishing pad 14. Further, by pressing the abrasive grains 12C against the polishing pad 14 with the pressure Pd, the abrasive grains 12C cut into the polishing pad 14 and the surface of the polishing pad 14 is sharpened.
【００２３】図３は、研磨定盤１３上のチャック４の配
置図である。（ａ）は本発明のチャック４の配置図であ
る。（ｂ）は本発明を用いない場合のチャック４と砥石
の配置図を示す。本発明では、チャック４が周囲に砥石
１２を有しているため、目立て用のチャックを設置する
必要がなく、研磨パッド１４上に多くのチャック４を設
置することができ、一度に多くの半導体基板を研磨する
ことができる。しかし、本発明を用いない場合には砥石
を有する目立て用のチャックを研磨パッド１４上に設置
する必要があるため、本発明を用いた場合よりも研磨用
のチャックが１つ少なくなり、スループットが低下す
る。FIG. 3 is an arrangement diagram of the chuck 4 on the polishing platen 13. (A) is an arrangement view of the chuck 4 of the present invention. (B) shows an arrangement diagram of the chuck 4 and the grindstone when the present invention is not used. In the present invention, since the chuck 4 has the grindstone 12 around the periphery, it is not necessary to install a dressing chuck, so that many chucks 4 can be installed on the polishing pad 14 and many semiconductors can be formed at once. The substrate can be polished. However, when the present invention is not used, a dressing chuck having a grindstone needs to be set on the polishing pad 14, so that the number of polishing chucks is one less than when the present invention is used, and the throughput is reduced. descend.
【００２４】また、本発明に係る化学的・機械的な研磨
加工装置の他の一実施形態を示す全体構成および研磨加
工要領を、図４を参照して説明する。図４は化学的・機
械的な研磨加工装置の概念図である。図４において、半
導体基板１（ウエハ）は、チャック４に支持されたベー
ス３上に貼り付けた支持体２に取り付けられている。研
磨定盤１３の上に、平坦化を良くするために酸やアルカ
リに強く耐磨耗性に優れた例えば硬質発泡ポリウレタン
系の研磨パッド１４が取り付けられている。研磨パッド
１４の上に、アルカリを含む溶液にＳｉＯ２の砥粒を入
れたコロイダルシリカや、酸を含む溶液にアルミナや酸
化セリウムの砥粒を入れた研磨剤１６が研磨剤供給管１
５から供給される。Further, an overall configuration and a polishing procedure of another embodiment of the chemical / mechanical polishing apparatus according to the present invention will be described with reference to FIG. FIG. 4 is a conceptual diagram of a chemical and mechanical polishing apparatus. In FIG. 4, a semiconductor substrate 1 (wafer) is attached to a support 2 attached to a base 3 supported by a chuck 4. On the polishing platen 13, for example, a hard foamed polyurethane-based polishing pad 14 that is resistant to acids and alkalis and has excellent abrasion resistance is attached to improve the flatness. On the polishing pad 14, colloidal silica in which SiO2 abrasive grains are put in a solution containing alkali or abrasive 16 in which abrasive grains of alumina or cerium oxide are put in a solution containing acid is supplied to the polishing agent supply pipe 1.
Supplied from 5.
【００２５】化学的・機械的な研磨加工は、図４に示す
ように回転する研磨パッド１４の上に研磨剤供給管１５
から研磨剤１６を供給しながら、チャック４で支持した
被加工物１を研磨パッド１４に接触させ、さらに回転す
るチャック４に研磨荷重を加えて研磨定盤１３の半径方
向に研磨定盤１３との間で相対的に往復運動させると、
絶縁膜の表面は上記研磨剤１６に含まれるアルカリ溶液
との間で化学反応が行われながら上記研磨剤１６に含ま
れるＳｉＯ２等の砥粒によって機械的な研磨が行われて
化学的・機械的な研磨加工が進行し、段差が０．１μm
以下に平坦化された、絶縁膜厚さのばらつきが±３％以
下の所望の膜厚を有する層間絶縁膜を得ることができ
る。As shown in FIG. 4, the chemical and mechanical polishing is performed by polishing a polishing agent supply pipe 15 on a rotating polishing pad 14.
The workpiece 1 supported by the chuck 4 is brought into contact with the polishing pad 14 while supplying a polishing agent 16 from above, and a polishing load is further applied to the rotating chuck 4 so that the polishing plate 13 is moved in the radial direction of the polishing table 13. When reciprocating relatively between
The surface of the insulating film is mechanically polished by abrasive grains such as SiO 2 contained in the polishing agent 16 while undergoing a chemical reaction with an alkali solution contained in the polishing agent 16, thereby causing a chemical / mechanical reaction. Polishing process progresses and the step is 0.1μm
It is possible to obtain an interlayer insulating film having a desired thickness which is flattened below and has a variation of the insulating film thickness of ± 3% or less.
【００２６】なお、金属膜に対する化学的・機械的な研
磨加工の場合には、研磨剤１６としてはアルカリを含む
溶液にＳｉＯ２の砥粒を入れたコロイダルシリカや、酸
を含む溶液にアルミナや酸化セリウム等の砥粒を入れた
ものが用いられる。In the case of chemical / mechanical polishing of a metal film, the polishing agent 16 may be colloidal silica in which SiO 2 abrasive grains are added to a solution containing an alkali, or alumina or an oxidizing solution may be added to a solution containing an acid. What contains abrasive grains such as cerium is used.
【００２７】回転可能なチャック４に設けられた窪みＡ
５には袋Ａ６が設置されており、該袋Ａ６には剛体３が
取り付けられている。該剛体３には支持体２が貼り付け
られており、該支持体２には半導体基板１が支持されて
いる。気体供給通路１７を介して袋Ａ６に気体が供給さ
れる。また、チャック４の窪みＡ５の外周に設けられた
窪みＤ３５には袋Ｄ３６が設置されており、該袋Ｄ３６
には砥石３７が取り付けられている。気体供給通路１４
を介して袋Ｄ３６に気体が供給される。半導体基板１を
支持体２に取り付け、袋Ａ６に気体を供給して半導体基
板１に研磨圧力を与える。また、袋Ｄ３６に気体を供給
して砥石３７によって研磨パッド１４を押圧すると同時
に研磨パッド１４の表面を目立てる。Depression A provided in rotatable chuck 4
5 is provided with a bag A6, and the rigid body 3 is attached to the bag A6. A support 2 is attached to the rigid body 3, and the semiconductor substrate 1 is supported on the support 2. Gas is supplied to the bag A6 via the gas supply passage 17. A bag D36 is provided in a recess D35 provided on the outer periphery of the recess A5 of the chuck 4, and the bag D36 is provided.
Is equipped with a grindstone 37. Gas supply passage 14
The gas is supplied to the bag D36 via the. The semiconductor substrate 1 is mounted on the support 2, and a gas is supplied to the bag A6 to apply a polishing pressure to the semiconductor substrate 1. Further, a gas is supplied to the bag D36 to press the polishing pad 14 with the grindstone 37, and at the same time, the surface of the polishing pad 14 is sharpened.
【００２８】次に、チャック４によるウェーハ外周部の
研磨圧力分布制御と、ドレッシングについて図５を用い
て説明する。図２は、チャック４の外周部分の断面拡大
図である。チャック４において、３７Ａはベース、３７
Ｂは砥石台、３７Ｃは半導体基板１が研磨中にチャック
４から飛び出すことを防止するリング、３８は砥石台３
７Ｂの位置を調節するためのスペーサ、３９は砥石台３
７Ｂをベース３７Ａに固定するためのネジ、４０は砥石
台３７Ｂに固定された砥石、４１は砥石４０の表面に固
定されている砥粒である。圧力ＰＡが剛体３に加えられ
ると、半導体基板１と研磨パッド１４との間に生じる研
磨圧力はＰＡとなる。圧力ＰＤがリング１１に加えられ
ると、リング１１と研磨パッド１４との間に生じる圧力
はＰｒとなる。圧力ＰＣがリング砥石台１２Ａに加えら
れると、砥粒１２Ｃと研磨パッド１４との間に生じる圧
力はＰｄとなる。リング１１を圧力Ｐｒで研磨パッド１
４を押圧することにより、半導体基板１の外周部の研磨
パッド１４を定盤１３の方向に変形させることになる。
そして研磨パッドの１４の変形量を適切にすることによ
り、半導体基板１の外周部の研磨圧力を変化させること
ができる。また、砥粒１２Ｃを圧力Ｐｄで研磨パッド１
４に押圧することにより、砥粒１２Ｃが研磨パッド１４
に切り込み、研磨パッド１４の表面が目立てられること
になる。この場合、スペーサ３８の厚さｔを大きくする
と砥粒４１の突き出し量ｈが増加し、砥粒４１が研磨パ
ッド１４の表面を目立てる深さが増加する。Next, the control of the polishing pressure distribution on the outer peripheral portion of the wafer by the chuck 4 and the dressing will be described with reference to FIG. FIG. 2 is an enlarged cross-sectional view of the outer peripheral portion of the chuck 4. In the chuck 4, 37A is a base, 37
B is a grindstone table, 37C is a ring for preventing the semiconductor substrate 1 from jumping out of the chuck 4 during polishing, and 38 is a grindstone table 3.
Spacer for adjusting the position of 7B, 39 is the wheel head 3
A screw for fixing 7B to the base 37A, 40 is a grindstone fixed to the grindstone table 37B, and 41 is an abrasive grain fixed to the surface of the grindstone 40. When the pressure PA is applied to the rigid body 3, the polishing pressure generated between the semiconductor substrate 1 and the polishing pad 14 becomes PA. When the pressure PD is applied to the ring 11, the pressure generated between the ring 11 and the polishing pad 14 becomes Pr. When the pressure PC is applied to the ring whetstone 12A, the pressure generated between the abrasive grains 12C and the polishing pad 14 becomes Pd. The ring 11 is pressed against the polishing pad 1 with the pressure Pr.
By pressing 4, the polishing pad 14 on the outer peripheral portion of the semiconductor substrate 1 is deformed in the direction of the surface plate 13.
The polishing pressure at the outer peripheral portion of the semiconductor substrate 1 can be changed by appropriately adjusting the amount of deformation of the polishing pad 14. Further, the polishing pad 1 is pressed with the abrasive grains 12C at a pressure Pd.
4, the abrasive grains 12C cause the polishing pad 14
And the surface of the polishing pad 14 is sharpened. In this case, when the thickness t of the spacer 38 is increased, the protrusion amount h of the abrasive grains 41 increases, and the depth at which the abrasive grains 41 stand out the surface of the polishing pad 14 increases.
【００２９】次に本発明に係る化学的・機械的な研磨加
工を半導体基板上に形成されたプラズマＴＥＯＳ膜
（１．５μm堆積）からなる層間絶縁膜に適用した場合
について説明する。Next, a case where the chemical / mechanical polishing according to the present invention is applied to an interlayer insulating film composed of a plasma TEOS film (1.5 μm deposition) formed on a semiconductor substrate will be described.
【００３０】はじめに、図１に示す装置を用いた場合に
ついて説明する。主な化学的・機械的な研磨条件は、研
磨圧力３５kＰａ、半導体基板と研磨パッドの平均相対
速度：１９ｍ／ｍｉｎ、研磨剤１６：アルカリ溶液から
なるコロイダルシリカ（粒径約３０ｎｍ）、研磨パッド
１４：硬質発泡ポリウレタン系（硬度約６０度）厚さ約
１ｍｍ、半導体基板の支持体２には、ベース３の表面に
形成した厚さ約０．５ｍｍのスウェードタイプの弾性体
を用いた。砥粒１２Ｃには粒径約２５０μmのダイヤモ
ンド砥粒を用い、目立ての圧力Ｐｄは約７ｋＰａとし
た。First, the case where the apparatus shown in FIG. 1 is used will be described. The main chemical and mechanical polishing conditions are a polishing pressure of 35 kPa, an average relative speed between the semiconductor substrate and the polishing pad: 19 m / min, a polishing agent 16: colloidal silica made of an alkaline solution (particle diameter: about 30 nm), a polishing pad 14. A hard foamed polyurethane (hardness: about 60 degrees) suede type elastic body having a thickness of about 1 mm and a thickness of about 0.5 mm formed on the surface of the base 3 was used as the support 2 of the semiconductor substrate. The abrasive grains 12C used were diamond abrasive grains having a particle size of about 250 μm, and the dressing pressure Pd was about 7 kPa.
【００３１】リングの内径とウェーハの外径の差が小さ
いことが望ましいが、リングの内径とウェーハの外径の
差が０.１ｍｍの場合にはリングの内径とウェーハの外
径の公差のため、研磨中にリングに拘束されてウェーハ
が変形し、研磨量ばらつきが大きくなった。また、リン
グの内径とウェーハの外径の差が１ｍｍ以上の場合には
ウェーハがチャックの一方に偏り、偏荷重がかかるた
め、研磨量ばらつきが大きくなった。そこで、リングの
内径とウェーハの外径の差は０.１ｍｍないし１ｍｍが
適当である。本実施例ではリングの内径とウェーハの外
径の差を０.５ｍｍとした。It is desirable that the difference between the inner diameter of the ring and the outer diameter of the wafer is small. However, when the difference between the inner diameter of the ring and the outer diameter of the wafer is 0.1 mm, there is a tolerance between the inner diameter of the ring and the outer diameter of the wafer. During the polishing, the wafer was deformed by being restrained by the ring, and the variation in the polishing amount became large. Further, when the difference between the inner diameter of the ring and the outer diameter of the wafer was 1 mm or more, the wafer was biased to one side of the chuck, and an uneven load was applied, resulting in a large variation in polishing amount. Therefore, the difference between the inner diameter of the ring and the outer diameter of the wafer is suitably 0.1 mm to 1 mm. In this embodiment, the difference between the inner diameter of the ring and the outer diameter of the wafer is set to 0.5 mm.
【００３２】また、リングで研磨パッドを加圧すると、
研磨パッドが変形してウェーハ外周部の研磨圧力のばら
つきを低減する効果があるため、リングの圧力Ｐｒがよ
り大きいことが望ましいが、リングの圧力Ｐｒが大きい
ほど研磨パッドの磨滅も大きくなる。そこで、本実施例
ではリング圧力Ｐｒを研磨圧力の２倍の７０ｋＰａとし
た。When the polishing pad is pressed with a ring,
Since the polishing pad is deformed and has the effect of reducing the variation in polishing pressure at the outer peripheral portion of the wafer, it is desirable that the pressure Pr of the ring is higher. However, the greater the pressure Pr of the ring, the greater the wear of the polishing pad. Therefore, in this embodiment, the ring pressure Pr is set to 70 kPa, which is twice the polishing pressure.
【００３３】図６は、層間絶縁膜に対する化学的・機械
的な研磨加工において、本発明に係るウェーハ外周部の
研磨圧力分布を制御し、研磨中にウェーハ外周に設けた
砥石で研磨パッドをドレッシングする場合の実施例と、
ウェーハ外周部での研磨圧力の制御と研磨パッドのドレ
ッシングなしの場合の比較例とを研磨後の絶縁膜の外周
部での厚さ分布について比較したものである。FIG. 6 shows that in the chemical and mechanical polishing of the interlayer insulating film, the polishing pressure distribution on the outer peripheral portion of the wafer according to the present invention is controlled, and the polishing pad is dressed with a grindstone provided on the outer peripheral portion of the wafer during polishing. When the embodiment,
The thickness distribution of the insulating film after polishing is compared between the control of the polishing pressure at the outer peripheral portion of the wafer and the comparative example without dressing of the polishing pad.
【００３４】図中、（ａ）は、ウェーハ外周部の研磨圧
力分布を制御し、研磨中にウェーハ外周に設けた砥石で
研磨パッドをドレッシングした場合の比較例としての実
験結果を示す。（ａ）は、プラズマＴＥＯＳ膜（１．５
μm堆積）に対して残膜厚さが０．５μmまで化学的・機
械的研磨加工を施したところ、ウェーハ半径が６０ｍｍ
から７３ｍｍまでの範囲で絶縁膜の厚さばらつきが±２
％であったことを示す。また、ウェーハ最外周部におい
て絶縁膜が残っており、基板が露出しないことを示す。In the figure, (a) shows an experimental result as a comparative example in which the polishing pressure distribution on the outer peripheral portion of the wafer is controlled and the polishing pad is dressed with a grindstone provided on the outer peripheral portion of the wafer during polishing. (A) shows a plasma TEOS film (1.5
Chemical and mechanical polishing was performed to a residual film thickness of 0.5 μm on the
Thickness variation of insulating film in the range of
%. In addition, the insulating film remains at the outermost peripheral portion of the wafer, indicating that the substrate is not exposed.
【００３５】図６中、（ｂ）は、ウェーハ外周部での研
磨圧力の制御と研磨パッドのドレッシングなしの場合の
実施例としての実験結果を示す。（ｂ）は、プラズマＴ
ＥＯＳ膜（１．５μm堆積）に対してウェーハ全体での
残膜厚さの平均値が０．４μmまで化学的・機械的研磨
加工を施したところ、ウェーハ半径が６０ｍｍから７０
ｍｍまでの範囲で絶縁膜の厚さばらつきが±６％であ
り、ウェーハ半径が６０ｍｍから７３ｍｍまでの範囲で
絶縁膜の厚さばらつきが±１４％であったことを示す。
また、ウェーハ最外周部半径７４ｍｍから７５ｍｍの範
囲で絶縁膜が残っておらず、基板が露出していることを
示す。FIG. 6B shows the experimental results as an example in the case where the polishing pressure is controlled at the outer peripheral portion of the wafer and the dressing of the polishing pad is not performed. (B) shows the plasma T
When the EOS film (1.5 μm deposition) was chemically and mechanically polished until the average value of the remaining film thickness of the entire wafer was 0.4 μm, the wafer radius was changed from 60 mm to 70 mm.
It shows that the thickness variation of the insulating film was ± 6% in the range up to mm, and ± 14% in the range of the wafer radius from 60 mm to 73 mm.
In addition, the insulating film does not remain in the range of the outermost radius of the wafer from 74 mm to 75 mm, indicating that the substrate is exposed.
【００３６】図７は、層間絶縁膜に対する化学的・機械
的な研磨加工において、本発明に係るウェーハ外周部の
研磨圧力分布を制御し、研磨中にウェーハ外周に設けた
砥石で研磨パッドをドレッシングする場合の実施例と、
ウェーハ外周部での研磨圧力の制御と研磨パッドのドレ
ッシングなしの場合の比較例とを研磨後の絶縁膜の半径
方向での厚さ分布について比較したものである。FIG. 7 shows that in the chemical / mechanical polishing of the interlayer insulating film, the polishing pressure distribution on the outer periphery of the wafer according to the present invention is controlled, and the polishing pad is dressed with a grindstone provided on the outer periphery of the wafer during polishing. When the embodiment,
This is a comparison of the control of the polishing pressure at the outer peripheral portion of the wafer and the comparative example without dressing of the polishing pad with respect to the thickness distribution in the radial direction of the polished insulating film.
【００３７】図中、（ａ）は、ウェーハ外周部の研磨圧
力分布を制御し、研磨中にウェーハ外周に設けた砥石で
研磨パッドをドレッシングした場合の比較例としての実
験結果を示す。（ａ）は、プラズマＴＥＯＳ膜（１．５
μm堆積）に対して残膜厚さが０．５μmまで化学的・機
械的研磨加工を施したところ、ウェーハ半径が７０ｍｍ
及び７３ｍｍまでの範囲で絶縁膜の厚さばらつきが共に
±３％であったことを示す。また、ウェーハ最外周部に
おいて絶縁膜が残っており、基板が露出しないことを示
す。In the figure, (a) shows an experimental result as a comparative example when the polishing pressure distribution on the outer peripheral portion of the wafer is controlled and the polishing pad is dressed with a grindstone provided on the outer peripheral portion of the wafer during polishing. (A) shows a plasma TEOS film (1.5
Chemical and mechanical polishing was performed to a residual film thickness of 0.5 μm on the
And that the variation in the thickness of the insulating film was ± 3% in the range up to 73 mm. In addition, the insulating film remains at the outermost peripheral portion of the wafer, indicating that the substrate is not exposed.
【００３８】図７中、（ｂ）は、ウェーハ外周部での研
磨圧力の制御と研磨パッドのドレッシングなしの場合の
実施例としての実験結果を示す。（ｂ）は、プラズマＴ
ＥＯＳ膜（１．５μm堆積）に対して残膜厚さの平均値
が０．４μmまで化学的・機械的研磨加工を施したとこ
ろ、ウェーハ半径が７０ｍｍまでの範囲で絶縁膜の厚さ
ばらつきが±１５％であり、ウェーハ半径が７３ｍｍま
での範囲で絶縁膜の厚さばらつきが±１９％であったこ
とを示す。また、ウェーハ最外周部で絶縁膜が残ってお
らず、基板が露出していることを示す。FIG. 7B shows an experimental result as an example in the case of controlling the polishing pressure at the outer peripheral portion of the wafer and without dressing the polishing pad. (B) shows the plasma T
When EOS film (1.5 μm deposition) was chemically and mechanically polished to an average value of remaining film thickness of 0.4 μm, the thickness variation of the insulating film was reduced up to a wafer radius of 70 mm. ± 15%, indicating that the thickness variation of the insulating film was ± 19% when the wafer radius was up to 73 mm. In addition, it shows that the insulating film does not remain at the outermost peripheral portion of the wafer and the substrate is exposed.
【００３９】化学的・機械的な研磨加工は、研磨後の絶
縁膜の研磨量ばらつきによって評価した。評価は光干渉
式の薄膜厚さ計を用いて半導体基板（ウエハ）の外周部
では１６箇所、直径方向では３１箇所の絶縁膜の厚さを
測定した。そして、絶縁膜の厚さの最大値をＴｍａｘ、
最小値をＴｍｉｎ、平均値をＴａｖｅとしたとき、膜厚
ばらつきＶを、次に示す（数１）から算出した。The chemical and mechanical polishing was evaluated by the variation in the polishing amount of the insulating film after polishing. For the evaluation, the thickness of the insulating film was measured at 16 locations on the outer peripheral portion of the semiconductor substrate (wafer) and at 31 locations in the diameter direction using a light interference type thin film thickness gauge. Then, the maximum value of the thickness of the insulating film is defined as Tmax,
When the minimum value was Tmin and the average value was Tave, the film thickness variation V was calculated from the following (Equation 1).
【００４０】[0040]
【数１】 (Equation 1)
【００４１】これらの各実験結果を示す図７及び図８か
ら分かるように、比較例に比べて本発明のように基板の
外周部の研磨圧力を改善することによって、また、研磨
中に研磨パッドをドレッシングすることによって研磨前
に絶縁膜の表面に存在した１μmの段差を、研磨後に
０．１μm以下にすることができた。この値は、この層
間絶縁膜上に０．２５μm以下の配線幅を有する配線を
形成することを可能にする値である。As can be seen from FIGS. 7 and 8, which show the results of these experiments, the polishing pressure at the outer peripheral portion of the substrate is improved as in the present invention as compared with the comparative example, and the polishing pad during polishing is improved. By dressing, the step of 1 μm existing on the surface of the insulating film before polishing could be reduced to 0.1 μm or less after polishing. This value allows a wiring having a wiring width of 0.25 μm or less to be formed on the interlayer insulating film.
【００４２】次に、本発明に係る研磨パッドを加圧して
被加工物の外周の研磨圧力を改善し、研磨パッドのドレ
ッシングを行う化学的・機械的な研磨加工方法を適用し
て、６インチのシリコン基板上に２層のアルミ配線構造
を持つ半導体装置を製造した実施例について、図８を用
いて説明する。Next, the polishing pad according to the present invention is pressurized to improve the polishing pressure on the outer periphery of the workpiece, and a chemical and mechanical polishing method for dressing the polishing pad is applied to form a 6-inch polishing pad. An example of manufacturing a semiconductor device having a two-layer aluminum wiring structure on a silicon substrate will be described with reference to FIG.
【００４３】すなわち、４２は半導体基板（６インチの
シリコン基板）上に１層目のアルミ配線を形成する工程
である。４３は工程４２で形成された１層目のアルミ配
線上に例えばプラズマＴＥＯＳ膜（層間絶縁膜）をＣＶ
Ｄにより１．５μm程度の厚さに堆積（成膜）する工程
である。４４は工程４３で堆積された例えば１．５μm
厚さのプラズマＴＥＯＳ膜の表面を、前記本発明の実施
の形態で説明した通り、基板の外周部の研磨圧力を改善
して化学的・機械的な研磨加工を行って表面を平坦化す
る工程である。この工程４４で１μm研磨した結果、プ
ラズマＴＥＯＳ膜の厚さ分布を光干渉式の薄膜厚さ測定
器を用いて測定したところ、厚さが０．５μm±０．０
１３μm（膜厚さのばらつきが±２．６％）であること
を確認した。このとき、プラズマＴＥＯＳ膜を堆積した
後にプラズマＴＥＯＳ膜の表面に存在した１μmの段差
について、触針式の段差測定器による測定とウエハの断
面のＳＥＭ観察を行い、段差が１μmから０．１μm以下
に低減されたことを確認した。また、接触式の表面粗さ
計及び原子間力顕微鏡を用いて、研磨したプラズマＴＥ
ＯＳ膜の表面粗さを測定し、プラズマＴＥＯＳ膜の表面
粗さが０．２ないし０．３ｎｍＲｍａｘであることを確
認した。That is, reference numeral 42 denotes a step of forming a first-layer aluminum wiring on a semiconductor substrate (6-inch silicon substrate). 43, a plasma TEOS film (interlayer insulating film) is formed on the first-layer aluminum wiring formed in the step 42 by CV.
This is a step of depositing (forming a film) a thickness of about 1.5 μm by D. 44 is, for example, 1.5 μm deposited in step 43
As described in the embodiment of the present invention, the surface of the plasma TEOS film having a thickness is improved by polishing the outer peripheral portion of the substrate and is subjected to chemical and mechanical polishing to flatten the surface. It is. As a result of polishing by 1 μm in this step 44, when the thickness distribution of the plasma TEOS film was measured using an optical interference type thin film thickness measuring instrument, the thickness was 0.5 μm ± 0.0
It was confirmed that the thickness was 13 μm (the thickness variation was ± 2.6%). At this time, a step of 1 μm existing on the surface of the plasma TEOS film after the plasma TEOS film was deposited was measured by a stylus-type step measuring instrument and a SEM observation of a cross section of the wafer was performed, and the step was 1 μm to 0.1 μm or less. It was confirmed that it was reduced to. In addition, using a contact type surface roughness meter and an atomic force microscope, the polished plasma TE
The surface roughness of the OS film was measured, and it was confirmed that the surface roughness of the plasma TEOS film was 0.2 to 0.3 nmRmax.
【００４４】４５は研磨したプラズマＴＥＯＳ膜の表面
に厚さ０．１μmのＳｉＯ２膜をＣＶＤで堆積（成膜）
する工程である。４６は工程４５で堆積したＳｉＯ２膜
に対して下層アルミ配線と電気接続をとるためのコンタ
クトホールをエッチングによって形成する工程である。
４７は工程４６で形成されたコンタクトホールにタング
ステン等からなる導電体のコンタクトビアを形成する工
程である。４８は工程４５で成膜されたＳｉＯ２膜の表
面に幅０．２５μmのアルミ上層配線を形成する工程で
ある。Numeral 45 indicates that a 0.1 μm-thick SiO 2 film is deposited (formed) on the surface of the polished plasma TEOS film by CVD.
This is the step of performing Step 46 is a step of forming a contact hole for making electrical connection with the lower aluminum wiring in the SiO2 film deposited in step 45 by etching.
47 is a step of forming a conductive contact via made of tungsten or the like in the contact hole formed in step 46. Reference numeral 48 denotes a step of forming an aluminum upper layer wiring having a width of 0.25 μm on the surface of the SiO 2 film formed in the step 45.
【００４５】以上説明した工程４２〜４８によって６イ
ンチのシリコン基板上に２層のアルミ配線構造を持つ半
導体装置を製造することができる。このように半導体装
置を製造し、コンタクトビア抵抗及び配線抵抗を測定し
た結果、コンタクト抵抗不良及び配線不良がないことが
分かり、信頼性の高い半導体装置を製造することができ
た。By the steps 42 to 48 described above, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate can be manufactured. As described above, the semiconductor device was manufactured and the contact via resistance and the wiring resistance were measured. As a result, it was found that there was no contact resistance failure and no wiring failure, and a highly reliable semiconductor device could be manufactured.
【００４６】次に本発明に係る研磨パッドを加圧して被
加工物の外周の研磨圧力を改善し、研磨パッドのドレッ
シングを行う化学的・機械的な研磨加工方法を適用し
て、半導体基板上に２層の配線構造を持つ半導体装置を
製造した実施例について、図９を用いて説明する。Next, the polishing pad according to the present invention is pressurized to improve the polishing pressure on the outer periphery of the workpiece, and a chemical / mechanical polishing method for dressing the polishing pad is applied to a semiconductor substrate. Next, an embodiment in which a semiconductor device having a two-layer wiring structure is manufactured will be described with reference to FIG.
【００４７】すなわち、４９は半導体基板上に下層配線
を形成する工程である。５０は工程４９で形成された下
層配線上に例えばプラズマＴＥＯＳ膜をＣＶＤにより
１．５μm程度の厚さに堆積（成膜）する工程である。
５１は工程５０で堆積された例えば１．５μm程度の厚
さのＴＥＯＳ膜（層間絶縁膜）の表面を、前記本発明の
実施の形態で説明した通り、基板の外周部の研磨圧力を
改善して化学的・機械的な研磨加工を行って表面を平坦
化する行程である。この行程５１で１μm研磨加工した
結果、図６ないし図７に示す実施例と同様に、厚さが
０．５μm±０．０１３μm（膜厚さのばらつきが±２．
６％）で膜厚さのばらつきを±３％以下にして、段差
（微小凹凸）を０．１μm以下に低減させて平坦化する
ことができる。プラズマＴＥＯＳ膜の表面粗さを０．２
ないし０．３ｎｍＲｍａｘにすることができる。That is, step 49 is a step of forming a lower wiring on a semiconductor substrate. Step 50 is a step of depositing (forming) a plasma TEOS film to a thickness of about 1.5 μm by CVD on the lower wiring formed in step 49.
Reference numeral 51 denotes a surface of the TEOS film (interlayer insulating film) having a thickness of, for example, about 1.5 μm, deposited in the step 50, for improving the polishing pressure on the outer peripheral portion of the substrate as described in the embodiment of the present invention. This is a step of flattening the surface by performing chemical and mechanical polishing. As a result of polishing at 1 μm in this step 51, as in the embodiment shown in FIGS. 6 and 7, the thickness is 0.5 μm ± 0.013 μm (the variation in film thickness is ± 2.
6%), the variation in film thickness can be reduced to ± 3% or less, and the level difference (small unevenness) can be reduced to 0.1 μm or less for flattening. Plasma TEOS film surface roughness of 0.2
To 0.3 nmRmax.
【００４８】５２は５１で表面が平坦化され、所望の膜
厚に研磨されたプラズマＴＥＯＳ膜に対して下層配線と
電気的接続をとるためのコンタクトホールをエッチング
によって形成する工程である。５３は工程５２で形成さ
れたコンタクトホールに対して選択ＣＶＤによりタング
ステン等からなる導電体のコンタクトスタッドを形成す
る工程である。５４は工程４４と同様に基板の外周の研
磨圧力を改善し、研磨パッドを目立てて化学的・機械的
な研磨加工を行って表面に成長したタングステン等の金
属膜を除去する工程である。５５はプラズマＴＥＯＳ膜
（層間絶縁膜）の表面に上層配線を形成する工程であ
る。Reference numeral 52 denotes a step of forming a contact hole for making an electrical connection with a lower wiring in the plasma TEOS film whose surface is flattened and polished to a desired thickness by 51. 53 is a step of forming a conductive contact stud made of tungsten or the like by selective CVD in the contact hole formed in step 52. A step 54 is a step of improving the polishing pressure on the outer periphery of the substrate similarly to the step 44, removing the metal film such as tungsten grown on the surface by performing a chemical / mechanical polishing process with the polishing pad being sharpened. Reference numeral 55 denotes a step of forming an upper wiring on the surface of the plasma TEOS film (interlayer insulating film).
【００４９】以上説明した工程４９〜５５によって半導
体基板上に多層配線構造を持つ半導体装置を製造するこ
とができる。このように半導体装置を製造し、コンタク
トスタッド抵抗及び配線抵抗を測定した結果、コンタク
ト不良及び配線不良がないことが分かり、信頼性の高い
半導体装置を製造することができる。By the steps 49 to 55 described above, a semiconductor device having a multilayer wiring structure on a semiconductor substrate can be manufactured. As a result of manufacturing the semiconductor device and measuring the contact stud resistance and the wiring resistance, it is found that there is no contact failure and no wiring failure, and a highly reliable semiconductor device can be manufactured.
【００５０】また、半導体装置の製造プロセスの過程で
形成された絶縁膜は例えば図１０（ａ）のように同心円
状に分布することが多いため、図１０（ｂ）に示すよう
にチップ内のＣＭＰが行われていない絶縁膜の厚さを測
定し厚さの等高線を求めると、等高線の曲率はウェーハ
上の半径ｒを表すため、チップに切断された後でも、チ
ップ内の絶縁膜の厚さ分布を測定すればチップの作られ
た半径位置が分かる。例えば６インチウェーハではチッ
プが半径７０ｍｍよりも外周に作られている場合にも容
易に分かる。Also, the insulating film formed in the course of the manufacturing process of the semiconductor device is often distributed concentrically, for example, as shown in FIG. 10A, and therefore, as shown in FIG. When the thickness of the insulating film not subjected to the CMP is measured and the contour of the thickness is obtained, the curvature of the contour represents the radius r on the wafer. By measuring the depth distribution, the radial position where the tip was made can be determined. For example, in the case of a 6-inch wafer, it can be easily understood even when the chips are formed on the outer periphery with a radius of more than 70 mm.
【００５１】また、図４に示す装置を用いた研磨方法で
も上記と同様の研磨条件を用いた。砥粒の突き出し量ｈ
を４０μm以下とした場合には研磨パッドの目立てが十
分に行われなかった。また、ｈを５０μmより大きくし
た場合、絶縁膜表面の段差が十分に低減できなかった。
そこで、本実施例では砥粒の突き出し量ｈを５０μmと
した。その結果、図２に示す装置を用いた研磨方法と同
等の結果を得た。In the polishing method using the apparatus shown in FIG. 4, the same polishing conditions as described above were used. Amount of protrusion of abrasive grains h
Was less than 40 μm, the polishing pad was not sharpened sufficiently. When h was larger than 50 μm, the step on the surface of the insulating film could not be sufficiently reduced.
Therefore, in this embodiment, the protrusion amount h of the abrasive grains is set to 50 μm. As a result, a result equivalent to that of the polishing method using the apparatus shown in FIG. 2 was obtained.
【００５２】また本発明は、薄膜多層配線基板を製造す
るのに適用することができる。Further, the present invention can be applied to manufacture a thin film multilayer wiring board.
【００５３】[0053]
【発明の効果】本発明によれば、化学的・機械的な研磨
加工において、研磨中に基板の外周部の研磨圧力分布を
制御して、絶縁膜や金属膜などの厚さを均一に、しかも
平坦に（例えば、膜厚さのばらつきを±３％以下で、し
かも微小凹凸を０．１μm以下）加工できるため、例え
ば半導体装置の高信頼化及び高集積化を図ることができ
る効果がある。According to the present invention, in the chemical / mechanical polishing process, the polishing pressure distribution on the outer peripheral portion of the substrate is controlled during polishing so that the thickness of the insulating film, the metal film, and the like can be made uniform. In addition, since it can be processed flat (for example, a variation in film thickness is ± 3% or less, and fine irregularities are 0.1 μm or less), for example, there is an effect that high reliability and high integration of a semiconductor device can be achieved. .
【図１】本発明に係る化学的・機械的な研磨加工装置の
一実施例の形態を示す概念図である。FIG. 1 is a conceptual diagram showing an embodiment of a chemical and mechanical polishing apparatus according to the present invention.
【図２】図１に示す基板を支持するチャックの説明図で
ある。FIG. 2 is an explanatory diagram of a chuck that supports the substrate shown in FIG.
【図３】図１に示す研磨定盤上の被加工物を支持するチ
ャック部の説明図であり、（ａ）は本発明を用いた場合
の研磨方法を説明するための図、（ｂ）は本発明を用い
ない場合の研磨方法を説明するための図である。3A and 3B are explanatory diagrams of a chuck portion for supporting a workpiece on the polishing platen shown in FIG. 1, wherein FIG. 3A is a diagram for explaining a polishing method when the present invention is used, and FIG. FIG. 3 is a diagram for explaining a polishing method when the present invention is not used.
【図４】本発明に係る化学的・機械的な研磨加工装置の
他の一実施例の形態を示す概念図である。FIG. 4 is a conceptual diagram showing another embodiment of the chemical and mechanical polishing apparatus according to the present invention.
【図５】図４に示す基板の外周部分を支持するチャック
の説明図である。FIG. 5 is an explanatory diagram of a chuck that supports an outer peripheral portion of the substrate shown in FIG.
【図６】被加工物の外周部の研磨後の絶縁膜厚さを示す
図であり、（ａ）は本発明を用いた場合の研磨方法によ
る効果を説明するための図、（ｂ）は本発明を用いない
場合の研磨結果を説明するための図である。6A and 6B are diagrams showing the thickness of the insulating film after polishing of the outer peripheral portion of the workpiece, where FIG. 6A is a diagram for explaining the effect of the polishing method when the present invention is used, and FIG. FIG. 9 is a diagram for explaining a polishing result when the present invention is not used.
【図７】被加工物の研磨後の面内の絶縁膜厚さの分布を
示す図であり、（ａ）は本発明を用いた場合の効果を本
発明の研磨方法による効果を説明するための図、（ｂ）
は本発明を用いない場合の研磨結果を説明するための図
である。FIGS. 7A and 7B are diagrams showing the distribution of the thickness of an insulating film in a surface of a workpiece after polishing, and FIG. 7A is a view for explaining the effect of the present invention and the effect of the polishing method of the present invention; Figure of (b)
FIG. 4 is a diagram for explaining a polishing result when the present invention is not used.
【図８】本発明に係る半導体装置を製造するための一実
施例である工程フローを示す図である。FIG. 8 is a view showing a process flow as an embodiment for manufacturing a semiconductor device according to the present invention.
【図９】本発明に係る半導体装置を製造するための他の
一実施例である工程フローを示す図である。FIG. 9 is a view showing a process flow as another embodiment for manufacturing a semiconductor device according to the present invention.
【図１０】本発明を用いた場合の研磨方法による効果を
説明するための図である。FIG. 10 is a diagram for explaining the effect of the polishing method when the present invention is used.
１・・・半導体基板、２・・・支持体、３・・・剛体、
４・・・チャック本体、５・・・窪みＡ、６・・・袋
Ａ、７・・・窪みＢ、８・・・袋Ｂ、９・・・窪みＣ、
１０・・・袋Ｃ、１１・・・リング、１２・・・砥石、
１２Ａ・・・砥石台、１２Ｂ・・・砥石、１２Ｃ・・・
砥粒、１３・・・定盤、１４・・・研磨パッド、１５・
・・研磨剤供給管、１６・・・研磨剤、１７・・・気体
供給通路Ａ、１８・・・気体供給通路Ｂ、１９・・・気
体供給通路Ｃ、２０・・・スリップリング、２１・・・
チャック回転軸、２２・・・チャック回転用モータ及び
減速機、２３・・・エアシリンダ軸、２４・・・エアシ
リンダ、２５・・・研磨機基部、２６・・・ストッパ、
２７・・・エアシリンダ、２８・・・定盤回転モータ及
び減速機、２９・・・ベース、３０・・・往復テーブ
ル、３１・・・ベースの可動方向、３２・・・ストッパ
の可動方向、３３・・・往復テーブルの可動方向、３４
・・・砥石、３５・・・窪みＤ、３６・・・袋Ｄ、３７
・・・砥石、３７Ａ・・・ベース、３７Ｂ・・・砥石
台、３７Ｃ・・・リング、３８・・・スペーサ、３９・
・・ネジ、４０・・・砥石、４１・・・砥粒、４２・・
・下層配線を形成する工程、４３・・・ＴＥＯＳ膜をＣ
ＶＤで成膜する工程、４４・・・化学的・機械的な研磨
によりＴＥＯＳ膜を平坦化する工程、４５・・・コンタ
クトホールをエッチングにより形成する工程、４６・・
・ＴＥＯＳ膜の表面にＳｉＯ２膜を形成する工程、４７
・・・コンタクトビアを形成する工程、４８・・・上層
配線を形成する工程、４９・・・下層配線を形成する工
程、５０・・・層間絶縁膜を形成する工程、５１・・・
化学的・機械的な研磨により層間絶縁膜を平坦化する工
程、５２・・・コンタクトホールをエッチングにより形
成する工程、５３・・・選択ＣＶＤによりコンタクトス
タッドを形成する工程、５４・・・化学的・機械的な研
磨により層間絶縁膜上に成長した金属膜を除去する工
程、５５・・・上層配線を形成する工程DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Support body, 3 ... Rigid body,
4 chuck body, 5 recess A, 6 bag A, 7 recess B, 8 bag B, 9 recess C,
10 ... bag C, 11 ... ring, 12 ... whetstone,
12A: Grindstone, 12B: Grindstone, 12C ...
Abrasive grains, 13: Surface plate, 14: Polishing pad, 15.
..Abrasive supply pipe, 16 ... Abrasive, 17 ... Gas supply passage A, 18 ... Gas supply passage B, 19 ... Gas supply passage C, 20 ... Slip ring, 21 ...・ ・
Chuck rotating shaft, 22: chuck rotating motor and reducer, 23: air cylinder shaft, 24: air cylinder, 25: polishing machine base, 26: stopper,
27 ... air cylinder, 28 ... surface plate rotating motor and reduction gear, 29 ... base, 30 ... reciprocating table, 31 ... moving direction of base, 32 ... moving direction of stopper, 33 ... movable direction of the reciprocating table, 34
... Whetstone, 35 ... Dent D, 36 ... Bag D, 37
... Whetstone, 37A ... Base, 37B ... Whetstone table, 37C ... Ring, 38 ... Spacer, 39
..Screws, 40: grinding stones, 41: abrasive grains, 42 ...
・ Step of forming lower wiring, 43 ... Changing TEOS film
Step of forming a film by VD, 44 ... Step of flattening the TEOS film by chemical / mechanical polishing, 45 ... Step of forming a contact hole by etching, 46 ...
A step of forming a SiO 2 film on the surface of the TEOS film, 47
... step of forming contact via, 48 ... step of forming upper layer wiring, 49 ... step of forming lower layer wiring, 50 ... step of forming interlayer insulating film, 51 ...
Step of planarizing the interlayer insulating film by chemical / mechanical polishing, 52: Step of forming contact holes by etching, 53: Step of forming contact studs by selective CVD, 54: Chemical A step of removing a metal film grown on the interlayer insulating film by mechanical polishing, 55 ... a step of forming an upper wiring
フロントページの続き (72)発明者 小島 弘之 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 漆原 真理子 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内Continued on the front page (72) Inventor Hiroyuki Kojima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd.Production Technology Research Institute (72) Inventor Mariko Urushihara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Inside the Production Engineering Laboratory
Claims (11)
パッド面に押圧し、前記基板上の絶縁膜表面に対して化
学的・機械的な研磨加工を行うことを特徴とする化学的
・機械的な研磨加工方法。1. A chemical polishing method comprising: pressing a grindstone placed adjacent to the outer periphery of a substrate against a polishing pad surface; and performing chemical and mechanical polishing on the surface of the insulating film on the substrate.・ Mechanical polishing method.
の接触部分を被覆した砥石を基板の外周に隣接して設置
し、該砥石を研磨パッド面に押圧し、前記基板上の絶縁
膜表面に対して化学的・機械的な研磨加工を行うことを
特徴とする化学的・機械的な研磨加工方法。2. A grinding wheel having a resin or a resin-containing material covering a contact portion with a substrate is installed adjacent to an outer periphery of the substrate, and the grinding stone is pressed against a polishing pad surface to form an insulating film on the substrate. A chemical / mechanical polishing method characterized by performing a chemical / mechanical polishing process on a workpiece.
縦弾性係数の小さい樹脂あるいは樹脂を含有する材料で
構成されたリングを研磨パッド面に押圧し、リングの外
周に隣接して設置した砥石を研磨パッドに押圧し、前記
基板上の絶縁膜表面に対して化学的・機械的な研磨加工
を行うことを特徴とする化学的・機械的な研磨加工方
法。3. A ring made of a resin or a resin-containing material having a smaller longitudinal elastic modulus than the substrate is pressed against the surface of the polishing pad, and is placed adjacent to the outer periphery of the substrate. A chemical / mechanical polishing method comprising: pressing an installed whetstone against a polishing pad; and performing chemical / mechanical polishing on the surface of the insulating film on the substrate.
縦弾性係数の小さい樹脂あるいは樹脂を含有する材料で
構成されたリングを研磨パッド面に押圧し、リングの外
周に隣接して設置した砥石を研磨パッドに押圧し、前記
基板上の絶縁膜表面に対して化学的・機械的な研磨加工
を行う場合に上記リングと砥石の研磨パッドへの押圧力
と研磨圧力とを独立して設定することを特徴とする化学
的・機械的な研磨加工方法。4. A ring made of a resin or a material containing a resin having a smaller longitudinal modulus than the substrate is pressed against the surface of the polishing pad, and is placed adjacent to the outer periphery of the substrate. When the installed grindstone is pressed against the polishing pad, and when the chemical and mechanical polishing is performed on the insulating film surface on the substrate, the pressing force and the polishing pressure of the ring and the grindstone on the polishing pad are independent. Chemical and mechanical polishing method characterized by setting.
パッド面に押圧し、基板上の金属膜表面に対して化学的
・機械的な研磨加工を行うことを特徴とする化学的・機
械的な研磨加工方法。5. A chemical / mechanical polishing method comprising: pressing a grindstone disposed adjacent to an outer periphery of a substrate against a polishing pad surface to perform a chemical / mechanical polishing process on a metal film surface on the substrate. Mechanical polishing method.
御できる手段と研磨パッドの表面を目立てる手段を備
え、上記基板上の絶縁膜表面の研磨量ばらつきを±３％
以下で、該絶縁膜表面の凹凸を０．１μm以下に化学的
・機械的な研磨加工を行うことを特徴とする化学的・機
械的な研磨加工方法。6. A polishing pad comprising means for controlling the distribution of the polishing pressure in the outer peripheral portion of the substrate and means for sharpening the surface of the polishing pad, wherein the variation in the polishing amount on the surface of the insulating film on the substrate is ± 3%.
A chemical / mechanical polishing method comprising the steps of: performing a chemical / mechanical polishing process to make the surface of the insulating film uneven to 0.1 μm or less.
磨パッドと、 研磨機に固定され、上下動可能な上下可動機構と、 該上下可動機構の先端に、基板を保持する基板保持機構
と環状の砥石を基板に隣接して設置し該砥石を研磨パッ
ドに加圧する砥石加圧機構とを有することを特徴とする
化学的・機械的な研磨加工を行う研磨装置。7. A polishing pad fixed on a polishing platen for polishing a substrate, a vertically movable mechanism fixed to a polishing machine and capable of moving up and down, and a substrate holding a substrate at a tip of the vertically movable mechanism. A polishing apparatus for performing a chemical / mechanical polishing process, comprising: a holding mechanism and a whetstone pressing mechanism for placing an annular whetstone adjacent to a substrate and pressing the whetstone against a polishing pad.
特徴とする化学的・機械的な研磨加工を行う研磨装置。8. The polishing apparatus according to claim 7, wherein the pressing mechanism for the substrate and the pressing mechanism for the grindstone are independent of each other.
縁膜形成工程と、該層間絶縁膜形成工程で形成された層
間絶縁膜の外周部分の研磨圧力を制御し、研磨パッドの
表面を目立てて上記層間絶縁膜表面の化学的・機械的な
研磨加工を行って平坦化する化学的・機械的な研磨加工
工程と、該化学的・機械的な研磨加工工程で平坦化され
た上記層間絶縁膜上に所望の上層配線を形成する上層配
線形成工程を有することを特徴とする半導体基板の製造
方法。9. An interlayer insulating film forming step of forming an interlayer insulating film on a lower layer wiring, and a polishing pressure on an outer peripheral portion of the interlayer insulating film formed in the interlayer insulating film forming step is controlled so that a surface of the polishing pad is formed. A chemical-mechanical polishing process for flattening by chemically and mechanically polishing the surface of the interlayer insulating film, and the interlayer planarized by the chemical-mechanical polishing process. A method of manufacturing a semiconductor substrate, comprising an upper wiring forming step of forming a desired upper wiring on an insulating film.
絶縁膜形成工程と、該層間絶縁膜形成工程で形成された
層間絶縁膜の外周部分の研磨圧力を制御し、研磨パッド
の表面を目立てて上記層間絶縁膜表面の化学的・機械的
な研磨加工を行って平坦化する化学的・機械的な研磨加
工工程と、該化学的・機械的な研磨加工工程で平坦化さ
れた層間絶縁膜に対してコンタクトホールを形成するコ
ンタクトホール形成工程と、該コンタクトホール形成工
程で形成されたコンタクトホールに導電材を埋め込んで
コンタクトスタッドを形成するコンタクトスタッド形成
工程と、該コンタクトスタッド形成工程の後、上記層間
絶縁膜上に所望の上層配線を形成する上層配線形成工程
を有することを特徴とする半導体基板の製造方法。10. An inter-layer insulating film forming step of forming an inter-layer insulating film on a lower wiring, and a polishing pressure of an outer peripheral portion of the inter-layer insulating film formed in the inter-layer insulating film forming step is controlled so that a surface of the polishing pad is formed. A chemical / mechanical polishing process for flattening the surface of the interlayer insulating film by chemical / mechanical polishing, and an interlayer insulating flattened by the chemical / mechanical polishing process A contact hole forming step of forming a contact hole in the film, a contact stud forming step of forming a contact stud by embedding a conductive material in the contact hole formed in the contact hole forming step, and after the contact stud forming step And a method of forming a desired upper layer wiring on the interlayer insulating film.
絶縁膜形成工程と、該層間絶縁膜形成工程で形成された
層間絶縁膜の外周部分の研磨圧力を制御し、研磨パッド
の表面を目立てて上記層間絶縁膜表面の化学的・機械的
な研磨加工を行って平坦化する化学的・機械的な研磨加
工工程と、該化学的・機械的な研磨加工工程で平坦化さ
れた上記層間絶縁膜上ＳｉＯ２膜をＣＶＤによって形成
するＳｉＯ２膜形成工程と、該ＳｉＯ２膜形成工程で形
成されたＳｉＯ２膜上に上層配線を形成する上層配線形
成工程とを有することを特徴とする半導体基板の製造方
法。11. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring, and a polishing pressure on an outer peripheral portion of the interlayer insulating film formed in the interlayer insulating film forming step is controlled to reduce the surface of the polishing pad. A chemical-mechanical polishing process for flattening by chemically and mechanically polishing the surface of the interlayer insulating film, and the interlayer planarized by the chemical-mechanical polishing process. A method of manufacturing a semiconductor substrate, comprising: a SiO2 film forming step of forming a SiO2 film on an insulating film by CVD; and an upper wiring forming step of forming an upper wiring on the SiO2 film formed in the SiO2 film forming step. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890496A JP3610676B2 (en) | 1996-06-11 | 1996-06-11 | Chemical and mechanical polishing method and apparatus, and semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890496A JP3610676B2 (en) | 1996-06-11 | 1996-06-11 | Chemical and mechanical polishing method and apparatus, and semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10553A true JPH10553A (en) | 1998-01-06 |
| JP3610676B2 JP3610676B2 (en) | 2005-01-19 |
Family
ID=15463276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14890496A Expired - Fee Related JP3610676B2 (en) | 1996-06-11 | 1996-06-11 | Chemical and mechanical polishing method and apparatus, and semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3610676B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567027A (en) * | 1983-07-19 | 1986-01-28 | Metallurgie Hoboken-Overpelt | Process for defluorinating an acid sulphate solution |
| CN105479325A (en) * | 2015-12-30 | 2016-04-13 | 天通吉成机器技术有限公司 | Partition pressing device and method suitable for large single-face grinding polishing device |
-
1996
- 1996-06-11 JP JP14890496A patent/JP3610676B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567027A (en) * | 1983-07-19 | 1986-01-28 | Metallurgie Hoboken-Overpelt | Process for defluorinating an acid sulphate solution |
| CN105479325A (en) * | 2015-12-30 | 2016-04-13 | 天通吉成机器技术有限公司 | Partition pressing device and method suitable for large single-face grinding polishing device |
| CN105479325B (en) * | 2015-12-30 | 2018-04-17 | 天通吉成机器技术有限公司 | A kind of subregion pressue device and method suitable for large-scale single side polishing grinding equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3610676B2 (en) | 2005-01-19 |
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