JPH1050930A - Multichip mounting method - Google Patents
Multichip mounting methodInfo
- Publication number
- JPH1050930A JPH1050930A JP8206876A JP20687696A JPH1050930A JP H1050930 A JPH1050930 A JP H1050930A JP 8206876 A JP8206876 A JP 8206876A JP 20687696 A JP20687696 A JP 20687696A JP H1050930 A JPH1050930 A JP H1050930A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- electrodes
- electrode
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
- H01L2224/75101—Chamber
- H01L2224/7511—High pressure chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は複数個のチップ部品
の基板へのマルチチップ実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a plurality of chip components on a multi-chip substrate.
【０００２】[0002]
【従来の技術】半導体チップや電子部品の小型薄型化に
伴い、これらに用いる回路や電極は高密度、高精細化し
ている。このような微細電極の接続は、最近接着剤を用
いる方法が多用されるようになってきた。この場合、接
着剤中に導電粒子を配合し加圧により接着剤の厚み方向
に電気的接続を得るもの（例えば特開昭５５−１０４０
０７号公報）と、導電粒子を用いないで接続時の加圧に
より電極面の微細凹凸の直接接触により電気的接続を得
るもの（例えば特開昭６０−２６２４３０号公報）があ
る。接着剤を用いた接続方式は、比較的低温での接続が
可能であり、接続部はフレキシブルなことから信頼性に
優れ、加えてフィルム状もしくはテ−プ状接着剤を用い
た場合、一定厚みの長尺状で供給されることから実装ラ
インの自動化が図れる等から注目されている。近年、上
記方式を発展させて複数以上のチップ類を、比較的小形
の基板に高密度に実装するマルチチップモジュ−ル（Ｍ
ＣＭ）が注目されている。この場合、まず接着剤層を基
板全面に形成した後、セパレ−タのある場合にはこれを
剥離し、次いで基板電極とチップ電極を位置合わせし接
着接合することが一般的である。ＭＣＭに用いるチップ
類は、半導体チップ、能動素子、受動素子、抵抗、コン
デンサなどの多種類（以下チップ類）がある。2. Description of the Related Art As semiconductor chips and electronic components have become smaller and thinner, circuits and electrodes used for them have become higher in density and definition. For connection of such fine electrodes, a method using an adhesive has recently been frequently used. In this case, conductive particles are blended in the adhesive and an electrical connection is obtained in the thickness direction of the adhesive by pressing (for example, Japanese Patent Application Laid-Open No. 55-1040).
No. 07) and a method of obtaining electrical connection by direct contact of fine irregularities on the electrode surface by pressurization at the time of connection without using conductive particles (for example, JP-A-60-262430). The connection method using an adhesive allows connection at a relatively low temperature, and the connection part is flexible, so it has excellent reliability. In addition, when a film or tape adhesive is used, a constant thickness is used. It is attracting attention because it is possible to automate the mounting line because it is supplied in a long shape. In recent years, a multi-chip module (M) that develops the above method and mounts a plurality of chips at a high density on a relatively small substrate has been developed.
CM) is attracting attention. In this case, it is common practice to first form an adhesive layer on the entire surface of the substrate, peel off the separator, if any, and then align and bond the substrate electrode and chip electrode. There are many types of chips (hereinafter referred to as chips) such as a semiconductor chip, an active element, a passive element, a resistor, and a capacitor for the MCM.
【０００３】[0003]
【発明が解決しようとする課題】ＭＣＭに用いるチップ
類は多種類であり、それに応じてチップサイズ（面積、
高さ）は多くの種類となる。そのため基板への接着剤を
用いた接続の際に、基板との熱圧着法などで従来にない
問題点が生じている。例えばチップ高さの異なる場合や
基板の両面に実装する場合、従来一般的に行われていた
平行設置された金型を油圧や空気圧により圧締するプレ
ス法や、平行設置されたゴムや金属の加圧ロ−ルにより
圧締するいわゆるロ−ル法などでは、図３に示すように
チップ高さが異なると、加熱加圧が均一に行われない欠
点がある。すなわちこれらのプレス法やロ−ル法では金
型やロ−ル間で加圧し、例えば平行設置された定盤８と
加圧型９の間で加圧するために、チップ高さの異なる場
合（２、２ａ、２ｂや２´、２ａ´、２ｂ´）やチップ
を基板の両面に実装（２と、２´など）すると、加圧状
態が一定とならないため、電極間の接続が不十分となり
接続信頼性が得られない。特に基板の両面（３と３´
面）に実装する場合には、表裏でチップ位置が対象状態
に設置される場合が少ないことから、圧力むらのない均
一加圧が要求される微細電極の接合に適当な加圧する手
段もない状態である。本発明は上記欠点に鑑みなされた
もので、チップ高さの異なる場合や基板の両面に実装す
る場合に有効なマルチチップ実装法を提供する。There are many kinds of chips used for the MCM, and the chip size (area, area,
Height) can be of many types. For this reason, when connecting to the substrate using an adhesive, there is a problem that has not existed in the past by the thermocompression bonding method with the substrate. For example, when the chip height is different or when mounting on both sides of the board, the conventional method of pressing parallel mounted dies by hydraulic or pneumatic pressure, or the parallel mounting of rubber or metal The so-called roll method of pressing with a press roll has the disadvantage that heating and pressurization is not performed uniformly when the tip height is different as shown in FIG. That is, in these press methods and roll methods, pressure is applied between dies and rolls. For example, pressure is applied between the platen 8 and the press die 9 installed in parallel. , 2a, 2b or 2 ', 2a', 2b ') or a chip mounted on both sides of the substrate (2, 2', etc.), the pressurized state is not constant, so the connection between the electrodes becomes insufficient and the connection becomes insufficient. Reliability cannot be obtained. Especially on both sides of the substrate (3 and 3 '
In the case of mounting on the surface), there are few cases where the chip position is installed in the target state on the front and back, so there is no means for applying appropriate pressure for joining fine electrodes that requires uniform pressure without uneven pressure. It is. The present invention has been made in view of the above-described drawbacks, and provides a multi-chip mounting method that is effective when the chip height is different or when mounting is performed on both surfaces of a substrate.
【０００４】[0004]
【課題を解決するための手段】本発明は、基板上に複数
個のチップを実装する方法であって、基板上の電極形成
面とチップ電極間に接着剤を介在させ、基板の電極とこ
れに相対峙するチップの電極を位置合わせした状態で、
静水圧下で加熱することを特徴とするマルチチップ実装
法に関する。また、基板上に複数個のチップを実装する
方法であって、基板上の電極形成面とチップ電極間に接
着剤を介在させ、基板の電極とこれに相対峙するチップ
の電極を位置合わせした状態で導通検査を行った後、静
水圧下で加熱することを特徴とするマルチチップ実装法
に関する。SUMMARY OF THE INVENTION The present invention relates to a method of mounting a plurality of chips on a substrate, wherein an adhesive is interposed between an electrode forming surface on the substrate and the chip electrodes, and the electrodes of the substrate are connected to each other. With the electrodes of the chip facing each other aligned,
The present invention relates to a multi-chip mounting method characterized by heating under hydrostatic pressure. Also, a method of mounting a plurality of chips on a substrate, wherein an adhesive is interposed between the electrode forming surface on the substrate and the chip electrodes, and the electrodes of the substrate and the electrodes of the chip opposed to this are aligned. The present invention relates to a multichip mounting method characterized in that after conducting a continuity test in a state, heating is performed under hydrostatic pressure.
【０００５】[0005]
【発明の実施の形態】本発明を図面を参照しながら以下
説明する。図１は、基板１上の電極５の形成面と、複数
個のチップ２、２ａ、２ｂの電極４間に、接着剤３を介
在させ、相対峙するチップの電極を位置合わせした状態
を示す断面模式図である。基板１上の電極５の形成面
は、片面（図１）でも、図３のような両面でも良い。基
板１上の電極Ｂ５もしくはチップ２上の電極Ａ４は、い
ずれも配線回路をそのまま接続端子としても、あるいは
さらに突起状の電極を形成しても良い。電極４および／
または５が突起状であると、相対峙する電極間で加圧が
集中的に得られるため電気的な接続が容易なので好まし
い。接着剤３は、フィルム状でも、液状やペ−スト状で
もよい。接続すべき接着剤付きチップの電極と基板の電
極を位置合わせする方法は、接続すべき基板１の電極５
Ｂとチップ２の電極Ａ４とを、顕微鏡や、画像認識装置
を用いて位置合わせする。このとき位置合わせマ−クの
使用や併用も有効である。位置合わせ後の基板１とチッ
プ２の保持は、接着剤３の有する粘着性や、凝集力を用
いて仮接続することで可能である。またクリップや粘着
テ−プ等の補助手段も単独もしくは併用して適用でき
る。仮接続は加熱加圧がある程度であれば不均一でも良
いので、従来から用いられている熱圧着装置を用いるこ
とが可能である。この時また、接続すべき電極間で導通
検査を行うことも可能である。接着剤は、未硬化あるい
は硬化反応の不十分な状態で導通検査が可能なので、接
着剤のリペア作業（接続不良部を剥離し清浄化したのち
再接続する作業）が容易である。同様にしてチップ周囲
の、余剰接着剤を除去する工程を付加することも可能で
ある。この方法によれば、導通検査を終了した良好な接
続品を次に述べる密閉容器内で加熱加圧することで接着
剤の硬化反応を進めるので、不良品再生が少なく工程の
ロス時間が短い。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 shows a state in which an adhesive 3 is interposed between the surface of the substrate 1 on which the electrodes 5 are formed and the electrodes 4 of the plurality of chips 2, 2a, 2b, and the electrodes of the opposing chips are aligned. It is a cross section schematic diagram. The surface on which the electrode 5 is formed on the substrate 1 may be one side (FIG. 1) or both sides as shown in FIG. Either the electrode B5 on the substrate 1 or the electrode A4 on the chip 2 may use a wiring circuit as a connection terminal as it is, or may further form a protruding electrode. Electrode 4 and / or
Alternatively, it is preferable that the protrusion 5 has a protruding shape, since pressure can be intensively obtained between the electrodes facing each other, so that electrical connection is easy. The adhesive 3 may be in the form of a film, liquid, or paste. The method of aligning the electrode of the chip with the adhesive to be connected and the electrode of the substrate is as follows.
B and the electrode A4 of the chip 2 are aligned using a microscope or an image recognition device. At this time, the use and use of the alignment mark are also effective. The holding of the substrate 1 and the chip 2 after the alignment can be performed by temporary connection using the adhesiveness of the adhesive 3 or cohesive force. Auxiliary means such as clips and adhesive tapes may be used alone or in combination. The temporary connection may be non-uniform as long as the heating and pressurizing is to some extent, and therefore, a conventional thermocompression bonding apparatus can be used. At this time, it is also possible to conduct a continuity test between the electrodes to be connected. Since the continuity test can be performed on the adhesive in an uncured state or an insufficient curing reaction state, it is easy to repair the adhesive (operation for peeling off a defective connection portion, cleaning the defective portion, and then reconnecting the adhesive). Similarly, it is possible to add a step of removing excess adhesive around the chip. According to this method, since the curing reaction of the adhesive is promoted by heating and pressurizing a good connection product after the continuity test in a closed container described below, defective products are not regenerated and the process loss time is short.
【０００６】図２は、電極の位置合わせを終了したチッ
プの電極と基板の電極を、静水圧に耐えることが可能な
密閉容器６の内部に入れて加熱加圧し、同一基板に複数
個のチップの電気的接続を得る。密閉容器５としては、
圧力鍋、プレッシャクッカ、オ−トクレ−ブ等がある。
密閉容器６には吸排気孔７を設けることにより、加圧減
圧の操作が簡単であり、圧力制御も可能なことから好ま
しい。また図示してないが試料の出し入れ口を設けても
よい。本発明でいう静水圧とは、物体の外部表面に垂直
に一定の圧力が作用する状態を示す（図２のＰの矢印で
例示）。ここで図２を用いて接続構造体の表面積につい
て考察すると、一般的にチップ面積Ｓが２〜２０ｍｍ□
であるのに対して、接続部の厚みｔは０．１ｍｍ以下多
くは３０μｍ以下と、圧倒的にＳがｔより大きいことか
ら、接続部の厚み方向であるチップ面積Ｓにかかる圧力
が大きく、電極の接続方向の圧力が容易に得られる。FIG. 2 shows that the electrodes of the chip and the electrodes of the substrate for which the electrode alignment has been completed are placed in a sealed container 6 capable of withstanding hydrostatic pressure, and heated and pressurized. To obtain the electrical connection. As the closed container 5,
There are pressure cookers, pressure cookers, autoclaves and the like.
It is preferable that the closed container 6 is provided with the suction / exhaust hole 7 because the operation of pressurizing and depressurizing is simple and the pressure can be controlled. Although not shown, a sample inlet / outlet may be provided. The hydrostatic pressure in the present invention refers to a state in which a constant pressure acts vertically on the outer surface of the object (exemplified by an arrow P in FIG. 2). Here, when the surface area of the connection structure is considered with reference to FIG.
On the other hand, the thickness t of the connection portion is 0.1 mm or less, most often 30 μm or less, and since S is overwhelmingly larger than t, the pressure applied to the chip area S in the thickness direction of the connection portion is large, Pressure in the electrode connection direction can be easily obtained.
【０００７】以上で図１や３のような、複数以上の各種
形状やサイズのチップ類２（ａ〜ｃ）の電極４を接着剤
３を用いて、比較的小形の基板１の電極５に高密度に実
装するマルチチップモジュ−ル（ＭＣＭ）が得られる。
本発明の基板１１としては、ポリイミドやポリエステル
等のプラスチックフィルム、ガラス繊維／エポキシ等の
複合体、シリコン等の半導体、ガラスやセラミックス等
の無機質等を例示できる。As described above, as shown in FIGS. 1 and 3, the electrodes 4 of the chips 2 (ac) having a plurality of various shapes and sizes are attached to the electrodes 5 of the relatively small substrate 1 using the adhesive 3. A multi-chip module (MCM) to be mounted at high density can be obtained.
Examples of the substrate 11 of the present invention include plastic films such as polyimide and polyester, composites such as glass fiber / epoxy, semiconductors such as silicon, and inorganic materials such as glass and ceramics.
【０００８】本発明に用いる接着剤３は、熱可塑性材料
や、熱や光により硬化性を示す材料が広く適用できる。
これらは接続後の耐熱性や耐湿性に優れることから、硬
化性材料の適用が好ましい。なかでも潜在性硬化剤を含
有したエポキシ系接着剤は、短時間硬化が可能で接続作
業性が良く、分子構造上接着性に優れるので特に好まし
い。潜在性硬化剤は、熱およびまたは圧力による反応開
始の活性点が比較的明瞭であり、熱や圧力工程を伴う本
発明に好適である。潜在性硬化剤としては、イミダゾ−
ル系、ヒドラジド系、三フッ化ホウ素−アミン錯体、ア
ミンイミド、ポリアミンの塩、オニウム塩、ジシアンジ
アミドなど、及びこれらの変性物があり，これらは単独
または２種以上の混合体として使用出来る。これらはア
ニオン又はカチオン重合型などのいわゆるイオン重合性
の触媒型硬化剤であり、速硬化性を得やすくまた化学当
量的な考慮が少なくてよいことから好ましい。これの中
では、イミダゾ−ル系のものが非金属系であり電食しに
くくまた反応性や接続信頼性の点からとくに好ましい。
硬化剤としてはその他に、ポリアミン類、ポリメルカプ
タン、ポリフェノール、酸無水物等の適用や前記触媒型
硬化剤との併用も可能である。また硬化剤を核としその
表面を高分子物質や、無機物で被覆したマイクロカプセ
ル型硬化剤は、長期保存性と速硬化性という矛盾した特
性の両立がであることが好ましい。本発明の硬化剤の活
性温度は、４０〜２００℃が好ましい。４０℃未満であ
ると室温との温度差が少なく保存に低温が必要であり、
２００℃を越すと接続の他の部材に熱影響を与えるため
であり、このような理由から５０〜１５０℃がより好ま
しい。本発明の活性温度は、ＤＳＣ（示差走査熱量計）
を用いて、エポキシ樹脂と硬化剤の配合物を試料とし
て、室温から１０℃／分で昇温させた時の発熱ピ−ク温
度を示す。活性温度は低温側であると反応性に勝るが保
存性が低下する傾向にあるので、これらを考慮して決定
する。本発明において、硬化剤の活性温度以下の熱処理
により仮接続することで接着剤付き基板の保存性が向上
し、活性温度以上で信頼性に優れたマルチチップの接続
が得られる。As the adhesive 3 used in the present invention, a thermoplastic material or a material which is curable by heat or light can be widely used.
Since these are excellent in heat resistance and moisture resistance after connection, it is preferable to use a curable material. Among them, an epoxy adhesive containing a latent curing agent is particularly preferable because it can be cured in a short time, has good connection workability, and has excellent adhesiveness in terms of molecular structure. The latent curing agent has a relatively clear active point at which the reaction is initiated by heat and / or pressure, and is suitable for the present invention involving a heat or pressure step. As the latent curing agent, imidazo-
And hydrazide, boron trifluoride-amine complex, amine imide, polyamine salt, onium salt, dicyandiamide and the like, and modified products thereof, which can be used alone or as a mixture of two or more. These are so-called ion-polymerizable catalyst-type curing agents such as anionic or cationic polymerization types, and are preferred because they can easily obtain fast curability and require little consideration of chemical equivalents. Among them, imidazole-based ones are non-metallic ones, are less likely to cause electrolytic corrosion, and are particularly preferable in terms of reactivity and connection reliability.
In addition, as the curing agent, polyamines, polymercaptans, polyphenols, acid anhydrides, and the like can be used, or the curing agent can be used in combination with the catalyst-type curing agent. Further, it is preferable that the microcapsule-type curing agent whose core is a curing agent and whose surface is coated with a polymer substance or an inorganic substance has both contradictory characteristics such as long-term storage property and rapid curing property. The activation temperature of the curing agent of the present invention is preferably from 40 to 200C. When the temperature is lower than 40 ° C., the temperature difference from room temperature is small and a low temperature is required for storage,
If the temperature exceeds 200 ° C., it will have a thermal effect on other members of the connection. For such a reason, 50 to 150 ° C. is more preferable. The activation temperature of the present invention is determined by DSC (differential scanning calorimeter).
The exothermic peak temperature when the temperature of the mixture of the epoxy resin and the curing agent was raised from room temperature at a rate of 10 ° C./min. When the activation temperature is on the low temperature side, the reactivity tends to be superior to the reactivity but the storage stability tends to decrease. In the present invention, the provisional connection by heat treatment at a temperature lower than the activation temperature of the curing agent improves the preservability of the substrate with the adhesive, and a multichip connection excellent in reliability at the activation temperature or higher can be obtained.
【０００９】これら接着剤３には、導電粒子や絶縁粒子
を添加することが、接着剤付きチップの製造時の加熱加
圧時に厚み保持材として作用するので好ましい。この場
合、導電粒子や絶縁粒子の割合は、０．１〜３０体積％
程度であり、異方導電性とするには０．５〜１５体積％
である。接着剤層４は、絶縁層と導電層を分離形成した
複数層の構成品も適用可能である。この場合、分解能が
向上するため高ピッチな電極接続が可能となる。導電粒
子としては、Ａｕ、Ａｇ、Ｐｔ、Ｎｉ、Ｃｕ、Ｗ、Ｓ
ｂ、Ｓｎ、はんだ等の金属粒子やカーボン、黒鉛等があ
り、またこれら導電粒子を核材とするか、あるいは非導
電性のガラス、セラミックス、プラスチック等の高分子
等からなる核材に前記したような材質からなる導電層を
被覆形成したもので良い。さらに導電材料を絶縁層で被
覆してなる絶縁被覆粒子や、導電粒子とガラス、セラミ
ックス、プラスチック等の絶縁粒子の併用等も分解能が
向上するので適用可能である。これら導電粒子の中で
は、プラスチック等の高分子核材に導電層を形成したも
のや、はんだ等の熱溶融金属が、加熱加圧もしくは加圧
により変形性を有し、接続に回路との接触面積が増加
し、信頼性が向上するので好ましい。特に高分子類を核
とした場合、はんだのように融点を示さないので軟化の
状態を接続温度で広く制御でき、電極の厚みや平坦性の
ばらつきに対応し易いので特に好ましい。また、例えば
ＮｉやＷ等の硬質金属粒子や、表面に多数の突起を有す
る粒子の場合、導電粒子が電極や配線パターンに突き刺
さるので、酸化膜や汚染層の存在する場合にも低い接続
抵抗が得られ、信頼性が向上するので好ましい。以上の
説明では、フィルム状接着剤を用いた場合について述べ
たが、液状もしくはペ−スト状についても、同様に適用
可能である。またチップ高さの異なる場合について述べ
たが、チップ高さが同等の場合も適用可能である。It is preferable to add conductive particles or insulating particles to the adhesive 3 because it acts as a thickness retainer during heating and pressurization during the production of a chip with an adhesive. In this case, the ratio of the conductive particles and the insulating particles is 0.1 to 30% by volume.
About 0.5 to 15% by volume for anisotropic conductivity
It is. As the adhesive layer 4, a multi-layer component in which an insulating layer and a conductive layer are separately formed is also applicable. In this case, high resolution electrode connection is possible because the resolution is improved. Au, Ag, Pt, Ni, Cu, W, S
There are metal particles such as b, Sn, solder, etc., carbon, graphite, etc., and these conductive particles are used as a core material, or a non-conductive glass, ceramics, a core material made of a polymer such as plastic, etc. It may be formed by coating a conductive layer made of such a material. Further, insulating coated particles obtained by coating a conductive material with an insulating layer, and a combination of conductive particles and insulating particles of glass, ceramics, plastics, and the like are also applicable because resolution is improved. Among these conductive particles, those obtained by forming a conductive layer on a polymer nucleus material such as plastic, or a hot-melt metal such as solder have a deformability by heating or pressurizing, and make contact with the circuit for connection. This is preferable because the area is increased and the reliability is improved. In particular, when a polymer is used as a nucleus, a melting point is not exhibited unlike solder, so that a softened state can be widely controlled by a connection temperature, and it is easy to cope with variations in electrode thickness and flatness. In the case of hard metal particles such as Ni or W, or particles having a large number of protrusions on the surface, for example, conductive particles penetrate electrodes and wiring patterns, so that a low connection resistance can be obtained even when an oxide film or a contamination layer is present. It is preferable because it improves the reliability. In the above description, the case where the film adhesive is used has been described. However, the present invention can be similarly applied to a liquid or paste form. Further, the case where the chip heights are different has been described, but the case where the chip heights are the same is also applicable.
【００１０】本発明のマルチチップ実装法によれば、密
閉容器内の圧力は場所が変わっても一定であるので、多
数枚のＭＣＭを一度に処理できるので量産効果が高い。
また気体での加圧であるため高価な金型が不要であり、
気体の種類を変更することで熱、湿気、嫌気性などの各
種接着剤に適用可能である。密閉容器は、例えば加熱ガ
スの導入や容器を加熱炉中に保持することで加熱加圧操
作を一度に行うことが可能であり、比較的接着剤の硬化
に長時間のかかる場合も一度の操作で多数枚の基板につ
いて作製可能である。本発明のマルチチップ実装法によ
れば、密閉容器内で本格的に硬化を行う前に導通検査を
行うことができるので不良接続部を発見したとき、接着
剤は硬化反応の不十分な状態なので、チップの剥離や、
その後の溶剤を用いた清浄化も極めて簡単であり、リペ
ア作業（接続不良部を剥離し清浄化したのち再接続する
作業）が容易である。接着剤の硬化後であると、チップ
の剥離や、その後の溶剤による清浄化が極めて困難であ
るが、本実施例によれば、狭い基板状に多数のチップが
存在する場合も、リペア作業が容易である。本発明の好
ましい実施態様によれば、接着剤に用いる潜在性硬化剤
の活性温度以下の熱処理によりチップを基板に形成でき
るので仮接続後の接着剤の保存性が向上する。また、活
性温度以上で密閉容器内で加熱加圧するので、接着剤の
硬化時間を長くするなど自由に設定でき、接続後の容器
からの取り出しも冷却して接着剤の凝集力が十分に高い
状態で行えるので、マルチチップの信頼性に優れた接続
が得られる。According to the multi-chip mounting method of the present invention, since the pressure in the sealed container is constant even if the location is changed, a large number of MCMs can be processed at one time, and the mass production effect is high.
Also, because it is pressurized with gas, expensive molds are not required,
By changing the type of gas, it can be applied to various adhesives such as heat, moisture, and anaerobic. The closed container can perform the heating and pressurizing operation at once by, for example, introducing a heating gas or holding the container in a heating furnace. Can be manufactured for a large number of substrates. According to the multi-chip mounting method of the present invention, it is possible to conduct a continuity test before performing full-scale curing in a closed container, so when a defective connection is found, the adhesive is in a state of insufficient curing reaction. , Chip peeling,
Subsequent cleaning using a solvent is also extremely simple, and a repair operation (an operation of removing a defective connection portion, cleaning the same, and then reconnecting) is easy. After the adhesive has been cured, it is extremely difficult to peel off the chip and clean it with a solvent.However, according to the present embodiment, even when a large number of chips are present on a narrow substrate, the repair work is difficult. Easy. According to a preferred embodiment of the present invention, a chip can be formed on a substrate by a heat treatment at or below the activation temperature of the latent curing agent used for the adhesive, so that the preservability of the adhesive after the temporary connection is improved. In addition, since heating and pressurization is performed in a closed container at a temperature equal to or higher than the activation temperature, the curing time of the adhesive can be set freely, for example, and the adhesive can be taken out of the container after connection and the cohesive force of the adhesive is sufficiently high. Therefore, a multi-chip highly reliable connection can be obtained.
【００１１】[0011]
【実施例】以下実施例でさらに詳細に説明するが、本発
明はこれに限定されない。 実施例１ （１）接着剤の作製 フェノキシ樹脂（ＰＫＨＡ、ユニオンカーバイド社製高
分子量エポキシ樹脂）とマイクロカプセル型潜在性硬化
剤を含有する液状エポキシ樹脂（ノバキュアＨＰ−３９
４２ＨＰ、旭化成製、エポキシ当量１８５）の比率を３
０／７０とし、酢酸エチルの３０％溶液を得た。この溶
液に、粒径３±０．２μｍのポリスチレン系粒子にＮｉ
／Ａｕの厚さ０．２／０．０２μｍの金属被覆を形成し
た導電性粒子を２体積％添加し混合分散した。５ｍｍ×
１１ｍｍで厚み０．８ｍｍのガラスエポキシ基板（ＦＲ
−４グレ−ド）上に、高さ１８μｍの銅の回路を有し、
回路端部が後記するＩＣチップのバンプピッチに対応し
た接続電極を有するガラスエポキシ基板の接続領域に、
前記分散液をスクリ−ン印刷で塗布し、１００℃で２０
分乾燥し、電極上の厚みが２０μｍの接着剤層を得た。
この接着層のＤＳＣによる活性温度は１２０℃である。The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto. Example 1 (1) Preparation of Adhesive A liquid epoxy resin containing a phenoxy resin (PKHA, a high molecular weight epoxy resin manufactured by Union Carbide) and a microcapsule-type latent curing agent (Novacure HP-39)
42HP, Asahi Kasei, epoxy equivalent 185) ratio of 3
0/70 to give a 30% solution of ethyl acetate. In this solution, polystyrene particles having a particle size of 3 ± 0.2 μm
2% by volume of conductive particles on which a metal coating having a thickness of 0.2 / 0.02 μm / Au was added and mixed and dispersed. 5mm ×
11mm glass epoxy board 0.8mm thick (FR
-4 grade), and has a copper circuit with a height of 18 μm,
In the connection area of the glass epoxy substrate having the connection electrode corresponding to the bump pitch of the IC chip described later,
The dispersion is applied by screen printing, and is
After drying for a minute, an adhesive layer having a thickness of 20 μm on the electrode was obtained.
The activation temperature of this adhesive layer by DSC is 120 ° C.
【００１２】（２）電極の位置合わせと接続 前記の接着剤付き基板に、ＩＣチップ３個（高さ０．
３、０．５５、１．０ｍｍ）を配置し、ＣＣＤカメラに
よる電極の位置合わせを行った。接着剤は室温でも若干
の粘着性がある状態であり、室温で接着面に押しつける
ことで基板に簡単に保持でき、チップの仮付け基板を得
た。チップの仮付け基板を、プレッシャ−クッカ試験機
の圧力釜に入れて、１２０℃、２０ｋｇｆ／ｍｍ2 、１
０分間空気圧で処理後に室温に冷却して取出した。 （３）評価 各チップの電極と基板電極は良好に接続が可能であっ
た。接着剤はチップ近傍のみに存在しているので、基板
表面に不要接着剤はほとんどなかった。本実施例では、
高さの異なるＩＣチップ３個を基板面に接続できた。(2) Alignment and connection of electrodes Three IC chips (having a height of 0.3 mm) are provided on the substrate with the adhesive.
3, 0.55, 1.0 mm), and the electrodes were aligned with a CCD camera. The adhesive was in a slightly tacky state even at room temperature, and could be easily held on the substrate by pressing against the bonding surface at room temperature to obtain a temporary mounting substrate for the chip. The temporary substrate of the chip is placed in a pressure cooker of a pressure cooker testing machine, and is heated at 120 ° C., 20 kgf / mm 2, 1
After treatment with air pressure for 0 minutes, the mixture was cooled to room temperature and taken out. (3) Evaluation The electrodes of each chip and the substrate electrodes could be connected well. Since the adhesive was present only near the chip, there was almost no unnecessary adhesive on the substrate surface. In this embodiment,
Three IC chips having different heights could be connected to the substrate surface.
【００１３】実施例２ 実施例１と同様であるが、チップの仮付け基板を得た後
で電極間の電気的接続を検査する中間検査工程を設け
た。まず、７０℃、１０ｋｇｆ／ｍｍ2 で、スプリング
装置で加圧しながら各接続点の接続抵抗をマルチメータ
で測定検査したところ、１個のＩＣチップが異常であっ
た。そこで異常チップを剥離して新規チップで前記同様
の接続を行ったところ良好であった。本実施例では接着
剤の硬化反応が不十分な状態なので、チップの剥離や、
その後のアセトンを用いた清浄化も極めて簡単であり、
リペア作業が容易であった。また、チップの周囲の余剰
接着剤も同様にアセトンで簡単に除去可能であった。以
上の通電検査工程およびリペア工程の後で、実施例１と
同様圧力釜に入れて処理した。ところ、良好な接続特性
を示した。接着剤の硬化後であると、チップの剥離や、
その後の溶剤による清浄化が極めて困難であるが、本実
施例によれば、狭い基板状に多数のチップが存在する場
合も、リペア作業が極めて容易であった。Embodiment 2 As in Embodiment 1, except that a temporary mounting substrate for the chip is obtained, an intermediate inspection step for inspecting the electrical connection between the electrodes is provided. First, when the connection resistance at each connection point was measured and inspected with a multimeter at 70 ° C. and 10 kgf / mm 2 while applying pressure by a spring device, one IC chip was abnormal. Then, the abnormal chip was peeled off, and the same connection as described above was performed with a new chip. In this embodiment, the curing reaction of the adhesive is in an insufficient state, so that the chip is peeled off,
Subsequent cleaning with acetone is also very easy,
Repair work was easy. Excess adhesive around the chip could also be easily removed with acetone. After the above-described energization inspection step and the repair step, they were placed in a pressure cooker and processed as in Example 1. However, good connection characteristics were shown. After the adhesive has been cured, the chip may peel off,
Although subsequent cleaning with a solvent is extremely difficult, according to the present embodiment, the repair work was extremely easy even when a large number of chips exist on a narrow substrate.
【００１４】実施例３ 実施例１と同様であるが、図３例示のような両面基板と
した。各チップの電極と基板電極は良好に接続が可能で
あった。なお本実施例では圧力釜の処理の際、チップの
仮付け基板の下側になる面は、耐熱性の粘着テ−プでチ
ップを接着剤面に押しつけて補強し、基板からチップ剥
離のないようにした。Example 3 The same as Example 1, but a double-sided board as shown in FIG. 3 was used. The electrodes of each chip and the substrate electrodes could be connected well. In this embodiment, the lower surface of the temporary mounting substrate of the chip during the processing of the pressure cooker is reinforced by pressing the chip against the adhesive surface with a heat-resistant adhesive tape so that the chip does not peel off from the substrate. I did it.
【００１５】実施例４ 実施例１と同様であるが、接着剤の種類を変えた。すな
わち、導電粒子を未添加とした。この場合も各チップの
電極と基板電極は良好に接続が可能であった。バンプと
ガラスエポキシ基板の回路端部が直接接触し、接着剤で
固定されているためと見られる。Example 4 Same as Example 1, except that the type of adhesive was changed. That is, the conductive particles were not added. Also in this case, the electrodes of each chip and the substrate electrodes could be connected well. This is probably because the bump and the circuit end of the glass epoxy substrate are in direct contact and are fixed with an adhesive.
【００１６】[0016]
【発明の効果】以上詳述したように本発明によれば、基
板上の電極形成面とチップ電極間に接着剤を介在させ、
基板の電極とこれに相対峙するチップの電極間に接着剤
を介在させ、電極を位置合わせした状態で静水圧下で加
熱加圧するので、チップ高さの異なる場合や基板の両面
に実装する場合に有効なマルチチップ実装法を提供でき
る。As described in detail above, according to the present invention, an adhesive is interposed between an electrode forming surface on a substrate and a chip electrode,
An adhesive is interposed between the electrode of the substrate and the electrode of the chip facing it, and heating and pressing under hydrostatic pressure with the electrodes aligned, so when the chip height is different or when mounting on both sides of the substrate It is possible to provide an effective multi-chip mounting method.
【図１】 本発明の一実施例を説明する、基板上の電極
とチップ電極間に、接着剤を介在させ位置合わせした状
態を説明する断面模式図である。FIG. 1 is a schematic cross-sectional view illustrating a state in which an adhesive is interposed between an electrode on a substrate and a chip electrode to explain an embodiment of the present invention.
【図２】 本発明の一実施例を説明する、静水圧を耐え
ることが可能な密閉容器を説明する断面模式図である。FIG. 2 is a schematic cross-sectional view illustrating an airtight container capable of withstanding hydrostatic pressure, illustrating an embodiment of the present invention.
【図３】 従来の接続法を説明する断面模式図である。FIG. 3 is a schematic sectional view illustrating a conventional connection method.
１ 基板 ２ チップ ３ 接着剤 ４ 電極Ａ ５ 電極Ｂ ６ 密閉容器 ７ 吸排気孔 ８ 定盤 ９ 加圧型 DESCRIPTION OF SYMBOLS 1 Substrate 2 Chip 3 Adhesive 4 Electrode A 5 Electrode B 6 Airtight container 7 Intake / exhaust hole 8 Surface plate 9 Pressurization type
───────────────────────────────────────────────────── フロントページの続き (72)発明者 福嶋 直樹 茨城県下館市大字五所宮1150番地 日立化 成工業株式会社五所宮工場内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naoki Fukushima 1150 Goshomiya, Shimodate, Ibaraki Pref.
Claims (2)
あって、基板上の電極形成面とチップ電極間に接着剤を
介在させ、基板の電極とこれに相対峙するチップの電極
を位置合わせした状態で、静水圧下で加熱することを特
徴とするマルチチップ実装法1. A method of mounting a plurality of chips on a substrate, wherein an adhesive is interposed between an electrode forming surface on the substrate and the chip electrodes, and the electrodes of the substrate and the electrodes of the chips facing the electrodes are connected to each other. Multi-chip mounting method characterized by heating under hydrostatic pressure in the aligned state
あって、基板上の電極形成面とチップ電極間に接着剤を
介在させ、基板の電極とこれに相対峙するチップの電極
を位置合わせした状態で導通検査を行った後、静水圧下
で加熱することを特徴とするマルチチップ実装法2. A method of mounting a plurality of chips on a substrate, wherein an adhesive is interposed between an electrode forming surface on the substrate and the chip electrodes, and the electrodes of the substrate and the electrodes of the chips facing the electrodes are connected to each other. A multi-chip mounting method characterized by heating under hydrostatic pressure after conducting a continuity test in the aligned state
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20687696A JP4032317B2 (en) | 1996-08-06 | 1996-08-06 | Chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20687696A JP4032317B2 (en) | 1996-08-06 | 1996-08-06 | Chip mounting method |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003199806A Division JP2004031975A (en) | 2003-07-22 | 2003-07-22 | Connecting equipment |
| JP2006257284A Division JP4563362B2 (en) | 2006-09-22 | 2006-09-22 | Chip mounting method |
| JP2007101704A Division JP4780023B2 (en) | 2007-04-09 | 2007-04-09 | Multi-chip module mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1050930A true JPH1050930A (en) | 1998-02-20 |
| JP4032317B2 JP4032317B2 (en) | 2008-01-16 |
Family
ID=16530517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20687696A Expired - Fee Related JP4032317B2 (en) | 1996-08-06 | 1996-08-06 | Chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4032317B2 (en) |
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| EP1030349A2 (en) | 1999-01-07 | 2000-08-23 | Alphasem AG | Method and apparatus for treating components mounted on a substrate, in particular semiconductor chips |
| JP2002359264A (en) * | 2001-05-31 | 2002-12-13 | Sony Corp | Method and device for mounting flip-chip and semiconductor device |
| JP2003077953A (en) * | 2001-09-06 | 2003-03-14 | Sony Corp | Flip chip mounting method and apparatus, and semiconductor device |
| JP2008098608A (en) * | 2006-09-15 | 2008-04-24 | Lintec Corp | Method for producing semiconductor device |
| EP1936676A2 (en) * | 2006-12-22 | 2008-06-25 | TDK Corporation | Method of mounting electronic components, method of manufacturing an electronic component-embedded substrate, and electronic component-embedded substrate |
| EP1936675A2 (en) * | 2006-12-22 | 2008-06-25 | TDK Corporation | Collective mounting method of electronic components and manufacturing method of electronic component-embedded substrate |
| JP2009135309A (en) * | 2007-11-30 | 2009-06-18 | Lintec Corp | Method of manufacturing semiconductor device |
| JP2010007076A (en) * | 2009-08-07 | 2010-01-14 | Hitachi Chem Co Ltd | Anisotropically conductive adhesive film |
| WO2010044179A1 (en) * | 2008-10-16 | 2010-04-22 | 住友ベークライト株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| JP2011192747A (en) * | 2010-03-12 | 2011-09-29 | Nitto Shinko Kk | Method of manufacturing semiconductor module |
| KR101299773B1 (en) * | 2006-09-15 | 2013-08-23 | 린텍 가부시키가이샤 | Process for producing semiconductor device |
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| KR20210138263A (en) | 2020-05-12 | 2021-11-19 | 삼성전자주식회사 | A semiconductor chip mounting tape and a method of manufacturing semiconductor package using the tape |
-
1996
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