JP2008098608A - Method for producing semiconductor device - Google Patents

Method for producing semiconductor device Download PDF

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JP2008098608A
JP2008098608A JP2007205221A JP2007205221A JP2008098608A JP 2008098608 A JP2008098608 A JP 2008098608A JP 2007205221 A JP2007205221 A JP 2007205221A JP 2007205221 A JP2007205221 A JP 2007205221A JP 2008098608 A JP2008098608 A JP 2008098608A
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Prior art keywords
adhesive layer
chip
semiconductor device
wiring board
adhesive
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JP2007205221A
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Osamu Yamazaki
修 山崎
Isao Ichikawa
功 市川
Naoya Saeki
尚哉 佐伯
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Lintec Corp
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Lintec Corp
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor device capable of easily eliminating voids regardless of board design and preventing the adhesive from curling up during the void-eliminating operation. <P>SOLUTION: The method for producing the semiconductor device heats a wiring board having a chip and uncured adhesive layer superposed thereon to cure the uncured adhesive layer. The method includes a static pressing step in which before curing, the wiring board having a chip and uncured adhesive layer superposed thereon is statically pressed at a pressure higher by at least 0.05 MPa than ordinary pressure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置を製造する方法に関する。より詳しくは、本発明は、チップと未硬化の接着剤層とが積層された配線基板を加熱して、上記未硬化の接着剤層を硬化させて半導体装置を製造する方法に関する。   The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device by heating a wiring board on which a chip and an uncured adhesive layer are laminated, and curing the uncured adhesive layer.

従来、半導体装置は、液状またはフィルム状の熱硬化性の接着剤によってチップと配線基板とがダイボンドされ（ダイボンディング工程）、続いてワイヤーボンディング工程、モールディング工程を経て製造されている（図４、Ｖ〜VII）。チップ２と配線基板４と
を未硬化の接着剤層３を介して積層する際に、接着剤中にボイド５が存在したり、接着剤のチップ側または配線基板側の界面にボイド６が存在したりする場合がある（図４）。これらのボイドはダイボンディング工程後にも消滅せずに存在する（図４）。特に、液状の接着剤を用いた場合は接着剤中にボイドが見られることが多く、また、フィルム状の接着剤を用いた場合は、接着力不足や被着面の凹凸への追従性不足のため、上記界面にボイドが存在することが多い。 Conventionally, a semiconductor device is manufactured through die bonding of a chip and a wiring board with a liquid or film-like thermosetting adhesive (die bonding process), and subsequently through a wire bonding process and a molding process (FIG. 4, FIG. V to VII). When the chip 2 and the wiring substrate 4 are laminated via the uncured adhesive layer 3, the void 5 exists in the adhesive, or the void 6 exists at the interface of the adhesive on the chip side or the wiring substrate side. (FIG. 4). These voids exist without disappearing after the die bonding process (FIG. 4). In particular, when a liquid adhesive is used, voids are often found in the adhesive, and when a film-like adhesive is used, the adhesive force is insufficient and the adherence to the unevenness of the adherend surface is insufficient. Therefore, voids often exist at the interface.

しかしながら、このようなボイドは、半導体装置の信頼性評価においてパッケージクラックの起点となるため、ボイドをなくす必要があった。
これに対して、液状の接着剤であれば塗布時の低い粘度により、フィルム状の接着剤であればダイボンド時の弾性率の低減化により、あるいは、ダイボンド条件の最適化により、配線基板の凹凸に追従させることが試みられている（特許文献１）。
国際公開第２００５／００４２１６号パンフレット However, since such a void becomes a starting point of the package crack in the reliability evaluation of the semiconductor device, it is necessary to eliminate the void.
On the other hand, if it is a liquid adhesive, it has a low viscosity at the time of application, and if it is a film adhesive, it can be reduced by reducing the elastic modulus at the time of die bonding or by optimizing the die bonding conditions. (Patent Document 1).
International Publication No. 2005/004216 Pamphlet

液状またはフィルム状の接着剤を用いた場合、上記の方法によりボイドを減らせるが、低粘度あるいは低弾性率化すると、ダイボンド時にチップ端面へ接着剤がはみ出す不具合が発生する。特に近年の薄型化されたチップにおいては、そのはみ出した接着剤がチップ回路面に巻き上がり、ワイヤーパッドを汚染して、ワイヤー接合強度を低下させるという問題がある。   When a liquid or film-like adhesive is used, voids can be reduced by the above method. However, when the viscosity or the elastic modulus is lowered, there is a problem that the adhesive protrudes from the chip end face during die bonding. In particular, in a thin chip in recent years, there is a problem that the protruding adhesive rolls up on the chip circuit surface, contaminates the wire pad, and lowers the wire bonding strength.

また、特にフィルム状の接着剤を用いた場合、上記界面に存在するボイドの発生については、基板デザインにも依存する。このため、基板デザインが変更になるたびに配合変更による粘度コントロールや弾性率の低下、あるいはダイボンド条件の見直し、最適化を行わなければならず、その扱いも困難である。特に近年の高密度な配線基板においては、凹凸の段差が大きく、その段差を埋めるべくダイボンドを行うのはかなり困難である。   In particular, when a film adhesive is used, the generation of voids existing at the interface depends on the substrate design. For this reason, every time the substrate design is changed, viscosity control or a decrease in elastic modulus due to a change in composition, or a review and optimization of die bonding conditions must be performed, which is difficult to handle. Particularly, in recent high-density wiring boards, the uneven step is large, and it is very difficult to perform die bonding to fill the step.

したがって、本発明の目的は、基板デザインに依存せず、ボイドのない半導体装置が簡便に製造できる方法を提供することであり、さらに、この際に接着剤の巻き上がりも見られない半導体装置が製造できる方法を提供することにある。   Therefore, an object of the present invention is to provide a method by which a semiconductor device without voids can be easily manufactured without depending on the substrate design. Further, in this case, there is a semiconductor device in which no adhesive is rolled up. It is to provide a method that can be manufactured.

本発明者らは鋭意研究した結果、特定の静圧加圧工程により上記課題を解決できることを見出し、本発明を完成するに至った。
すなわち、本発明に係る半導体装置の製造方法は、
チップと未硬化の接着剤層とが積層された配線基板（チップが未硬化の接着剤層を介して積層された配線基板）を加熱して、上記未硬化の接着剤層を硬化させて半導体装置を製
造する方法であって、
上記硬化前（上記硬化が完了する前）に、上記チップと未硬化の接着剤層とが積層された配線基板を常圧に対して０．０５ＭＰａ以上の静圧により加圧する静圧加圧工程を含むことを特徴とする。 As a result of intensive studies, the present inventors have found that the above-mentioned problems can be solved by a specific hydrostatic pressure step, and have completed the present invention.
That is, a method for manufacturing a semiconductor device according to the present invention includes:
A wiring board in which a chip and an uncured adhesive layer are laminated (wiring board in which a chip is laminated through an uncured adhesive layer) is heated to cure the uncured adhesive layer and to form a semiconductor. A method of manufacturing a device comprising:
Static pressure pressurizing step of pressurizing the wiring board on which the chip and the uncured adhesive layer are laminated with a static pressure of 0.05 MPa or more with respect to normal pressure before the curing (before the curing is completed) It is characterized by including.

また、上記静圧加圧工程による加圧状態のまま、上記チップと未硬化の接着剤層とが積層された配線基板を加熱して上記未硬化の接着剤層を硬化する熱硬化工程をさらに含むことが好ましい。   Further, a thermosetting step of curing the uncured adhesive layer by heating the wiring board on which the chip and the uncured adhesive layer are laminated while being in a pressurized state by the static pressure pressing step. It is preferable to include.

本発明に係る半導体装置の製造方法によれば、チップと配線基板とを未硬化の接着剤層により積層する際は、通常通りの条件で行うことができ、その後の静圧加圧工程により基板デザインに依存せず簡便にボイドを消滅できる。また、この静圧加圧工程においては静圧により加圧するため、接着剤の巻き上がりも起こらない。   According to the method for manufacturing a semiconductor device according to the present invention, when the chip and the wiring substrate are laminated with the uncured adhesive layer, the substrate can be subjected to a normal pressure and pressurization step after that. Voids can be easily eliminated without depending on the design. Further, in this static pressure pressurizing step, pressure is applied by static pressure, so that the adhesive does not roll up.

以下、本発明について具体的に説明する。
本発明に係る半導体装置の製造方法では、チップ２と未硬化の接着剤層３とが積層（ダイボンド）された配線基板１（チップ２が未硬化の接着剤層３を介して積層された配線基板１。以下同様。）を加熱して、上記未硬化の接着剤層３を硬化させて半導体装置を製造する（図１）。なお、最終的にはこの接着剤層は充分に硬化されている。 Hereinafter, the present invention will be specifically described.
In the method for manufacturing a semiconductor device according to the present invention, a wiring substrate 1 in which a chip 2 and an uncured adhesive layer 3 are laminated (die-bonded) (a wiring in which the chip 2 is laminated via an uncured adhesive layer 3). The substrate 1 (the same applies hereinafter) is heated to cure the uncured adhesive layer 3 to manufacture a semiconductor device (FIG. 1). Finally, this adhesive layer is sufficiently cured.

チップ２としては、半導体ウェハを回路ごとに個別に切断して得られたチップを用いる。また、配線基板４としては、例えば金属からなるリードフレーム、有機材料または無機材料からなる基板、または金属および有機材料または無機材料からなる積層基板などが用いられる。また、本発明において、マルチスタック型半導体装置を製造する場合は、相対的に下側に位置するチップも配線基板とみなす。   As the chip 2, a chip obtained by individually cutting a semiconductor wafer for each circuit is used. As the wiring substrate 4, for example, a lead frame made of metal, a substrate made of organic material or inorganic material, or a laminated substrate made of metal and organic material or inorganic material is used. In the present invention, when a multi-stack semiconductor device is manufactured, a relatively lower chip is also regarded as a wiring board.

未硬化の接着剤層３は、フィルム状または液状の接着剤から形成される。好ましくはフィルム状の接着剤から形成される。本発明に用いられる接着剤は熱硬化性の接着剤であり、熱硬化性樹脂を含んでいればよい。熱硬化性樹脂は、たとえば、エポキシ、フェノキシ、フェノール、レゾルシノール、ユリア、メラミン、フラン、不飽和ポリエステル、シリコーンなどであり、適当な硬化剤及び必要に応じて添加される硬化促進剤と組み合わせて用いられる。このような熱硬化性樹脂は種々知られており、本発明においては特に制限されることなく公知の様々な熱硬化性樹脂が用いられる。また、熱硬化性の接着剤としては、常温で粘着性を有する粘接着剤であってもよい。粘接着剤とは、初期状態において常温で粘着性を示し、加熱のようなトリガーにより硬化し強固な接着性を示す接着剤をいう。常温で粘着性を有する粘接着剤としては、たとえば常温で感圧接着性を有するバインダー樹脂と、上記のような熱硬化性樹脂との混合物が挙げられる。常温で感圧接着性を有するバインダー樹脂としては、たとえばアクリル樹脂、ポリエステル樹脂、ポリビニルエーテル、ウレタン樹脂、ポリアミド等が挙げられる。   The uncured adhesive layer 3 is formed from a film-like or liquid adhesive. Preferably, it is formed from a film adhesive. The adhesive used in the present invention is a thermosetting adhesive as long as it contains a thermosetting resin. The thermosetting resin is, for example, epoxy, phenoxy, phenol, resorcinol, urea, melamine, furan, unsaturated polyester, silicone, etc., and is used in combination with an appropriate curing agent and a curing accelerator added as necessary. It is done. Various such thermosetting resins are known, and various known thermosetting resins are used in the present invention without particular limitation. Moreover, as a thermosetting adhesive agent, the adhesive agent which has adhesiveness at normal temperature may be sufficient. The adhesive is an adhesive that exhibits tackiness at normal temperature in an initial state and is cured by a trigger such as heating to exhibit strong adhesiveness. Examples of the adhesive having tackiness at normal temperature include a mixture of a binder resin having pressure-sensitive adhesive property at normal temperature and the thermosetting resin as described above. Examples of the binder resin having pressure-sensitive adhesive property at normal temperature include acrylic resin, polyester resin, polyvinyl ether, urethane resin, polyamide and the like.

本発明において、接着剤層３としてフィルム状の接着剤を使用する場合は、例えば、フィルム状の接着剤層が設けられたダイシング・ダイボンディングシートが用いられる。ダイシング・ダイボンディングシートは、基材フィルム上に前述した組成のフィルム状の接着剤層が剥離可能に積層した構成を有する。ダイシング・ダイボンディングシートの基材フィルムとフィルム状の接着剤層との剥離性を制御するため、フィルム状の接着剤層を形成する接着剤の組成中にウレタン系アクリレートオリゴマーなどのエネルギー線硬化性樹脂をさらに配合することが好ましい。エネルギー線硬化性樹脂を配合すると、エネルギー線照射前は基材とよく密着し、エネルギー線照射後は基材から剥離しやすくなるという効
果を付与できる。 In the present invention, when a film-like adhesive is used as the adhesive layer 3, for example, a dicing die-bonding sheet provided with a film-like adhesive layer is used. The dicing die bonding sheet has a configuration in which a film-like adhesive layer having the above-described composition is laminated on a base film in a peelable manner. In order to control the peelability between the base film of the dicing die-bonding sheet and the film-like adhesive layer, energy ray curable properties such as urethane acrylate oligomers are used in the composition of the adhesive that forms the film-like adhesive layer. It is preferable to further blend a resin. When energy beam curable resin is mix | blended, the effect that it will adhere | attach well with a base material before energy beam irradiation, and will become easy to peel from a base material after energy beam irradiation can be provided.

ダイシング・ダイボンディングシートに形成されるフィルム状の接着剤層の厚みは、接着する配線基板の凹凸の高さ形状等によって異なるが、通常３〜１００μｍ、好ましくは１０〜５０μｍである。   The thickness of the film-like adhesive layer formed on the dicing / die-bonding sheet is usually 3 to 100 μm, preferably 10 to 50 μm, although it varies depending on the uneven shape of the wiring board to be bonded.

また、本発明において接着剤層３として液状の接着剤を使用する場合は、例えば、前述したフィルム状の接着剤層の組成からバインダー樹脂を除いた熱硬化性樹脂とその硬化剤からなる配合の液状（ペースト状）接着剤が用いられる。   Further, when a liquid adhesive is used as the adhesive layer 3 in the present invention, for example, a composition comprising a thermosetting resin excluding the binder resin from the composition of the film-like adhesive layer described above and a curing agent thereof. A liquid (paste-like) adhesive is used.

次に、本発明の半導体装置の製造方法について、ダイシング・ダイボンディングシート（フィルム状の接着剤）を使用した場合の具体例について説明する。
本発明において、ダイシング・ダイボンディングシートを使用する場合、例えば、（１）ダイシング工程、（２）ダイボンド工程、（３）静圧加圧工程、（４）熱硬化工程、（５）組立工程の各工程を経て半導体装置が製造される。 Next, the manufacturing method of the semiconductor device of the present invention will be described with reference to a specific example in the case of using a dicing die bonding sheet (film adhesive).
In the present invention, when using a dicing die bonding sheet, for example, (1) dicing step, (2) die bonding step, (3) static pressure pressing step, (4) thermosetting step, and (5) assembly step. A semiconductor device is manufactured through each process.

（１）ダイシング工程は、シリコン等からなるウェハにダイシング・ダイボンディングシートを貼着して、ウェハと未硬化の接着剤層をともにダイシングする工程である。この工程により、片面に未硬化の接着剤層を有するチップが得られる。ダイシング・ダイボンディングシートがエネルギー線硬化性を有する場合は、ダイシング工程前あるいはダイシング工程後にエネルギー線を照射し、基材フィルムとの密着性を低下させておく。ダイシング・ダイボンディングシートを貼着する条件によっては、チップと未硬化の接着剤層との界面にボイドが形成される場合がある。   (1) The dicing process is a process in which a dicing die bonding sheet is attached to a wafer made of silicon or the like, and the wafer and the uncured adhesive layer are diced together. By this step, a chip having an uncured adhesive layer on one side is obtained. When the dicing die bonding sheet has energy ray curability, the energy ray is irradiated before the dicing step or after the dicing step to reduce the adhesion with the base film. Depending on the conditions for adhering the dicing die bonding sheet, a void may be formed at the interface between the chip and the uncured adhesive layer.

（２）ダイボンド工程は、ダイシング・ダイボンディングシートの基材フィルムと未硬化の接着剤層３の界面で剥離（ピックアップ）を行い、分離された未硬化の接着剤層を有するチップを配線基板のチップ搭載部に積層（ダイボンド）する工程である。この工程により、チップ２と未硬化の接着剤層３とが積層された配線基板１が得られる。ダイボンドの条件（圧力、温度、時間等）によっては、未硬化の接着剤層３と配線基板４との界面にボイド６が形成される場合がある(図１)。   (2) In the die bonding step, peeling (pickup) is performed at the interface between the base film of the dicing die bonding sheet and the uncured adhesive layer 3, and the chip having the separated uncured adhesive layer is removed from the wiring board. This is a step of stacking (die bonding) on the chip mounting portion. By this step, the wiring substrate 1 in which the chip 2 and the uncured adhesive layer 3 are laminated is obtained. Depending on the die bonding conditions (pressure, temperature, time, etc.), a void 6 may be formed at the interface between the uncured adhesive layer 3 and the wiring board 4 (FIG. 1).

（３）静圧加圧工程は、未硬化の接着剤層が充分に硬化される前に、ダイボンドされた配線基板の全方位から均等に加圧（静圧加圧）を行う工程である（図１、Ｉ）。本発明における加圧条件は、常圧に対し０．０５ＭＰａ以上であり、好ましくは常圧に対し０．１〜１．０ＭＰａである。すなわち、常圧に比較して０．０５ＭＰａ以上大きな圧力、好ましくは０．１〜１．０ＭＰａ大きな圧力を印加する。   (3) The static pressure pressing step is a step of applying pressure (static pressure pressing) uniformly from all directions of the die-bonded wiring board before the uncured adhesive layer is sufficiently cured ( FIG. 1, I). The pressurizing condition in the present invention is 0.05 MPa or more with respect to normal pressure, and preferably 0.1 to 1.0 MPa with respect to normal pressure. That is, a pressure larger than the normal pressure by 0.05 MPa or more, preferably a pressure larger by 0.1 to 1.0 MPa is applied.

静圧加圧工程には、具体的には、以下のような態様が挙げられる。まず、未硬化状態の接着剤層３がダイボンドされた配線基板１を上記静圧により加圧する（図１、Ｉ）。この静圧による加圧により、接着剤層３とチップ２との間に発生したボイド（図示せず）または接着剤層３と配線基板４との間に発生したボイド６が消滅する。配線基板４が微細で高低差が大きな回路デザインであったとしても、この静圧加圧工程を行えば、接着剤層３と配線基板４との界面に生じたボイド６も消滅させられる。このように、チップ２と配線基板４とを未硬化の接着剤層３により積層する際の条件を特別に制御することなく、簡便にボイド６を消滅できる。また、この静圧加圧工程においては静圧による加圧であるため、接着剤層のみが加圧されず、接着剤の巻き上がりも起こらない。   Specific examples of the hydrostatic pressure step include the following modes. First, the wiring board 1 to which the uncured adhesive layer 3 is die-bonded is pressed by the static pressure (FIG. 1, I). By this pressurization by static pressure, voids (not shown) generated between the adhesive layer 3 and the chip 2 or voids 6 generated between the adhesive layer 3 and the wiring substrate 4 disappear. Even if the wiring board 4 is fine and the circuit design has a large difference in height, the void 6 generated at the interface between the adhesive layer 3 and the wiring board 4 can be eliminated by performing this static pressure application step. Thus, the void 6 can be easily eliminated without specially controlling the conditions when the chip 2 and the wiring board 4 are laminated with the uncured adhesive layer 3. In addition, since the static pressure is applied by static pressure, only the adhesive layer is not pressurized, and the adhesive is not rolled up.

印加する圧力が上記範囲にあると、効率的にボイドの消滅が促されるとともに、汎用の加圧装置、耐圧防爆設備が使用でき、生産ラインをコンパクトにできる。また、設定圧力までの時間をほとんど要しない点で好ましい。   When the applied pressure is in the above range, void disappearance is promoted efficiently, and a general-purpose pressurizing device and pressure-proof explosion-proof equipment can be used, and the production line can be made compact. Moreover, it is preferable at the point which requires little time to setting pressure.

また、圧力を印加する時間は、好ましくは１〜１２０分、より好ましくは５〜９０分である。
静圧加圧装置としては、ダイボンドされた配線基板１に静圧が印加できれば特に制限されないが、好ましくは、オートクレーブ（コンプレッサー付き耐圧容器）などにより行われる。ところで、オートクレーブなど一定容積内で圧力が加えられると雰囲気温度の上昇が起こる。半導体装置の安定生産を行うためには温度を一定に保つことが好ましいため、未硬化の接着剤層３が硬化しない程度の温度に制御してもよい。また、温度を上げることにより、接着剤層が流動化して発生したボイドが動きやすくなり、消滅しやすくなることも期待できる。このような温度としては、接着剤層３を形成する接着剤の組成によって適宜設定されるが、例えば、３０〜１２０℃程度である。 Moreover, the time for applying pressure is preferably 1 to 120 minutes, more preferably 5 to 90 minutes.
Although it will not restrict | limit especially if a static pressure can be applied to the wiring board 1 die-bonded as a static pressure apparatus, Preferably, it is performed by an autoclave (pressure vessel with a compressor) etc. By the way, when pressure is applied within a certain volume such as an autoclave, the ambient temperature rises. Since it is preferable to keep the temperature constant for stable production of the semiconductor device, the temperature may be controlled so that the uncured adhesive layer 3 is not cured. It can also be expected that by increasing the temperature, voids generated by the fluidization of the adhesive layer are likely to move and disappear easily. Such temperature is appropriately set depending on the composition of the adhesive forming the adhesive layer 3, and is, for example, about 30 to 120 ° C.

（４）熱硬化工程は、ダイボンドされた配線基板１の接着剤層３を加熱して未硬化状態から充分な硬化状態にする工程である（図１、II）。なお、本明細書において、未硬化状態とは、接着剤の硬化反応が進行していない状態にあることをいう。充分な硬化状態、すなわち、硬化が完了した状態とは、反応が進行し、接着剤が変形できない状態にあることをいう。（３）静圧加圧工程でボイドが消滅したダイボンドされた配線基板１を加圧装置から開放し、大気圧下で使用する加熱装置に投入する。これにより、未硬化の接着剤層３を硬化させて硬化した接着剤層８とし、半導体装置のダイボンド用接着剤として必要な接着性能が与えられる。この状態におけるダイボンドされた配線基板は、（３）静圧加圧工程の状態を維持しており、接着剤層８の両側の界面にはボイドが存在せず、チップ２と配線基板４とが強固に接着されている。   (4) The thermosetting step is a step of heating the adhesive layer 3 of the die-bonded wiring board 1 to make it sufficiently hardened from an uncured state (FIG. 1, II). In the present specification, the uncured state means that the curing reaction of the adhesive is not progressing. A sufficiently cured state, that is, a state where curing is completed means that the reaction proceeds and the adhesive cannot be deformed. (3) The die-bonded wiring board 1 from which voids disappeared in the hydrostatic pressing process is released from the pressurizing apparatus and put into a heating apparatus used under atmospheric pressure. As a result, the uncured adhesive layer 3 is cured to form a cured adhesive layer 8, and the adhesion performance necessary as an adhesive for die bonding of a semiconductor device is given. The die-bonded wiring board in this state maintains the state of the (3) static pressure application process, and there are no voids on the interfaces on both sides of the adhesive layer 8, and the chip 2 and the wiring board 4 are It is firmly bonded.

加熱温度及び加熱時間は、接着剤層が充分に硬化できれば特に制限されず、接着剤組成に依存する。加熱温度は、好ましくは、１００〜２００℃、より好ましくは１２０〜１６０℃であり、加熱時間は、好ましくは１５〜３００分、より好ましくは３０〜１８０分である。   The heating temperature and the heating time are not particularly limited as long as the adhesive layer can be sufficiently cured, and depend on the adhesive composition. The heating temperature is preferably 100 to 200 ° C., more preferably 120 to 160 ° C., and the heating time is preferably 15 to 300 minutes, more preferably 30 to 180 minutes.

熱硬化を行うための加熱装置としては、特に制限はなく、従来使用される熱硬化装置（オーブン）がそのまま使用できる。
（５）組立工程は、接着剤層の熱硬化が行われたダイボンドされた配線基板を半導体装置に組立加工する工程である。例えば、図１に示す工程のようにワイヤー９を結線するワイヤーボンディング工程、封止樹脂１１を用いたモールディング工程などが行われる（図１、III、IV）。このようにして半導体装置１０が製造される。本発明の製造方法によっ
て得られた半導体装置１０は、接着剤層の界面にボイドが存在しないため、信頼性評価においてパッケージクラックが生じない。 There is no restriction | limiting in particular as a heating apparatus for performing thermosetting, The thermosetting apparatus (oven) used conventionally can be used as it is.
(5) The assembly process is a process for assembling a die-bonded wiring board on which the adhesive layer has been thermally cured into a semiconductor device. For example, a wire bonding process for connecting the wires 9 as in the process shown in FIG. 1, a molding process using the sealing resin 11 and the like are performed (FIGS. 1, III, and IV). In this way, the semiconductor device 10 is manufactured. Since the semiconductor device 10 obtained by the manufacturing method of the present invention does not have voids at the interface of the adhesive layer, no package crack occurs in the reliability evaluation.

以上、（３）静圧加圧工程の後に常圧に戻してから（４）熱硬化工程を行う半導体装置を製造する方法について説明したが、本発明に係る半導体装置の製造方法は、（３）静圧加圧工程において、静圧加圧状態のまま、上記未硬化の接着剤層３を加熱して硬化する熱硬化工程を行う製造方法でもよい。   The method for manufacturing a semiconductor device in which (3) the pressure is returned to normal pressure after the static pressure pressing step and (4) the thermosetting step is described above. However, the method for manufacturing a semiconductor device according to the present invention is (3 ) In the static pressure pressurizing step, a manufacturing method for performing a thermosetting step of heating and curing the uncured adhesive layer 3 in the static pressure pressurizing state may be used.

具体的には、静圧加圧工程を行ってボイドを消滅させるとともに、加圧下におきながら熱硬化工程を行って接着剤層３を充分に硬化させた後に、静圧加圧工程と熱硬化工程とを同時に終了する態様であってもよい。この場合は、熱硬化が行われるような高温で発生すると考えられる接着剤層中のボイドを、発生すると同時に静圧加圧により消滅させられると考えられるので好ましい。最終的に、半導体装置は接着剤層中にも界面にもボイドが存在せず、充分に接着剤が硬化した状態となり、チップと配線基板とが強固に接着される。   Specifically, the static pressure pressurizing step is performed to eliminate the voids, and the adhesive layer 3 is sufficiently cured by performing the thermosetting step while being pressed, and then the static pressure pressurizing step and the thermosetting. The aspect which complete | finishes a process simultaneously may be sufficient. In this case, it is preferable that voids in the adhesive layer considered to be generated at a high temperature at which thermosetting is performed are considered to be eliminated at the same time as static pressure is applied. Eventually, the semiconductor device has no void in the adhesive layer or at the interface, and the adhesive is sufficiently cured, so that the chip and the wiring board are firmly bonded.

本態様における加圧条件は、常圧に対し０．０５ＭＰａ以上、好ましくは０．１〜１．
０ＭＰａであり、加熱温度は、接着剤層が充分に硬化できれば特に制限されないが、好ましくは、１００〜２００℃、より好ましくは１２０〜１６０℃である。 The pressurizing condition in this embodiment is 0.05 MPa or more, preferably 0.1 to 1.
Although it is 0 MPa and the heating temperature is not particularly limited as long as the adhesive layer can be sufficiently cured, it is preferably 100 to 200 ° C, more preferably 120 to 160 ° C.

また、加圧および加熱時間は、ボイドが消滅でき、接着剤層が充分に硬化できれば特に制限されないが、好ましくは１５〜３００分、より好ましくは３０〜１８０分である。
また、熱硬化工程を２段階に分けて、第１段階を接着剤層を硬化させない加熱条件とし、第２段階を接着剤層を硬化させる加熱条件とする態様であっても良い。この場合、第１段階の加熱条件は、例えば、加熱温度が３０〜１２０℃程度であり、加熱時間は、好ましくは１〜１２０分、より好ましくは５〜９０分である。また、第２段階の加熱条件は、例えば、加熱温度が１２０〜２００℃であり、加熱時間は、好ましくは１５〜３００分、より好ましくは３０〜１８０分である。 The pressurization and heating time are not particularly limited as long as voids can be eliminated and the adhesive layer can be sufficiently cured, but it is preferably 15 to 300 minutes, more preferably 30 to 180 minutes.
Alternatively, the thermosetting process may be divided into two stages, and the first stage may be a heating condition that does not cure the adhesive layer, and the second stage may be a heating condition that cures the adhesive layer. In this case, the heating condition of the first stage is, for example, a heating temperature of about 30 to 120 ° C., and a heating time is preferably 1 to 120 minutes, more preferably 5 to 90 minutes. Moreover, as for the heating conditions of a 2nd step, heating temperature is 120-200 degreeC, for example, Heating time becomes like this. Preferably it is 15-300 minutes, More preferably, it is 30-180 minutes.

また、本発明の半導体装置の製造方法においては、接着剤層３として液状（ペースト状）の接着剤が使用されても良い。液状の接着剤を使用する場合は、前述の（１）ダイシング工程において、ダイシング・ダイボンディングシートの代わりにダイボンド機能のない通常のダイシングシートが使用され、ウエハがチップ化される。（２）ダイボンド工程でチップをピックアップした後、液状接着剤を塗布した配線基板にダイボンドを行う。（３）静圧加圧工程、（４）熱硬化工程及び（５）組み立て工程は、前述の態様と同様の方法で行うことができる。ダイボンドされた配線基板の取扱いを行い易くするため、（３）静圧加圧工程の前で液状の接着剤を半硬化（Ｂステージ化）させる加熱工程を加えても良い。なお、液状の接着剤を用いた場合は、ダイボンド工程で接着剤層３中にボイド５が存在していても、静圧加圧工程によってボイド５が消滅できる（図４参照）。   In the method for manufacturing a semiconductor device of the present invention, a liquid (paste-like) adhesive may be used as the adhesive layer 3. When a liquid adhesive is used, a normal dicing sheet having no die bonding function is used instead of the dicing die bonding sheet in the above-mentioned (1) dicing step, and the wafer is chipped. (2) After picking up the chip in the die bonding step, die bonding is performed on the wiring substrate coated with the liquid adhesive. The (3) static pressure pressing step, (4) thermosetting step, and (5) assembly step can be performed by the same method as described above. In order to facilitate the handling of the die-bonded wiring board, (3) a heating step of semi-curing (B-stage) the liquid adhesive may be added before the static pressure step. In addition, when a liquid adhesive is used, even if the void 5 exists in the adhesive layer 3 in the die bonding process, the void 5 can be eliminated by the hydrostatic pressing process (see FIG. 4).

本発明の製造方法によって得られる半導体装置の構成は前述の態様のものに限定されず、種々の構成の半導体装置の製造に適用できる。
例えば、本発明の半導体装置の製造方法は、マルチスタック型の半導体装置の製造に適用してもよい。すなわち、相対的に上部を構成するチップ２２と、ワイヤーが結線されていてもよい相対的に下部を構成するチップ２５（配線基板）とを未硬化の接着剤層２３を介して積層するチップどうしのダイボンド工程に用いても良い（図２）。このような半導体装置は、図２のように上部と下部のサイズが同じセイムサイズスタック型半導体装置であっても良いし、サイズの異なる階段状のマルチスタック型半導体装置であっても良い。さらに、接着剤層２３が、結線されたワイヤーを埋め込む形で積層されたセイムサイズスタック型半導体装置であっても良く、この場合、本発明によれば、ワイヤーの周辺に発生するボイドを消滅できるのでより好ましい。 The configuration of the semiconductor device obtained by the manufacturing method of the present invention is not limited to the above-described embodiment, and can be applied to the manufacture of semiconductor devices having various configurations.
For example, the semiconductor device manufacturing method of the present invention may be applied to the manufacture of a multi-stack type semiconductor device. That is, chips that relatively stack the chip 22 that constitutes the upper part and the chip 25 (wiring substrate) that constitutes the lower part that may be connected to the wire via the uncured adhesive layer 23. You may use for the die-bonding process of (FIG. 2). Such a semiconductor device may be a same size stack type semiconductor device having the same upper and lower sizes as shown in FIG. 2, or may be a stepped multi-stack type semiconductor device having different sizes. Further, the same size stack type semiconductor device may be used in which the adhesive layer 23 is laminated so as to embed the connected wires. In this case, according to the present invention, voids generated around the wires can be eliminated. It is more preferable.

このようなマルチスタック型半導体装置の製造方法は、前述の態様において下部のチップ２５を配線基板１の代わりとすることにより達成できる。
また、本発明の半導体装置の製造方法は、図３に示すように、フリップチップ型の半導体装置に用いてもよい。この場合、フリップチップボンドに用いられるアンダーフィル材が未硬化の接着剤層に相当する。アンダーフィル材としては、液状（ペースト状）のアンダーフィル材を用いても良く、シート状アンダーフィル材を用いても良い。熱硬化性のシート状アンダーフィル材としては、例えば、本願出願人らによる特願２００５−１２９５０２に記載されたものが使用できる。 Such a manufacturing method of the multi-stack type semiconductor device can be achieved by replacing the lower chip 25 with the wiring board 1 in the above-described embodiment.
Further, the semiconductor device manufacturing method of the present invention may be used for a flip-chip type semiconductor device as shown in FIG. In this case, the underfill material used for flip chip bonding corresponds to the uncured adhesive layer. As the underfill material, a liquid (paste-like) underfill material or a sheet-like underfill material may be used. As the thermosetting sheet-like underfill material, for example, those described in Japanese Patent Application No. 2005-129502 by the applicants of the present application can be used.

シート状アンダーフィル材を使用した場合における製造方法は、次の通りである。まず、回路面にバンプが形成された半導体ウェハを準備する。半導体ウェハの回路面に、上記シートのアンダーフィル層（接着剤層３３）がバンプを貫通するように貼付する。次いで、半導体ウェハの裏面に通常のダイシングテープを貼着し、これを介してリングフレームに固定して、ダイシング装置を用いて半導体ウェハを切断分離し、チップを得る。次いで、上記シートの基材のみを剥離し、バンプ頂部を露出させる。これにより、回路面が未硬
化の接着剤層３３で覆われ、かつバンプ３５頂部が接着剤層３３から突出したチップが得られる。次いで、このバンプ３５が、配線基板３４の電極部に相対するように位置合わせをし、チップ３２と配線基板３４との導通を確保するように、チップ３２を配線基板３４に載置する。このようにしてチップと未硬化の接着剤層３３（アンダーフィル材）とが積層（フリップチップボンド）された配線基板３１が得られる。 The manufacturing method in the case of using a sheet-like underfill material is as follows. First, a semiconductor wafer having a bump formed on a circuit surface is prepared. The underfill layer (adhesive layer 33) of the sheet is stuck on the circuit surface of the semiconductor wafer so as to penetrate the bumps. Next, a normal dicing tape is attached to the back surface of the semiconductor wafer, fixed to the ring frame through this, and the semiconductor wafer is cut and separated using a dicing apparatus to obtain a chip. Subsequently, only the base material of the said sheet | seat is peeled and a bump top part is exposed. As a result, a chip in which the circuit surface is covered with the uncured adhesive layer 33 and the tops of the bumps 35 protrude from the adhesive layer 33 is obtained. Next, the bumps 35 are aligned so as to face the electrode portions of the wiring board 34, and the chip 32 is placed on the wiring board 34 so as to ensure conduction between the chip 32 and the wiring board 34. In this way, the wiring substrate 31 in which the chip and the uncured adhesive layer 33 (underfill material) are laminated (flip chip bond) is obtained.

本態様においては、このようにして得られたフリップチップボンドされた配線基板を、前述した態様と同様の（３）静圧加圧工程、（４）熱硬化工程及び（５）組立工程が行われて半導体装置が製造される。本態様においては（５）組み立て工程におけるワイヤーボンディング工程は不要であるため、未硬化の接着剤層３３（アンダーフィル材）を硬化させた後にモールディング工程を経て、半導体装置が製造される。   In this aspect, the flip-chip bonded wiring board thus obtained is subjected to the same (3) static pressure pressing process, (4) thermosetting process and (5) assembling process as those described above. In this way, a semiconductor device is manufactured. In this aspect, since the wire bonding step in the assembly step (5) is unnecessary, the semiconductor device is manufactured through the molding step after curing the uncured adhesive layer 33 (underfill material).

［実施例］
以下、実施例に基づいて本発明をさらに具体的に説明するが、本発明はこれらの実施例に限定されるものではない。 [Example]
EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not limited to these Examples.

［実施例１］
（１）ダイシング工程
ダミーのシリコンウェハ(200mm径、厚さ150μm)に、ダイシング・ダイボンディングシ
ート（リンテック社製、Adwill LE-5003）をテープマウンター（リンテック社製、Adwill
RAD2500 m/8）を用いて貼付し、同時にリングフレームに固定した。その後、UV照射装置（リンテック社製Adwill RAD2000 m/8）を用いて基材面から紫外線を照射した。次に、ダイシング装置（ディスコ社製、DFD651）を使用し8mm×8mmのサイズのチップにダイシングした。ダイシングの際の切り込み量は、ダイシング・ダイボンディングシートの基材フィルムに対して20μｍ切り込むようにした。
（２）ダイボンド工程
チップをダイボンドする配線基板として、銅箔張り積層板（三菱ガス化学社製、CCL-HL830）の銅箔に回路パターンが形成され、パターン上にソルダーレジスト（太陽インキ社
製、PSR-4000 AUS5）を有している基板 (ちの技研社製) を用いた。（１）で得られたシ
リコンチップを粘接着剤層（未硬化の接着剤層）ごとピックアップし、該配線基板上に粘接着剤層を介して載置した後、100℃、300gf、1秒間の条件で圧着（ダイボンド）した。
（３）静圧加圧工程
続いて、（２）で得られたチップがダイボンドされた配線基板を加熱加圧装置（栗原製作所製オートクレーブ）に投入し、常圧よりも0.5ＭＰａ大きい静圧下で、100℃、30分加熱し、粘接着剤層に出現するボイドの除去を行った。
（４）熱硬化工程
加熱加圧装置よりダイボンドされた配線基板を取り出した後、常圧のオーブンにて120
℃、1時間、続いて140℃、1時間の条件で加熱し、粘接着剤層を硬化させた。
（５）組立工程
封止装置(アピックヤマダ株式会社製MPC-06M Trial Press)により、（３）で得られた
ダイボンドされた配線基板をモールド樹脂(京セラケミカル株式会社製KE-1100AS3)で封止厚400μmになるように封止した。次いで、175℃、5時間で封止樹脂を硬化させた。さらに、封止した配線基板をダイシングテープ(リンテック社製Adwill D-510T)に貼付し、ダイ
シング装置(ディスコ社製、DFD651)により12mm×12mmサイズにダイシングしてダミーチップによるワイヤーなしの模擬的な半導体装置を得た。 [Example 1]
(1) Dicing process A dummy silicon wafer (200mm diameter, 150μm in thickness) with a dicing die bonding sheet (Lintech, Adwill LE-5003) tape mounter (Lintech, Adwill)
RAD2500 m / 8) was applied and fixed to the ring frame at the same time. Thereafter, the substrate surface was irradiated with ultraviolet rays using a UV irradiation device (Adwill RAD2000 m / 8 manufactured by Lintec). Next, the wafer was diced into 8 mm × 8 mm chips using a dicing machine (DFD651, manufactured by DISCO Corporation). The amount of cut at the time of dicing was set to cut 20 μm with respect to the base film of the dicing die bonding sheet.
(2) Die-bonding process As a wiring board for die-bonding the chip, a circuit pattern is formed on the copper foil of a copper foil-clad laminate (manufactured by Mitsubishi Gas Chemical Company, CCL-HL830), and a solder resist (manufactured by Taiyo Ink, A substrate (manufactured by Chino Giken) with PSR-4000 AUS5) was used. The silicon chip obtained in (1) is picked up together with the adhesive layer (uncured adhesive layer) and placed on the wiring substrate via the adhesive layer, and then 100 ° C., 300 gf, Pressure bonding (die bonding) was performed for 1 second.
(3) Static pressure pressurizing step Subsequently, the wiring board on which the chip obtained in (2) is die-bonded is put into a heating and pressurizing device (autoclave manufactured by Kurihara Seisakusho), and under a static pressure 0.5 MPa larger than normal pressure. The mixture was heated at 100 ° C. for 30 minutes to remove voids appearing in the adhesive layer.
(4) Thermosetting process After the die-bonded wiring board is taken out from the heating and pressurizing device, it is 120 in an atmospheric pressure oven.
The adhesive layer was cured by heating at 140 ° C. for 1 hour, followed by heating at 140 ° C. for 1 hour.
(5) Assembly process With a sealing device (MPC-06M Trial Press manufactured by Apic Yamada Co., Ltd.), the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.). Sealed to 400 μm. Next, the sealing resin was cured at 175 ° C. for 5 hours. Furthermore, the sealed wiring board is affixed to a dicing tape (Adwill D-510T manufactured by Lintec Corporation), and is diced into a 12 mm x 12 mm size by a dicing device (DFD 651 manufactured by Disco Corporation), and a dummy chip without wires is simulated. A semiconductor device was obtained.

［実施例２］〜［実施例６］
実施例１において、（３）静圧加圧工程における処理条件を表１の条件に変更して行った以外は、実施例１と同様にして模擬的な半導体装置を得た。なお、表１において、圧力の値は、常圧よりもどれだけ大きいかで示す。 [Example 2] to [Example 6]
In Example 1, a simulated semiconductor device was obtained in the same manner as in Example 1 except that (3) the processing conditions in the static pressure application step were changed to the conditions shown in Table 1. In Table 1, the pressure value indicates how much larger than the normal pressure.

Figure 2008098608
Figure 2008098608

［実施例７］
（３）静圧加圧工程および（４）熱硬化工程を同時に開始し同時に終了した。すなわち、常圧よりも0.5ＭＰａ大きい静圧下で、120℃、1時間、続いて140℃、1時間行い、粘接
着剤層を充分に硬化させた。それ以外は実施例１と同様にして模擬的な半導体装置を得た。 [Example 7]
(3) The hydrostatic pressure step and (4) the thermosetting step were started and ended simultaneously. That is, under a static pressure 0.5 MPa higher than normal pressure, 120 ° C. for 1 hour, followed by 140 ° C. for 1 hour to sufficiently cure the adhesive layer. Otherwise, a simulated semiconductor device was obtained in the same manner as in Example 1.

［実施例８］
ダイシング・ダイボンディングシートをAdwill LE-5006（リンテック社製）に変更した以外は、実施例１と同様にして模擬的な半導体装置を得た。 [Example 8]
A simulated semiconductor device was obtained in the same manner as in Example 1 except that the dicing die bonding sheet was changed to Adwill LE-5006 (manufactured by Lintec Corporation).

［実施例９］
（１）ダイシング工程
ダミーのシリコンウェハ(200mm径、厚さ150μm)に、UV硬化型ダイシングテープ（Adwill D-628 リンテック社製）をテープマウンター（リンテック社製、Adwill RAD2500 m/8）を用いて貼付し、同時にリングフレームに固定した。次に、ダイシング装置（ディスコ社製、DFD651）を使用し8mm×8mmのサイズのチップにダイシングした。ダイシングの際の切り込み量は、基材に対して20μｍ切り込むようにした。その後、UV照射装置（リンテック社製Adwill RAD2000 m/8）を用いて基材面から紫外線を照射した。
（２）ダイボンド工程
チップをダイボンドする配線基板として、銅箔張り積層板（三菱ガス化学社製、CCL-HL830）の銅箔に回路パターンが形成され、パターン上にソルダーレジスト（太陽インキ社
製、PSR-4000 AUS5）を有している基板 (ちの技研社製) を用いた。以下の配合よりなる
ペースト状の接着剤を該配線基板上に塗布し、（１）で得られたシリコンチップをピックアップして、該配線基板上のペースト状の接着剤の上に載置した後、23℃、100gf、1秒間の条件で圧着（ダイボンド）した。
（ペースト状接着剤の配合）
液状ビスフェノールＡ型骨格エポキシ樹脂（ジャパンエポキシレジン（株）社製、エピコート828）：３０重量部、グリシジルアミン型エポキシ樹脂（ジャパンエポキシレジン
（株）社製、エピコート630）：１５重量部、ノボラック型エポキシ樹脂（日本化薬（株
）製、EOCN-102S）：５重量部、硬化剤（旭電化製、アデカハードナー3636AS）を有機溶
媒（メチルエチルケトン）に分散した溶液（固形濃度が１５％）：５重量部、硬化促進剤（四国化成工業製、キュアゾール2PHZ）を有機溶媒（メチルエチルケトン）に分散した溶液（固形濃度が１５％）：１０重量部
（３）静圧加圧工程および（４）熱硬化工程
続いて、（３）静圧加圧工程および（４）熱硬化工程を同時に開始し同時に終了した。
すなわち、チップがダイボンドされた配線基板を加熱加圧装置（栗原製作所製オートクレーブ）に投入し、0.5ＭＰａの静圧下で、120℃、1時間、続いて140℃、1時間行い、加圧
条件下で粘接着剤層を硬化させた。
（５）封止工程
封止装置(アピックヤマダ株式会社製MPC-06M Trial Press)により、（３）で得られた
ダイボンドされた配線基板をモールド樹脂(京セラケミカル株式会社製KE-1100AS3)で封止厚400μmになるように封止した。次いで、175℃、5時間で封止樹脂を硬化させた。次いで、封止した配線基板をダイシングテープ(リンテック社製Adwill D-510T)に貼付し、ダイ
シング装置(ディスコ社製、DFD651)により12mm×12mmサイズにダイシングして模擬的な半導体装置を得た。 [Example 9]
(1) Dicing process Using a UV mount dicing tape (Adwill D-628 Lintec) and tape mounter (Adwill RAD2500 m / 8) on a dummy silicon wafer (200mm diameter, 150μm thickness) Affixed to the ring frame at the same time. Next, the wafer was diced into 8 mm × 8 mm chips using a dicing machine (DFD651, manufactured by DISCO Corporation). The amount of cut at the time of dicing was set to cut by 20 μm with respect to the base material. Thereafter, the substrate surface was irradiated with ultraviolet rays using a UV irradiation device (Adwill RAD2000 m / 8 manufactured by Lintec).
(2) Die-bonding process As a wiring board for die-bonding the chip, a circuit pattern is formed on the copper foil of a copper foil-clad laminate (manufactured by Mitsubishi Gas Chemical Co., Ltd., CCL-HL830). A substrate (manufactured by Chino Giken) with PSR-4000 AUS5) was used. After applying a paste adhesive having the following composition on the wiring substrate, picking up the silicon chip obtained in (1) and placing it on the paste adhesive on the wiring substrate And pressure bonding (die bonding) under the conditions of 23 ° C., 100 gf, 1 second.
(Formation of paste adhesive)
Liquid bisphenol A type skeleton epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 828): 30 parts by weight, glycidylamine type epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 630): 15 parts by weight, novolak type Epoxy resin (Nippon Kayaku Co., Ltd., EOCN-102S): 5 parts by weight, hardener (Asahi Denka Co., Adeka Hardener 3636AS) dispersed in an organic solvent (methyl ethyl ketone) (solid concentration 15%): 5 Part by weight, a solution in which a curing accelerator (manufactured by Shikoku Kasei Kogyo Co., Ltd., Curesol 2PHZ) is dispersed in an organic solvent (methyl ethyl ketone) (solid concentration is 15%): 10 parts by weight (3) Static pressure and pressure step Process Subsequently, (3) the static pressure pressing process and (4) the thermosetting process were started at the same time and ended simultaneously.
In other words, the circuit board on which the chip is die-bonded is put into a heating and pressurizing device (autoclave manufactured by Kurihara Seisakusho), and subjected to a static pressure of 0.5 MPa at 120 ° C. for 1 hour, followed by 140 ° C. for 1 hour. The adhesive layer was cured with
(5) Sealing process Using a sealing device (MPC-06M Trial Press manufactured by Apic Yamada Co., Ltd.), the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.). Sealed to a thickness of 400 μm. Next, the sealing resin was cured at 175 ° C. for 5 hours. Next, the sealed wiring board was affixed to a dicing tape (Adwill D-510T manufactured by Lintec Corporation), and diced to 12 mm × 12 mm size with a dicing apparatus (DFD 651 manufactured by Disco Corporation) to obtain a simulated semiconductor device.

［比較例１］
静圧加圧工程〜熱硬化工程において、ダイボンドされた配線基板を加熱加圧装置に投入したが加圧を行わず、大気圧下で、120℃、1時間、続いて140℃、1時間加熱し、粘接着剤層を硬化した。それ以外は実施例１と同様にして模擬的な半導体装置を得た。すなわち、静圧加圧工程を行わなかった以外は実施例１と同様にして模擬的な半導体装置を得た。 [Comparative Example 1]
In the hydrostatic pressing process to the thermosetting process, the die-bonded wiring board was put into a heating and pressurizing device, but it was not pressurized and heated under atmospheric pressure at 120 ° C for 1 hour, followed by 140 ° C for 1 hour. And the adhesive layer was cured. Otherwise, a simulated semiconductor device was obtained in the same manner as in Example 1. That is, a simulated semiconductor device was obtained in the same manner as in Example 1 except that the static pressure application step was not performed.

［比較例２］
実施例９の（２）ダイボンド工程において、チップの圧着条件を23℃、500gf、1秒間とした以外は、実施例９と同様の評価を行った。なお、ダイボンド工程後の接着剤の巻き上がりが多すぎたため、その後の工程は行わなかった。 [Comparative Example 2]
Evaluation was performed in the same manner as in Example 9 except that, in (2) die bonding step of Example 9, the pressure bonding condition of the chip was 23 ° C., 500 gf, and 1 second. In addition, since there were too many rolls of the adhesive agent after a die-bonding process, the subsequent process was not performed.

［評価方法］
試験 １； ボイドの有無の確認
実施例、比較例の半導体装置の製造方法において、シリコンウエハの代わりに透明の円板ガラス（エヌ・エスジー・プレシジョン社製、直径8インチ、厚さ100μm）を用いて同
様の操作を行った。得られたガラスチップがダイボンドされた配線基板は、接着剤層がガラスチップ側から透視可能であり、デジタルマイクロスコープによりボイドの有無を観察した。結果を表２に示す。 [Evaluation methods]
Test 1; Confirmation of the presence or absence of voids In the semiconductor device manufacturing methods of the examples and comparative examples, a transparent disk glass (manufactured by NSG Precision, diameter 8 inches, thickness 100 μm) was used instead of the silicon wafer. The same operation was performed. The obtained wiring board on which the glass chip was die-bonded had an adhesive layer that could be seen through from the glass chip side, and the presence or absence of voids was observed with a digital microscope. The results are shown in Table 2.

試験 ２； 接着剤のチップ表面への巻き上がりの確認
実施例、比較例の半導体装置の製造方法において、（３）静圧加圧工程および（４）熱硬化工程を終えた段階でダイボンドされた配線基板の断面およびチップ表面をデジタルマイクロスコープにより観察して、チップ表面への接着剤の巻き上がりの有無を確認した。結果を表２に示す。 Test 2: Confirmation of roll-up of adhesive onto chip surface In the semiconductor device manufacturing methods of Examples and Comparative Examples, (3) static pressure pressing step and (4) thermosetting step were die-bonded. The cross section of the wiring board and the chip surface were observed with a digital microscope, and the presence or absence of the adhesive being rolled up on the chip surface was confirmed. The results are shown in Table 2.

試験 ３； 半導体パッケージの信頼性評価
実施例、比較例の半導体装置の製造方法において、（５）封止工程を終えた半導体装置（半導体パッケージ）を８５℃、６０％ＲＨ条件下に１６８時間放置して吸湿させた後、最高温度２６０℃加熱時間1分間のＩＲリフロー(リフロー炉：相模理工製ＷＬ-１５-２０ＤＮＸ型)を３回行った。この後、チップと配線基板との接合部の浮き・剥がれの有無、
パッケージクラック発生の有無を、走査型超音波探傷装置(日立建機ファインテック株式
会社製Ｈｙｅ-Ｆｏｃｕｓ)による断面観察で評価した。接合部に０．５ｍｍ以上の剥離を観察した場合を「剥離が発生した」と判断した。半導体パッケージ２５個について上記試験を行い、「剥離が発生しなかった」個数を数えた。この評価結果を表２に示す。 Test 3; Reliability evaluation of semiconductor package In the semiconductor device manufacturing methods of the examples and comparative examples, (5) the semiconductor device (semiconductor package) after the sealing process is left for 168 hours at 85 ° C. and 60% RH. After moisture absorption, IR reflow (reflow furnace: WL-15-20DNX type, manufactured by Sagami Riko Co., Ltd.) with a maximum temperature of 260 ° C. for 1 minute was performed three times. After this, the presence or absence of floating / peeling at the joint between the chip and the wiring board,
The presence or absence of package cracks was evaluated by cross-sectional observation using a scanning ultrasonic flaw detector (Hy-Focus manufactured by Hitachi Construction Machinery Finetech Co., Ltd.). The case where peeling of 0.5 mm or more was observed at the joint was judged as “peeling occurred”. The above test was performed on 25 semiconductor packages, and the number of “no peeling occurred” was counted. The evaluation results are shown in Table 2.

Figure 2008098608
Figure 2008098608

図１は、本発明の半導体装置の製造方法を説明するための図である。FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to the present invention. 図２は、本発明に用いられるチップと未硬化の接着剤層とが積層された配線基板の例を示す。FIG. 2 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated. 図３は、本発明に用いられるチップと未硬化の接着剤層とが積層された配線基板の例を示す。FIG. 3 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated. 図４は、従来の半導体装置の製造方法を説明するための図である。FIG. 4 is a diagram for explaining a conventional method of manufacturing a semiconductor device.

符号の説明Explanation of symbols

１： チップと未硬化の接着剤層とが積層された配線基板
２： チップ
３： 未硬化の接着剤層
４： 配線基板
５： 接着剤層中に存在するボイド
６： 配線基板と接着剤層との界面に存在するボイド
８： 硬化した接着剤層
９： ワイヤー
１０： 半導体装置
１１： 封止樹脂
Ｉ： 静圧加圧工程
II： 熱硬化工程
III： ワイヤーボンディング工程
IV： モールディング工程
２１： 封止前のマルチスタック型半導体装置
２２： 相対的に上部（第２層）を構成するチップ
２３： 未硬化の接着剤層
２５： 相対的に下部（第１層）を構成するチップ（配線基板）
２６： 接着剤層
２７： チップ搭載用配線基板
３１： チップと未硬化の接着剤層（アンダーフィル材）とが積層（フリップチップボンド）された配線基板
３２： チップ
３３： 未硬化の接着剤層
３４： 配線基板
３５： バンプ
４１： 充分に硬化した接着剤層を有する配線基板
４２： 硬化した接着剤層
４３： ワイヤー
４４： 半導体装置
４５： 封止樹脂
Ｖ： ダイボンディング工程
VI： ワイヤーボンディング工程
VII： モールディング工程 1: Wiring board in which chip and uncured adhesive layer are laminated 2: Chip 3: Uncured adhesive layer 4: Wiring board 5: Void present in adhesive layer 6: Wiring board and adhesive layer 8: Hardened adhesive layer 9: Wire 10: Semiconductor device 11: Sealing resin I: Hydrostatic pressure process
II: Thermosetting process
III: Wire bonding process
IV: Molding process 21: Multi-stack type semiconductor device before sealing 22: Chip that relatively forms upper part (second layer) 23: Uncured adhesive layer 25: Lower part (first layer) Configured chip (wiring board)
26: Adhesive layer 27: Wiring board for chip mounting 31: Wiring board in which chip and uncured adhesive layer (underfill material) are laminated (flip chip bond) 32: Chip 33: Uncured adhesive layer 34: Wiring board 35: Bump 41: Wiring board having a sufficiently hardened adhesive layer 42: Hardened adhesive layer 43: Wire 44: Semiconductor device 45: Sealing resin V: Die bonding process
VI: Wire bonding process
VII: Molding process

Claims (2)

チップと未硬化の接着剤層とが積層された配線基板を加熱して、前記未硬化の接着剤層を硬化させて半導体装置を製造する方法であって、
前記硬化前に、前記チップと未硬化の接着剤層とが積層された配線基板を常圧に対し０．０５ＭＰａ以上の静圧により加圧する静圧加圧工程を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device by heating a wiring substrate in which a chip and an uncured adhesive layer are laminated, curing the uncured adhesive layer,
A semiconductor device comprising: a static pressure pressing step of pressing the wiring board on which the chip and the uncured adhesive layer are laminated with a static pressure of 0.05 MPa or more with respect to normal pressure before the curing. Manufacturing method. 前記静圧加圧工程による加圧状態のまま、前記チップと未硬化の接着剤層とが積層された配線基板を加熱して前記未硬化の接着剤層を硬化する熱硬化工程をさらに含むことを特徴とする請求項１に記載の半導体装置の製造方法。   The method further includes a thermosetting step of curing the uncured adhesive layer by heating the wiring board on which the chip and the uncured adhesive layer are laminated in the pressurized state in the static pressure pressing step. The method of manufacturing a semiconductor device according to claim 1.
JP2007205221A 2006-09-15 2007-08-07 Method for producing semiconductor device Pending JP2008098608A (en)

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JP2010118640A (en) * 2008-10-16 2010-05-27 Sumitomo Bakelite Co Ltd Method of manufacturing semiconductor device and semiconductor device
JP2010245412A (en) * 2009-04-09 2010-10-28 Renesas Electronics Corp Method of manufacturing semiconductor integrated circuit device
JP2011114301A (en) * 2009-11-30 2011-06-09 Lintec Corp Manufacturing method for semiconductor device
WO2023190950A1 (en) * 2022-03-31 2023-10-05 リンテック株式会社 Laminated body manufacturing method

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JP2010118640A (en) * 2008-10-16 2010-05-27 Sumitomo Bakelite Co Ltd Method of manufacturing semiconductor device and semiconductor device
JP2010245412A (en) * 2009-04-09 2010-10-28 Renesas Electronics Corp Method of manufacturing semiconductor integrated circuit device
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JP2011114301A (en) * 2009-11-30 2011-06-09 Lintec Corp Manufacturing method for semiconductor device
WO2023190950A1 (en) * 2022-03-31 2023-10-05 リンテック株式会社 Laminated body manufacturing method

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