JPH1050501A - Chip resistor - Google Patents
Chip resistorInfo
- Publication number
- JPH1050501A JPH1050501A JP8204579A JP20457996A JPH1050501A JP H1050501 A JPH1050501 A JP H1050501A JP 8204579 A JP8204579 A JP 8204579A JP 20457996 A JP20457996 A JP 20457996A JP H1050501 A JPH1050501 A JP H1050501A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- electrode
- electroplating
- chip resistor
- plating bath
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ抵抗器の改
良、詳しくは、絶縁基板上に形成された抵抗素子を被覆
保護する樹脂被膜と当該絶縁基板との密着性に優れたチ
ップ抵抗器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a chip resistor, and more particularly, to a chip resistor excellent in adhesion between a resin film for covering and protecting a resistance element formed on an insulating substrate and the insulating substrate. Things.
【０００２】[0002]
【従来の技術】現在、弱電工業および電子工業分野で
は、電気電子機器の小型化の要請によりセラミック等の
絶縁基板上に抵抗素子を形成して小型化を図った角形チ
ップ抵抗器や、抵抗素子を絶縁基板上に複数形成して各
素子の必要な相互接続を基板内で済ませて集積化を図っ
たチップネットワーク抵抗器などのチップ抵抗器の利用
が盛んである。2. Description of the Related Art At present, in the fields of the light electric industry and the electronics industry, there is a demand for miniaturization of electric and electronic equipment, and a rectangular chip resistor or a resistance element in which a resistance element is formed on an insulating substrate made of ceramic or the like for miniaturization. The use of chip resistors such as a chip network resistor, in which a plurality of elements are formed on an insulating substrate and required interconnection of each element is completed within the substrate, thereby achieving integration.
【０００３】これら従来のチップ抵抗器は、抵抗信頼性
を確保すると共に実装時のハンダ付け性を保証するため
に、その電極を三層構造にしているのが普通である。即
ち、図１〜図４に示すように、絶縁基板10上に形成した
抵抗素子30に直接に連結される銀系の内部電極20と；こ
の内部電極20上に電気メッキされハンダ付け時のハンダ
くわれを防止するニッケル系の中間電極50と；この中間
電極50上に電気メッキされハンダ付け性を実現するスズ
又はスズ−鉛合金系の外部電極60と；の三層構造から電
極が構成されている。そして、最近では、抵抗素子30を
保護するために低融点ガラス被膜の代わりに、熱硬化性
樹脂から成る樹脂被膜40を抵抗素子30の表面に被覆する
ことが行われている。In these conventional chip resistors, the electrodes are usually formed in a three-layer structure in order to ensure resistance reliability and to assure solderability during mounting. That is, as shown in FIGS. 1 to 4, a silver-based internal electrode 20 directly connected to a resistor element 30 formed on an insulating substrate 10; The electrode is composed of a three-layer structure of a nickel-based intermediate electrode 50 for preventing fraying, and a tin or tin-lead alloy-based external electrode 60 which is electroplated on the intermediate electrode 50 to realize solderability. ing. In recent years, in order to protect the resistance element 30, a resin coating 40 made of a thermosetting resin has been applied to the surface of the resistance element 30 instead of the low melting point glass coating.
【０００４】ところが最近、この樹脂被膜タイプのチッ
プ抵抗器の更なる小型化が進められるに従い、外部電極
60（図２参照）のメッキ処理時に、絶縁基板10と樹脂被
膜40との境界部Ｍ（図３参照）が当該メッキ浴により侵
されてしまい、この浸食が内部の抵抗素子30にまで進ん
で抵抗値の変動を来し歩留り低下を齎したり、或いはこ
の浸食により生じた境界部Ｍの隙間に、メッキ浴の金属
成分が残留してしまい特にネットワーク抵抗器（図４参
照）の隣接電極間においてこの導電性残留物Ｅによる短
絡事故が多発するといった問題が生じている。However, recently, with further miniaturization of this resin film type chip resistor, external electrodes have been developed.
During the plating process 60 (see FIG. 2), the boundary M (see FIG. 3) between the insulating substrate 10 and the resin film 40 is eroded by the plating bath, and this erosion proceeds to the internal resistance element 30. A change in the resistance value causes a decrease in the yield, or a metal component of the plating bath remains in the gap at the boundary portion M caused by the erosion, particularly between adjacent electrodes of the network resistor (see FIG. 4). There is a problem that a short circuit accident due to the conductive residue E frequently occurs.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、従来の樹脂
被膜タイプのチップ抵抗器に上記のような問題があった
ことに鑑みて為されたものであり、樹脂被膜と絶縁基板
との密着性に優れており抵抗素子を確実に被覆保護し、
樹脂被膜の剥離や隣接電極間の短絡事故の心配のないチ
ップ抵抗器を提供することを技術的課題とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional resin film type chip resistor, and has been made in consideration of the close contact between the resin film and the insulating substrate. It is excellent in performance and reliably covers and protects the resistance element,
An object of the present invention is to provide a chip resistor which is free from a risk of peeling of a resin film and a short circuit between adjacent electrodes.
【０００６】[0006]
【課題を解決するための手段】本発明者は、長年携わっ
てきた電気メッキ処理の実務を通じ、従来、外部電極の
メッキ形成のために使用されていた強酸性スズ−鉛系メ
ッキ浴が、樹脂被膜や絶縁基板の外表面を侵すだけに停
まらず、実際には、密着状態にある樹脂被膜と絶縁被膜
の境界部に対しても多大なダメージを与えることを突き
止めた。そしてこの絶縁基板と樹脂被膜の境界部の浸食
により両者の密着性が損なわれる結果、樹脂被膜が剥離
し易くなるばかりか、かかる境界部の浸食によって生じ
た隙間にメッキ浴の金属成分が残留してしまい、この導
電性残留物が、特にネットワーク抵抗器における隣接電
極間の短絡を引き起こす事実を見出したのである。SUMMARY OF THE INVENTION The present inventor has developed a strongly acidic tin-lead-based plating bath conventionally used for plating external electrodes through the practice of electroplating, which has been involved for many years. It has been found that it does not stop only by attacking the coating or the outer surface of the insulating substrate, but in fact causes a great deal of damage to the boundary between the resin coating and the insulating coating in close contact. As a result of the erosion at the boundary between the insulating substrate and the resin film, the adhesion between the two is impaired. As a result, not only does the resin film easily peel off, but also the metal component of the plating bath remains in the gap created by the erosion at the boundary. It has been found that this conductive residue causes a short circuit between adjacent electrodes, particularly in a network resistor.
【０００７】そこで、本発明者は、チップ抵抗器におけ
る絶縁基板と樹脂被膜との境界部の浸食を阻止すべく種
々の試行錯誤的実験を繰り返した末、以下の解決手段を
採用することにより上記課題を解決したのである。The inventor of the present invention has conducted various trial and error experiments to prevent the erosion of the boundary between the insulating substrate and the resin film in the chip resistor. The problem was solved.
【０００８】即ち、本発明は、上記技術的課題を解決す
るために、絶縁基板１上に形成された少なくとも一つの
抵抗素子３と、この抵抗素子３に連結された内部電極２
と、当該抵抗素子３を被覆する熱硬化性樹脂から成る樹
脂被膜４と、前記内部電極２上に電気メッキ形成された
中間電極５と、この中間電極５上に電気メッキ形成され
たスズ又はスズ−鉛合金系の外部電極６とを有するチッ
プ抵抗器であって、前記外部電極６をｐＨ３〜６の弱酸
性スズ又はスズ−鉛合金系メッキ浴で電気メッキ形成す
ることにより、前記絶縁基板１と樹脂被膜４との境界部
Ｍのメッキ浴による損傷を防いで当該絶縁基板１と樹脂
被膜４とを密着せしめるという技術的手段を採用した。That is, according to the present invention, in order to solve the above technical problem, at least one resistance element 3 formed on an insulating substrate 1 and an internal electrode 2 connected to the resistance element 3 are provided.
A resin film 4 made of a thermosetting resin for covering the resistance element 3; an intermediate electrode 5 formed by electroplating on the internal electrode 2; and tin or tin formed by electroplating on the intermediate electrode 5. A chip resistor having a lead alloy-based external electrode 6, wherein the external electrode 6 is electroplated in a weakly acidic tin or tin-lead alloy-based plating bath having a pH of 3 to 6 to form the insulating substrate 1. A technical means is adopted in which the insulating substrate 1 and the resin film 4 are brought into close contact with each other by preventing the boundary portion M between the resin film 4 and the resin film 4 from being damaged by the plating bath.
【０００９】なお、ここで、ｐＨ３〜６の弱酸性スズ又
はスズ−鉛合金メッキ浴は、電気メッキ処理時の電流効
率の点からｐＨ４〜５がより好ましい。[0009] Here, the pH of the weakly acidic tin or tin-lead alloy plating bath having a pH of 3 to 6 is more preferably 4 to 5 from the viewpoint of current efficiency during electroplating.
【００１０】また、ここで、熱硬化性樹脂は、尿素樹
脂、メラミン樹脂、グアナミン樹脂などのアミノ樹脂
や、ビスフェノールＡ型、臭素化ビスフェノールＡ型な
どのエポキシ樹脂や、レゾール型などのフェノール樹脂
等を、単独で用いるか二種以上併用することができる。Here, the thermosetting resin may be an amino resin such as a urea resin, a melamine resin or a guanamine resin, an epoxy resin such as a bisphenol A type or a brominated bisphenol A type, or a phenol resin such as a resol type. Can be used alone or in combination of two or more.
【００１１】[0011]
【発明の実施の形態】以下、本発明を添付図面に示す実
施形態に基づき詳しく説明する。なお、図１は従来の角
形チップ抵抗器の概略平面図、図２は図１のＡ−Ａ線上
の部分概略縦断面図、図３は図１のＢ−Ｂ線上の部分概
略横断面図、図４は従来のチップネットワーク抵抗器の
樹脂被膜を一部破断した状態の概略平面図である。図５
は本実施形態のチップ抵抗器の概略平面図、図６は図５
のＣ−Ｃ線上の部分概略縦断面図、図７は図５のＤ−Ｄ
線上の部分概略横断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. 1 is a schematic plan view of a conventional rectangular chip resistor, FIG. 2 is a partial schematic longitudinal sectional view taken along line AA in FIG. 1, FIG. 3 is a partial schematic transverse sectional view taken along line BB in FIG. FIG. 4 is a schematic plan view showing a state in which a resin film of a conventional chip network resistor is partially broken. FIG.
FIG. 6 is a schematic plan view of the chip resistor of the present embodiment, and FIG.
5 is a partial schematic vertical cross-sectional view taken along the line CC of FIG.
It is a partial schematic cross-sectional view on a line.
【００１２】図５〜図７に示す本実施形態の角形チップ
抵抗器は、外部電極６が弱酸性のスズ−鉛合金系メッキ
浴を使用して電気メッキ形成されている点に特徴があ
り、電極構造を含むチップ抵抗器の構造自体は従来品と
変わりはない。したがって、本実施形態のチップ抵抗器
は電極構造の複雑化を伴うことなく製造工程も従来と同
様であるので、製造コスト高を招くこともなく安価な製
造が可能である。以下、本実施形態のチップ抵抗器につ
いて製造工程順に詳しく説明する。The square chip resistor according to the present embodiment shown in FIGS. 5 to 7 is characterized in that the external electrode 6 is formed by electroplating using a weakly acidic tin-lead alloy plating bath. The structure of the chip resistor including the electrode structure itself is not different from the conventional product. Therefore, the chip resistor of the present embodiment has the same manufacturing process as the conventional one without complicating the electrode structure, and can be manufactured at low cost without increasing the manufacturing cost. Hereinafter, the chip resistor of the present embodiment will be described in detail in the order of the manufacturing process.
【００１３】図５〜図７中、符号１で指示するものは直
方平板状のアルミナセラミック材料から成る絶縁基板で
ある。まず、この絶縁基板１の両端部の所定位置に銀系
ペーストをスクリーン印刷して、その後高温焼成するこ
とによって一対の銀系の内部電極２・２を形成する。In FIG. 5 to FIG. 7, what is indicated by reference numeral 1 is a rectangular plate-shaped insulating substrate made of an alumina ceramic material. First, a silver-based paste is screen-printed at predetermined positions on both ends of the insulating substrate 1 and then fired at a high temperature to form a pair of silver-based internal electrodes 2.
【００１４】次いで、これら内部電極２・２間に酸化ル
テニウム系ペーストを、当該内部電極２に一部オーバー
レイした状態でスクリーン印刷してその後高温焼成する
ことによって抵抗素子３を形成する。Next, a ruthenium oxide-based paste is screen-printed between the internal electrodes 2 in a state of being partially overlaid on the internal electrodes 2 and then fired at a high temperature to form the resistance element 3.
【００１５】そして、このオーバーレイ部分を含み当該
抵抗素子３の全体を覆うようにしてアミノ樹脂及びエポ
キシ樹脂から成る熱硬化性樹脂の樹脂ペーストをスクリ
ーン印刷した後、高温焼成することによって樹脂被膜４
を形成する。Then, a resin paste of a thermosetting resin composed of an amino resin and an epoxy resin is screen-printed so as to cover the entire resistive element 3 including the overlay portion, and then fired at a high temperature to form a resin coating 4.
To form
【００１６】そして、水洗処理を挟みながら脱脂、中
和、酸活性の各処理を順に行った後、下記のニッケルメ
ッキ浴を用いてバレル式電気メッキ処理を施すことによ
って、前記内部電極２・２の露出部に各々膜厚約６μｍ
のニッケル系の中間電極５・５を電気メッキ形成する。After the degreasing, neutralization, and acid activity treatments are sequentially performed while sandwiching the water washing treatment, the internal electrodes 2 and 2 are subjected to barrel-type electroplating treatment using the following nickel plating bath. About 6 μm on each exposed part
Is formed by electroplating.
【００１７】 「ニッケル系メッキ浴」 硫酸ニッケル ３００ｇ／リットル 塩化ニッケル ５０ｇ／リットル ホウ酸 ５０ｇ／リットル ｐＨ 3.５ 浴温度 ５０℃ 電流密度 0.５Ａ/dm2 [Nickel-based plating bath] Nickel sulfate 300 g / l Nickel chloride 50 g / l Boric acid 50 g / l pH 3.5 Bath temperature 50 ° C Current density 0.5 A / dm 2
【００１８】そして、水洗処理した後に、下記の弱酸性
のスズ−鉛合金メッキ浴を用いてバレル式電気メッキ処
理を施すことによって、前記ニッケル系の中間電極５・
５の表面上に各々膜厚約６μｍのスズ−鉛合金系の外部
電極６・６を電気メッキ形成する。After washing with water, barrel-type electroplating is performed using the following weakly acidic tin-lead alloy plating bath, whereby the nickel-based intermediate electrode 5.
The outer electrodes 6.6 each having a thickness of about 6 μm and made of a tin-lead alloy are formed by electroplating on the surface of each of the electrodes 5.
【００１９】 「弱酸性スズ−鉛合金メッキ浴」 スズ塩（スルホコハク酸第一スズ） １４ｇ／リットル 鉛塩（スルホコハク酸鉛） １ｇ／リットル 伝導性塩（スルホコハク酸のエチレンジアミン塩） ２モル／リットル キレート剤（ＥＤＴＡ） 0.１モル／リットル ｐＨ調整剤 適量 ｐＨ ４ 浴温度 ２０℃ 電流密度 0.５Ａ/dm2 "Weakly acidic tin-lead alloy plating bath" Tin salt (stannous sulfosuccinate) 14 g / liter Lead salt (lead sulfosuccinate) 1 g / liter Conductive salt (ethylenediamine salt of sulfosuccinic acid) 2 mol / liter chelate Agent (EDTA) 0.1 mol / l pH adjuster qs pH4 bath temperature 20 ° C current density 0.5A / dm 2
【００２０】そして、水洗処理後に、変色防止処理、水
洗・乾燥処理を施して本実施形態のチップ抵抗器の完成
品を得る。Then, after the water washing treatment, a discoloration prevention treatment and a water washing / drying treatment are performed to obtain a finished product of the chip resistor of the present embodiment.
【００２１】このように、本実施形態においては、弱酸
性スズ−鉛合金メッキ浴（ｐＨ４）を用いて外部電極６
を電気メッキ形成しているので、絶縁基板１と樹脂被膜
４との境界部Ｍのスズ−鉛合金メッキ浴によるダメージ
もなく、境界部Ｍが浸食されることがない。したがっ
て、ｐＨ１以下の強酸性のスズ−鉛合金メッキ浴を使用
していた従来とは異なり、絶縁基板１と樹脂被膜４の境
界部Ｍの密着性が損なわれてしまい樹脂被膜４が簡単に
剥離する問題もないのである。As described above, in this embodiment, the external electrode 6 is formed by using a weakly acidic tin-lead alloy plating bath (pH 4).
Is formed by electroplating, the boundary portion M between the insulating substrate 1 and the resin film 4 is not damaged by the tin-lead alloy plating bath, and the boundary portion M is not eroded. Therefore, unlike the conventional method using a strongly acidic tin-lead alloy plating bath having a pH of 1 or less, the adhesion between the insulating substrate 1 and the boundary portion M between the resin film 4 is impaired, and the resin film 4 is easily peeled off. There is no problem to do it.
【００２２】また、スズ−鉛合金メッキ浴によって境界
部Ｍが浸食されて其処に隙間が生ずることもないので、
従来のチップネットワーク抵抗器（図４参照）の如く、
境界部Ｍの隙間にメッキ浴の金属成分が残留してしま
い、この導電性残留物によって隣接電極間の短絡事故が
発生することもない。Further, since the boundary portion M is not eroded by the tin-lead alloy plating bath and no gap is formed there,
Like a conventional chip network resistor (see FIG. 4),
The metal component of the plating bath remains in the gap at the boundary portion M, and the conductive residue does not cause a short circuit between adjacent electrodes.
【００２３】『実施例』ｐＨ１以下の強酸性スズ−鉛合
金メッキ浴を用いて外部電極をメッキ形成した従来のチ
ップ抵抗器（比較例；計２００個）と、ｐＨ４の弱酸性
のスズ−鉛合金メッキ浴を用いて外部電極をメッキ形成
した本実施形態のチップ抵抗器（実施例；計２００個）
について、樹脂被膜の剥離性に関して比較実験を行なっ
た。Example A conventional chip resistor (comparative example; total of 200 pieces) in which external electrodes were formed by plating using a strongly acidic tin-lead alloy plating bath having a pH of 1 or less, and a weakly acidic tin-lead having a pH of 4 Chip resistors of the present embodiment in which external electrodes are formed by plating using an alloy plating bath (Examples: 200 total)
, A comparative experiment was conducted on the peelability of the resin film.
【００２４】この比較試験は、各チップ抵抗器をその樹
脂被膜を下にして両面接着テープに接着しておいて、一
方の電極端子を垂直方向へ引き起こした際の樹脂被膜と
絶縁基板との剥離の有無を調べる試験である。実験結果
は、従来のチップ抵抗器（比較例）は、２００個のうち
６６個が剥離したのに対し、本実施形態のチップ抵抗器
において樹脂被膜が剥離したのは皆無であった。In this comparative test, each chip resistor was adhered to a double-sided adhesive tape with its resin film facing down, and the resin film was peeled off from the insulating substrate when one electrode terminal was raised in the vertical direction. This is a test to check for the presence or absence of As a result of the experiment, 66 pieces out of 200 pieces of the conventional chip resistor (comparative example) were peeled off, but no resin film was peeled off in the chip resistor of the present embodiment.
【００２５】以上、実施形態を例に本発明を説明した
が、本発明は上記実施形態に限定されるものではなく
「特許請求の範囲」の記載内において種々の変更が可能
である。As described above, the present invention has been described by taking the embodiment as an example. However, the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the claims.
【００２６】例えば、上記実施形態では、絶縁基板１上
にただ一つの抵抗素子３が形成されて成る角形チップ抵
抗器を説明したが、これに限定されるものではなく、抵
抗素子が絶縁基板上に複数形成されていて各素子の必要
な相互接続を基板内で済ませたネットワーク抵抗器とし
て構成しても良いことは勿論である。For example, in the above-described embodiment, a rectangular chip resistor in which only one resistance element 3 is formed on the insulating substrate 1 has been described. However, the present invention is not limited to this. It is needless to say that a network resistor may be formed in which a plurality of elements are formed and the necessary interconnection of each element is completed in the substrate.
【００２７】また、外部電極６を電気メッキ形成するた
めの、弱酸性スズ又はスズ−鉛合金メッキ浴に関して
も、上記実施形態に限定されるものではなく、ｐＨ３〜
６の弱酸性の範囲であればメッキ浴の組成は任意に変更
可能であり、また、メッキ条件も前述した上記実施形態
に限定されるものではなく種々の変更が可能である。Further, the weak acid tin or tin-lead alloy plating bath for forming the external electrode 6 by electroplating is not limited to the above-described embodiment, but has a pH of 3 to 5.
The composition of the plating bath can be arbitrarily changed within a weakly acidic range of 6, and the plating conditions are not limited to the above-described embodiment, but can be variously changed.
【００２８】[0028]
【発明の効果】以上、実施形態をもって説明したとお
り、本発明に係るチップ抵抗器にあっては、外部電極
を、弱酸性のスズ又はスズ−鉛系メッキ浴により電気メ
ッキ形成しているので、絶縁基板と樹脂被膜との境界部
のスズ−鉛合金メッキ浴によるダメージもなく、当該境
界部が浸食されることがない。したがって、ｐＨ１以下
の強酸性のスズ−鉛合金メッキ浴を使用していた従来と
は異なり、絶縁基板と樹脂被膜との境界部の密着性に優
れており、樹脂被膜が簡単に剥離する問題もない。As described above in the embodiment, in the chip resistor according to the present invention, the external electrodes are formed by electroplating with a weakly acidic tin or tin-lead plating bath. The boundary between the insulating substrate and the resin film is not damaged by the tin-lead alloy plating bath, and the boundary is not eroded. Therefore, unlike the conventional method using a strongly acidic tin-lead alloy plating bath having a pH of 1 or less, the adhesion at the boundary between the insulating substrate and the resin film is excellent, and there is also a problem that the resin film is easily peeled off. Absent.
【００２９】また、弱酸性のスズ又はスズ−鉛合金メッ
キ浴により当該境界部が浸食されて其処に隙間が生ずる
こともないので、従来のチップネットワーク抵抗器とは
異なり、境界部の隙間にメッキ浴の金属成分が残留して
隣接電極間において短絡事故が多発するようなこともな
い。Further, since the boundary is not eroded by the weakly acidic tin or tin-lead alloy plating bath and a gap is not formed there, unlike the conventional chip network resistor, the gap at the boundary is plated. The metal component of the bath does not remain and short-circuit accidents frequently occur between adjacent electrodes.
【図１】従来の角形チップ抵抗器の概略平面図である。FIG. 1 is a schematic plan view of a conventional square chip resistor.
【図２】図１のＡ−Ａ線上の部分概略縦断面図である。FIG. 2 is a partial schematic longitudinal sectional view taken along line AA of FIG.
【図３】図１のＢ−Ｂ線上の部分概略横断面図である。FIG. 3 is a partial schematic cross-sectional view taken along the line BB of FIG. 1;
【図４】従来のチップネットワーク抵抗器の樹脂被膜を
一部破断した状態の概略平面図である。FIG. 4 is a schematic plan view showing a state in which a resin coating of a conventional chip network resistor is partially broken.
【図５】本実施形態のチップ抵抗器の概略平面図であ
る。FIG. 5 is a schematic plan view of the chip resistor of the present embodiment.
【図６】図５のＣ−Ｃ線上の部分概略縦断面図である。FIG. 6 is a partial schematic longitudinal sectional view taken along line CC of FIG. 5;
【図７】図５のＤ−Ｄ線上の部分概略横断面図である。FIG. 7 is a partial schematic cross-sectional view taken along line DD of FIG. 5;
１ 絶縁基板 ２ 内部電極 ３ 抵抗素子 ４ 樹脂被膜 ５ 中間電極 ６ 外部電極 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Internal electrode 3 Resistance element 4 Resin coating 5 Intermediate electrode 6 External electrode
Claims (1)
つの抵抗素子３と、この抵抗素子３に連結された内部電
極２と、当該抵抗素子３を被覆する熱硬化性樹脂から成
る樹脂被膜４と、前記内部電極２上に電気メッキ形成さ
れた中間電極５と、この中間電極５上に電気メッキ形成
されたスズ又はスズ−鉛合金系の外部電極６とを有する
チップ抵抗器であって、 前記外部電極６をｐＨ３〜６の弱酸性スズ又はスズ−鉛
合金系メッキ浴で電気メッキ形成することにより、前記
絶縁基板１と樹脂被膜４との境界部Ｍのメッキ浴による
損傷を防いで当該絶縁基板１と樹脂被膜４とを密着せし
めたことを特徴とするチップ抵抗器。At least one resistive element formed on an insulating substrate, an internal electrode connected to the resistive element, and a resin coating made of a thermosetting resin covering the resistive element. A chip resistor comprising: an intermediate electrode 5 electroplated on the internal electrode 2; and a tin or tin-lead alloy-based external electrode 6 electroplated on the intermediate electrode 5. The external electrode 6 is formed by electroplating in a weakly acidic tin or tin-lead alloy-based plating bath having a pH of 3 to 6, thereby preventing a boundary portion M between the insulating substrate 1 and the resin coating 4 from being damaged by the plating bath. A chip resistor comprising an insulating substrate 1 and a resin film 4 adhered to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8204579A JPH1050501A (en) | 1996-08-02 | 1996-08-02 | Chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8204579A JPH1050501A (en) | 1996-08-02 | 1996-08-02 | Chip resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1050501A true JPH1050501A (en) | 1998-02-20 |
Family
ID=16492813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8204579A Pending JPH1050501A (en) | 1996-08-02 | 1996-08-02 | Chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1050501A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666547B2 (en) | 2002-10-08 | 2017-05-30 | Honeywell International Inc. | Method of refining solder materials |
-
1996
- 1996-08-02 JP JP8204579A patent/JPH1050501A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666547B2 (en) | 2002-10-08 | 2017-05-30 | Honeywell International Inc. | Method of refining solder materials |
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