JPH10340994A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10340994A JPH10340994A JP9149164A JP14916497A JPH10340994A JP H10340994 A JPH10340994 A JP H10340994A JP 9149164 A JP9149164 A JP 9149164A JP 14916497 A JP14916497 A JP 14916497A JP H10340994 A JPH10340994 A JP H10340994A
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- JP
- Japan
- Prior art keywords
- film
- capacitor
- temperature
- partial pressure
- oxygen partial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高誘電体膜をキャ
パシタの絶縁膜とした半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device using a high dielectric film as an insulating film of a capacitor.
【０００２】[0002]
【従来の技術】近年、半導体集積回路の高集積化に伴
い、回路の微細化は進む一方であり、メモリセルにおい
てはキャパシタのセル面積も非常に小さくなっている。
セル面積の縮小化に伴いキャパシタ容量も小さくなって
しまうが、感度やソフトエラー等の点からキャパシタ容
量はそれほど小さくできないという要請がある。キャパ
シタ容量の低下を防ぐ方法として、キャパシタを三次元
的に形成してセル面積をできるだけ広くしてキャパシタ
容量を稼ぐ方法と、キャパシタ絶縁膜に誘電率の高い物
質を用いる方法が検討されている。誘電率の高い絶縁膜
として、例えば（Ｂａ，Ｓｒ）ＴｉＯ3 膜をキャパシタ
絶縁膜として用いることが検討されている。2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated, circuit miniaturization has been progressing, and the cell area of a capacitor in a memory cell has become very small.
As the cell area decreases, the capacitance of the capacitor also decreases. However, there is a demand that the capacitance of the capacitor cannot be reduced so much in terms of sensitivity and soft error. As a method of preventing a decrease in the capacitance of the capacitor, a method of forming the capacitor three-dimensionally to increase the cell area as much as possible to increase the capacitance of the capacitor and a method of using a substance having a high dielectric constant for the capacitor insulating film are being studied. It has been studied to use, for example, a (Ba, Sr) TiO 3 film as a capacitor insulating film as an insulating film having a high dielectric constant.
【０００３】高い誘電率の（Ｂａ，Ｓｒ）ＴｉＯ3 膜を
得るには、４５０℃以下の基板温度でアモルファス膜を
成膜した後にアニールして結晶化させる方法と、６００
℃以上の基板温度で多結晶の（Ｂａ，Ｓｒ）ＴｉＯ3 を
形成して得る方法がある。これら二つの方法を比べる
と、結晶化温度以上の温度で成膜した（Ｂａ，Ｓｒ）Ｔ
ｉＯ3 の方が結晶粒が大きく、誘電率も高いことが実験
より判明している。In order to obtain a (Ba, Sr) TiO 3 film having a high dielectric constant, a method of forming an amorphous film at a substrate temperature of 450 ° C. or lower, followed by annealing and crystallizing the film,
There is a method in which polycrystalline (Ba, Sr) TiO 3 is formed at a substrate temperature of not less than ° C. Comparing these two methods, (Ba, Sr) T formed at a temperature higher than the crystallization temperature
Experiments have shown that iO 3 has larger crystal grains and a higher dielectric constant.
【０００４】（Ｂａ，Ｓｒ）ＴｉＯ3 膜は、酸素を含む
雰囲気中で形成しなければならないため、キャパシタの
下部電極として高温でも酸化されにくいプラチナの使用
が検討されていた。しかし、Ｐｔは加工性が悪いため、
現在では、酸化されても金属導電性を示すＲｕ膜やＩｒ
膜を用いることが検討されている。Since the (Ba, Sr) TiO 3 film must be formed in an atmosphere containing oxygen, the use of platinum which is hardly oxidized even at a high temperature as a lower electrode of a capacitor has been studied. However, since Pt has poor workability,
At present, Ru films and Ir films exhibiting metal conductivity even when oxidized are used.
The use of membranes is being considered.
【０００５】ところが、下部電極にＰｔを用いていた時
と同様に、（Ｂａ，Ｓｒ）ＴｉＯ3膜を６００℃以上の
基板温度で形成し結晶化させて高い誘電率を得ようとす
ると、図１３に示すように、（Ｂａ，Ｓｒ）ＴｉＯ3 膜
４１の成膜時に下部電極であるＲｕ膜４２の表面の酸化
が著しくＲｕＯ2 ４３が形成される。ＲｕＯ2 ４３の形
成に伴い、体積膨張が起こりＲｕ膜４２表面のモフォロ
ジーが悪化する。下部電極表面のモフォロジーが劣化す
ると、キャパシタ絶縁膜中に発生するクラックによる上
部電極と下部電極でのショート、あるいは凹凸部での電
界集中によるリーク電流の増大という問題がある。However, as in the case where Pt is used for the lower electrode, when a (Ba, Sr) TiO 3 film is formed at a substrate temperature of 600 ° C. or more and crystallized to obtain a high dielectric constant, As shown in FIG. 13, when the (Ba, Sr) TiO 3 film 41 is formed, the surface of the Ru film 42 serving as the lower electrode is significantly oxidized, and RuO 2 43 is formed. With the formation of RuO 2 43, volume expansion occurs and the morphology of the surface of the Ru film 42 deteriorates. When the morphology of the lower electrode surface is deteriorated, there is a problem that a short circuit occurs between the upper electrode and the lower electrode due to a crack generated in the capacitor insulating film, or a leak current increases due to electric field concentration at the uneven portion.
【０００６】一方、４５０℃以下の温度で（Ｂａ，Ｓ
ｒ）ＴｉＯ3 膜を成膜した後にアニールした場合は、Ｒ
ｕ表面のモフォロジー劣化は見られず、良好なリーク電
流特性が得られるものの、誘電率が低く小さなキャパシ
タ容量しか得られないという問題がある。On the other hand, at a temperature of 450 ° C. or less, (Ba, S
r) When annealing is performed after forming the TiO 3 film, R
Although the morphology of the u surface is not deteriorated and good leakage current characteristics are obtained, there is a problem that the dielectric constant is low and only a small capacitor capacity can be obtained.
【０００７】また、図１４に示すように、Ｒｕ膜４２を
堆積した後にＲｕＯ2 ４４を形成された積層構造の下部
電極を用いる場合、６００℃以上の温度で（Ｂａ，Ｓ
ｒ）ＴｉＯ3 膜４１を成膜すると、ＲｕＯ2 ４４／Ｒｕ
膜４２界面のＲｕ膜４２の酸化によりモフォロジーの劣
化が生じ、Ｒｕ電極を用いた場合と同様にリーク電流が
生じるという問題がある。また、Ｒｕの代わりにＩｒ、
ＲｕＯ2 の代わりにＩｒＯ2 を用いた場合も同様の問題
が生じる。Further, as shown in FIG. 14, when a lower electrode having a laminated structure in which RuO 2 44 is formed after depositing a Ru film 42 is used, (Ba, S
r) When the TiO 3 film 41 is formed, RuO 2 44 / Ru
Oxidation of the Ru film 42 at the interface of the film 42 causes deterioration of morphology, which causes a problem that a leak current occurs as in the case of using the Ru electrode. Also, instead of Ru, Ir,
A similar problem occurs when IrO 2 is used instead of RuO 2 .
【０００８】[0008]
【発明が解決しようとする課題】上記したように、キャ
パシタのＲｕ，ＲｕＯ2 ，Ｉｒ或いはＩｒＯ2 上にＳｒ
ＴｉＯ3 或いは（Ｂａ，Ｓｒ）ＴｉＯ3 を形成するとシ
ョートの発生，リーク電流の増加若しくは誘電率の低下
が生じるという問題がある。本発明の目的は、高容量且
つ低リーク電流のキャパシタを形成し得る半導体装置の
製造方法を提供することにある。As described above, Sr is placed on Ru, RuO 2 , Ir or IrO 2 of a capacitor.
When TiO 3 or (Ba, Sr) TiO 3 is formed, there is a problem that a short circuit occurs, a leak current increases, or a dielectric constant decreases. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a capacitor having high capacitance and low leakage current.
【０００９】[0009]
［構成］本発明は、上記目的を達成するために以下のよ
うに構成されている。 （１） 本発明（請求項１）は、Ｒｕ，Ｉｒ，ＲｕとＲ
ｕＯ2 との積層構造或いはＩｒとＩｒＯ2 との積層構造
からなるキャパシタの下部電極上に、該キャパシタの絶
縁膜としてペロブスカイト構造の絶縁体を形成する半導
体装置の製造方法であって、前記絶縁体を結晶化温度以
上６００℃未満の基板温度で形成することを特徴とす
る。[Configuration] The present invention is configured as described below to achieve the above object. (1) The present invention (Claim 1) uses Ru, Ir, Ru and R
A method of manufacturing a semiconductor device, comprising forming an insulator having a perovskite structure as an insulating film of a capacitor on a lower electrode of a capacitor having a stacked structure of uO 2 or a stacked structure of Ir and IrO 2. Is formed at a substrate temperature equal to or higher than the crystallization temperature and lower than 600 ° C.
【００１０】本発明の好ましい実施態様を以下に記す。
前記絶縁体として（Ｂａ，Ｓｒ）ＴｉＯ3 膜を形成する
場合、前記基板温度が４７０℃以上６００℃未満であ
る。Preferred embodiments of the present invention are described below.
When a (Ba, Sr) TiO 3 film is formed as the insulator, the substrate temperature is 470 ° C. or more and less than 600 ° C.
【００１１】前記絶縁体としてＳｒＴｉＯ3 膜を形成す
る場合、前記基板温度が４３０℃以上６００℃未満であ
る。前記絶縁体の成膜時間が５分以内である。When the SrTiO 3 film is formed as the insulator, the substrate temperature is 430 ° C. or more and less than 600 ° C. The film formation time of the insulator is within 5 minutes.
【００１２】前記基板温度まで加熱する際、昇温速度が
１００℃／ｍｉｎ以上である。 ［作用］本発明は、上記構成によって以下の作用・効果
を有する。When heating to the substrate temperature, the rate of temperature rise is 100 ° C./min or more. [Operation] The present invention has the following operation / effect by the above configuration.
【００１３】発明者の研究により、下部電極の表面粗さ
が３．５ｎｍ以上になると、リーク電流が増加すること
が判明した。下部電極の表面は、上部にＳｒＴｉＯ3 若
しくは（Ｂａ，Ｓｒ）ＴｉＯ3 膜絶縁膜を成膜する際の
酸素によって荒らされる。従って、ＳｒＴｉＯ3 若しく
は（Ｂａ，Ｓｒ）ＴｉＯ3 膜の成膜の際に、下部電極の
表面粗さを３．５ｎｍ以下に抑える必要がある。According to the study of the inventor, it has been found that when the surface roughness of the lower electrode becomes 3.5 nm or more, the leak current increases. The surface of the lower electrode is roughened by oxygen when an SrTiO 3 or (Ba, Sr) TiO 3 film insulating film is formed on the upper portion. Therefore, it is necessary to suppress the surface roughness of the lower electrode to 3.5 nm or less when forming the SrTiO 3 or (Ba, Sr) TiO 3 film.
【００１４】そこで、本発明のプロセス条件を用いて、
Ｒｕ，Ｒｕ／ＲｕＯ2 ，Ｉｒ，Ｉｒ／ＩｒＯ2 からなる
下部電極上に、ＳｒＴｉＯ3 若しくは（Ｂａ，Ｓｒ）Ｔ
ｉＯ3 膜を形成することによって、表面粗さが少なくリ
ーク電流が少ないキャパシタを形成することができる。Therefore, using the process conditions of the present invention,
Ru, Ru / RuO 2 , Ir, Ir / IrO 2 on a lower electrode made of SrTiO 3 or (Ba, Sr) T
By forming the iO 3 film, a capacitor having a small surface roughness and a small leak current can be formed.
【００１５】また、基板温度範囲において形成されるＳ
ｒＴｉＯ3 若しくは（Ｂａ，Ｓｒ）ＴｉＯ3 膜の誘電率
は十分高いので、容量の大きいキャパシタを形成するこ
とができる。The S formed in the substrate temperature range is
Since the dielectric constant of the rTiO 3 or (Ba, Sr) TiO 3 film is sufficiently high, a capacitor having a large capacitance can be formed.
【００１６】[0016]
【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。 ［第１実施形態］（Ｂａ，Ｓｒ）ＴｉＯ3 膜の成膜時の
パラメータを変えて成膜を行い、表面粗さをＡＦＭで測
定した。以下に、Ｒｕ下部電極上に３５０ｎｍの（Ｂ
ａ，Ｓｒ）ＴｉＯ3 膜を堆積した場合の各種パラーメー
タ依存性に関して説明する。Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] A (Ba, Sr) TiO 3 film was formed by changing parameters at the time of film formation, and the surface roughness was measured by AFM. In the following, 350 nm (B) is formed on the Ru lower electrode.
A description will be given of the dependence of various parameters upon deposition of the (a, Sr) TiO 3 film.
【００１７】図１は、昇温時の酸素分圧を０．０１Ｐ
ａ，昇温速度を５００℃／ｍｉｎ，成膜中の酸素分圧を
０．１Ｐａ及び成膜速度を１０ｎｍ／ｍｉｎで成膜した
場合の表面粗さの基板温度依存性を示す特性図である。
６００℃以上で成膜すると、表面粗さは４ｎｍを超える
ことがわかる。従って、リーク電流を抑えるためには、
基板温度を６００℃未満にしてキャパシタ絶縁膜を成膜
する必要があることがわかる。FIG. 1 shows that the oxygen partial pressure at the time of temperature rise is 0.01 P
a is a characteristic diagram showing the substrate temperature dependence of surface roughness when a film is formed at a temperature rising rate of 500 ° C./min, an oxygen partial pressure of 0.1 Pa during film formation, and a film forming rate of 10 nm / min. .
It can be seen that when the film is formed at a temperature of 600 ° C. or higher, the surface roughness exceeds 4 nm. Therefore, to suppress the leakage current,
It can be seen that it is necessary to set the substrate temperature to less than 600 ° C. to form the capacitor insulating film.
【００１８】また、図２にＳｒＴｉＯ3 膜及び（Ｂａ，
Ｓｒ）ＴｉＯ3 膜の誘電率の基板温度依存性を示す。Ｓ
ｒＴｉＯ3 膜の場合には、４３０℃以上、（Ｂａ，Ｓ
ｒ）ＴｉＯ3 膜の４７０℃以上の温度で成長させると、
結晶化が起こり高い誘電率の膜を得ることができる。FIG. 2 shows an SrTiO 3 film and (Ba,
4 shows the substrate temperature dependence of the dielectric constant of the Sr) TiO 3 film. S
In the case of the rTiO 3 film, the temperature is 430 ° C. or more, (Ba, S
r) When the TiO 3 film is grown at a temperature of 470 ° C. or more,
Crystallization occurs and a film having a high dielectric constant can be obtained.
【００１９】以上の条件から、ＳｒＴｉＯ3 膜の場合に
は４３０℃以上６００℃未満、（Ｂａ，Ｓｒ）ＴｉＯ3
膜の場合には４７０℃以上６００℃未満の温度で形成す
ることによって、容量が大きくリーク電流の少ないキャ
パシタを形成することができる。From the above conditions, in the case of the SrTiO 3 film, the temperature is 430 ° C. or more and less than 600 ° C., and (Ba, Sr) TiO 3
In the case of a film, a capacitor having a large capacitance and a small leak current can be formed by forming the film at a temperature of 470 ° C. or higher and lower than 600 ° C.
【００２０】また、基板温度以外にも、以下に記すよう
な好ましい成膜条件がある。図３は昇温時の酸素分圧
０．０１Ｐａ、成膜時の基板温度５５０℃、成膜時の酸
素分圧０．１Ｐａとした場合の成膜時間に関するグラフ
である。なお、（Ｂａ，Ｓｒ）ＴｉＯ3 膜の膜厚は３０
ｎｍである。成膜速度が遅い場合は所望の膜厚を得るた
めに長時間酸化性雰囲気にさらされるため、表面モフォ
ロジーの劣化が起きる。そのため、表面粗さを３ｎｍ以
下にするために、成膜時間を５分以下にすることが好ま
しい。In addition to the substrate temperature, there are other preferable film forming conditions as described below. FIG. 3 is a graph relating to the film formation time when the oxygen partial pressure at the time of temperature rise is 0.01 Pa, the substrate temperature at the time of film formation is 550 ° C., and the oxygen partial pressure at the time of film formation is 0.1 Pa. The thickness of the (Ba, Sr) TiO 3 film is 30
nm. When the film forming rate is low, the film is exposed to an oxidizing atmosphere for a long time to obtain a desired film thickness, so that the surface morphology is deteriorated. Therefore, in order to reduce the surface roughness to 3 nm or less, the film formation time is preferably set to 5 minutes or less.
【００２１】図４は、昇温時の酸素分圧を成膜時の酸素
分圧と同じにした場合の成膜時酸素分圧依存性を示すグ
ラフである。表面粗さが少なく良好なリーク電流特性を
有するキャパシタを得るためには、成膜時の酸素分圧を
０．５Ｐａ以下にすることが好ましい。FIG. 4 is a graph showing the oxygen partial pressure dependence during film formation when the oxygen partial pressure during temperature rise is the same as the oxygen partial pressure during film formation. In order to obtain a capacitor having a small surface roughness and good leak current characteristics, it is preferable that the oxygen partial pressure during film formation be 0.5 Pa or less.
【００２２】図５は、昇温時の酸素分圧０．０１Ｐａ、
成膜中の酸素分圧０．１Ｐａ、成膜時の基板温度５５０
℃、成膜速度１０ｎｍ／ｍｉｎとした場合の基板の昇温
速度依存性に関するグラフである。この図から、基板の
昇温速度は１００ｎｍ／ｍｉｎ以上にすると、表面粗さ
が３ｎｍ以下になることが分かる。従って、昇温温度を
１００ｎｍ／ｍｉｎ以上にすることが好ましい。FIG. 5 shows an oxygen partial pressure of 0.01 Pa when the temperature is raised,
Oxygen partial pressure 0.1 Pa during film formation, substrate temperature 550 during film formation
FIG. 6 is a graph showing the dependence of the substrate on the rate of temperature rise when the film formation rate is 10 nm / min. From this figure, it can be seen that when the temperature rise rate of the substrate is 100 nm / min or more, the surface roughness becomes 3 nm or less. Therefore, it is preferable that the temperature increase temperature be 100 nm / min or more.
【００２３】また、図６は成膜条件を昇温速度１００℃
／ｍｉｎ，成膜中の酸素分圧１．０Ｐａ，成膜時の基板
温度５５０℃及び成膜速度１０ｍ／ｍｉｎとした場合の
基板昇温時の酸素分圧依存性に関するグラフである。こ
の場合は違いが顕著に見られるように基板の昇温速度を
遅く、また、成膜中の酸素分圧を高めにしてある。グラ
フより、昇温時の酸素分圧は１０-2Ｐａ以下の酸素分圧
が望ましいことがわかる。FIG. 6 shows a film forming condition in which the temperature was raised at a rate of 100 ° C.
6 is a graph showing the oxygen partial pressure dependency when the substrate temperature is raised when the substrate temperature is 550 ° C. and the film forming speed is 10 m / min. In this case, the temperature rise rate of the substrate is slowed down and the oxygen partial pressure during film formation is increased so that the difference is remarkably seen. From the graph, it is understood that the oxygen partial pressure at the time of temperature rise is desirably 10 −2 Pa or less.
【００２４】なお、本実施形態では、下部電極としてＲ
ｕ膜を用いたが、Ｒｕ／ＲｕＯ2 膜，Ｉｒ或いはＩｒ／
ＩｒＯ2 膜を下部電極として用いた場合も同様な結果が
得られた。In this embodiment, R is used as the lower electrode.
Although a u film was used, a Ru / RuO 2 film, Ir or Ir /
Similar results were obtained when the IrO 2 film was used as the lower electrode.
【００２５】［第２実施形態］本実施形態では、下部電
極としてＲｕ膜を用い、絶縁膜として（Ｂａ，Ｓｒ）Ｔ
ｉＯ3 膜を用いたキャパシタの形成について説明する。[Second Embodiment] In this embodiment, a Ru film is used as a lower electrode, and (Ba, Sr) T is used as an insulating film.
The formation of a capacitor using the iO 3 film will be described.
【００２６】図７，８は本発明の第２実施形態に係わる
キャパシタの製造工程を示す工程断面図である。先ず、
ｐタイプシリコン基板１０上に素子を分離する素子分離
領域１１を形成した後、トランジスタのゲート絶縁膜１
２，ゲート電極（ワード線）１３，ｎ+拡散層１４（１
４ａ，１４ｂ）を形成する。そして、全面に第１の層間
絶縁膜１５を堆積する。その後、ｎ+ 拡散層１４ａに接
続するコンタクトホールを第１の層間絶縁膜１５に形成
する。そして、コンタクトホールを通してｎ+ 拡散層１
４ａに電気的に接続するビット線１６を形成する。そし
て、全面に第２の層間絶縁膜１７を形成する。第１及び
第２の層間絶縁膜１５，１７にｎ+ 拡散層１４ｂに接続
するコンタクトホールを開孔した後、全面にｎ+ 多結晶
シリコン１８を堆積する。そして、エッチバック法若し
くはＣＭＰ法を用いてｎ+ 多結晶シリコンを後退させ、
コンタクトホール内にのみｎ+ 多結晶シリコン１８を埋
め込む（図７（ａ））。FIGS. 7 and 8 are sectional views showing the steps of manufacturing a capacitor according to the second embodiment of the present invention. First,
After forming an element isolation region 11 for isolating elements on a p-type silicon substrate 10, the gate insulating film 1 of the transistor is formed.
2, gate electrode (word line) 13, n + diffusion layer 14 (1
4a, 14b) are formed. Then, a first interlayer insulating film 15 is deposited on the entire surface. Thereafter, a contact hole connected to n + diffusion layer 14a is formed in first interlayer insulating film 15. Then, the n + diffusion layer 1 is formed through the contact hole.
A bit line 16 electrically connected to 4a is formed. Then, a second interlayer insulating film 17 is formed on the entire surface. After a contact hole connected to the first and second interlayer insulating films 15 and 17 to the n + diffusion layer 14b, depositing a n + polycrystalline silicon 18 on the entire surface. Then, the n + polycrystalline silicon is retracted by using the etch-back method or the CMP method,
The n + polycrystalline silicon 18 is buried only in the contact hole (FIG. 7A).
【００２７】次いで、酸素を含む雰囲気中でＲｕ膜１９
を全面に堆積し（図７（ｂ））、キャパシタの下部電極
として柱状に加工する（図７（ｃ））。そして、全面
に、（Ｂａ，Ｓｒ）ＴｉＯ3 膜２０をＣＶＤ法を用いて
全面に形成する（図８（ｄ））。成膜条件は、昇温時の
酸素分圧１０-3Ｐａ以下，基板の昇温速度５００℃／ｍ
ｉｎ，成膜温度５５０℃，成膜速度１０ｎｍ／ｍｉｎ，
成膜中の酸素分圧０．１Ｐａ及び成膜圧力０．５Ｐａで
ある。なお、基板の構造によってはスパッタ法で成膜し
て良い。Next, the Ru film 19 is formed in an atmosphere containing oxygen.
Is deposited on the entire surface (FIG. 7B), and is processed into a columnar shape as a lower electrode of the capacitor (FIG. 7C). Then, a (Ba, Sr) TiO 3 film 20 is formed on the entire surface by using the CVD method (FIG. 8D). The film forming conditions are as follows: the oxygen partial pressure at the time of temperature rise is 10 −3 Pa or less, and the substrate temperature rise rate is 500 ° C./m
in, deposition temperature 550 ° C., deposition rate 10 nm / min,
The oxygen partial pressure during film formation is 0.1 Pa and the film formation pressure is 0.5 Pa. Note that the film may be formed by a sputtering method depending on the structure of the substrate.
【００２８】次いで、全面に酸素を含む雰囲気中でＲｕ
膜２１を全面に堆積し、キャパシタの上部電極となるよ
う加工する（図８（ｅ））。図９に従来の製造方法と本
実施形態で説明した製造方法で形成されたキャパシタの
リーク電流特性を示す。キャパシタ絶縁膜である（Ｂ
ａ，Ｓｒ）ＴｉＯ3 膜の膜厚は３０ｎｍである。なお、
従来例の成膜条件は酸素分圧１．０Ｐａ、成膜温度６０
０℃、成膜速度３ｎｍ／ｍｉｎである。なお、両者と
も、昇温時の酸素分圧は０．０１Ｐａ、基板の昇温速度
は５００℃／ｍｉｎとした。図から明らかなように、本
発明により、リーク電流は大幅に滅少していることがわ
かる。なお、（Ｂａ，Ｓｒ）ＴｉＯ3 膜のＳｉＯ2 換算
膜厚は、従来例で０．３１ｎｍ、本発明で０．３２ｎｍ
の値が得られた。Next, Ru in an atmosphere containing oxygen on the entire surface.
A film 21 is deposited on the entire surface and processed so as to be an upper electrode of the capacitor (FIG. 8E). FIG. 9 shows the leakage current characteristics of the capacitors formed by the conventional manufacturing method and the manufacturing method described in the present embodiment. Capacitor insulating film (B
The thickness of the (a, Sr) TiO 3 film is 30 nm. In addition,
The film forming conditions of the conventional example are as follows: oxygen partial pressure 1.0 Pa, film forming temperature 60
The temperature is 0 ° C. and the film formation rate is 3 nm / min. In both cases, the oxygen partial pressure during the temperature rise was 0.01 Pa, and the temperature rise rate of the substrate was 500 ° C./min. As is clear from the figure, it can be seen that the leakage current is greatly reduced by the present invention. The SiO 2 equivalent film thickness of the (Ba, Sr) TiO 3 film is 0.31 nm in the conventional example and 0.32 nm in the present invention.
Was obtained.
【００２９】以上説明したように、本実施形態によれ
ば、（Ｂａ，Ｓｒ）ＴｉＯ3 膜を形成する際に、基板の
昇温速度を５００℃／ｍｉｎ、昇温時の酸素分圧を１０
-3Ｐａとすることによって昇温時に下部Ｒｕ電極が酸化
されてモフォロジーが劣化することを防止している。ま
た、成膜中の基板温度を５５０℃とすることで多結晶の
（Ｂａ，Ｓｒ）ＴｉＯ3 膜を得ることができ、高い誘電
率を得ることができる。また、成膜中の酸素分圧を０．
１Ｐａ、成膜速度を１０ｎｍ／ｍｉｎとすることによっ
て成膜時のＲｕ膜の酸化を抑制することができ、良好な
リーク電流特性が得られる。As described above, according to the present embodiment, when forming the (Ba, Sr) TiO 3 film, the temperature of the substrate is raised at a rate of 500 ° C./min, and the oxygen partial pressure during the temperature rise is reduced by 10%.
By setting the pressure to -3 Pa, the lower Ru electrode is prevented from being oxidized at the time of raising the temperature and the morphology is degraded. Further, by setting the substrate temperature during film formation to 550 ° C., a polycrystalline (Ba, Sr) TiO 3 film can be obtained, and a high dielectric constant can be obtained. Further, the oxygen partial pressure during the film formation is set at 0.
By setting the pressure to 1 Pa and the film formation rate to 10 nm / min, oxidation of the Ru film at the time of film formation can be suppressed, and good leak current characteristics can be obtained.
【００３０】また、昇温温度が１００℃／ｍｉｎ以上昇
温時の酸素分圧を１０-2Ｐａ以下にすることでも、昇温
時に下部のＲｕ電極が酸化されてモフォロジーの劣化を
抑えることができる。また、成膜中の酸素分圧を０．５
Ｐａ以下，基板温度が４７０〜６００℃，成膜時間を５
分以内にすることでも同様にリーク電流が少なく、容量
の高いキャパシタを形成することができる。Also, by lowering the oxygen partial pressure when the temperature rise temperature is 100 ° C./min or more to 10 −2 Pa or less, the lower Ru electrode is oxidized at the time of temperature rise and the morphology is prevented from deteriorating. it can. Further, the oxygen partial pressure during film formation is set to 0.5.
Pa or lower, the substrate temperature is 470 to 600 ° C., and the film formation time is 5
Even within minutes, a capacitor having a low leakage current and a high capacity can be formed.
【００３１】［第３実施形態］本実施形態では、下部電
極としてＲｕ膜とＲｕＯ2 膜の積層構造を用い、絶縁膜
としてＳｒＴｉＯ3 膜を用いたキャパシタの形成につい
て説明する。[Third Embodiment] In this embodiment, the formation of a capacitor using a laminated structure of a Ru film and a RuO 2 film as a lower electrode and using a SrTiO 3 film as an insulating film will be described.
【００３２】図１０〜１２は本発明の第２実施形態に係
わるキャパシタの製造工程を示す工程断面図である。先
ず、第２実施形態と同様に、ｐタイプシリコン基板１０
に素子分離領域１１を形成した後、ゲート絶縁膜１２，
ゲート電極（ワード線）１３，ｎ+ 拡散層１４（１４
ａ，１４ｂ）からなるトランジスタを形成する。その
後、全面に第１の層間絶縁膜１５を堆積し、ｎ+ 拡散層
１４ａに接続するビット線１６を形成する。そして、全
面に第２の層間絶縁膜１７を堆積した後、ｎ+ 拡散層１
４ｂに接続するｎ+ 多結晶シリコン１８を形成する（図
１０（ａ））。FIGS. 10 to 12 are sectional views showing the steps of manufacturing a capacitor according to the second embodiment of the present invention. First, as in the second embodiment, the p-type silicon substrate 10
After forming an element isolation region 11 in the gate insulating film 12,
Gate electrode (word line) 13, n + diffusion layer 14 (14
a, 14b). Thereafter, a first interlayer insulating film 15 is deposited on the entire surface, and a bit line 16 connected to the n + diffusion layer 14a is formed. Then, after depositing a second interlayer insulating film 17 on the entire surface, the n + diffusion layer 1 is formed.
An n + polycrystalline silicon 18 connected to 4b is formed (FIG. 10A).
【００３３】次いで、酸素を含む雰囲気中でＲｕ膜１９
を全面に堆積した後、雰囲気中の酸素量を増やして第１
のＲｕＯ2 膜３１を堆積し、Ｒｕ膜１９と第１のＲｕＯ
2 膜３１との積層膜を形成する（図１０（ｂ））。次い
で、Ｒｕ膜１９と第１のＲｕＯ2 膜３１との積層膜を柱
状に加工する（図１０（ｃ））。その後、全面に第２の
ＲｕＯ2 膜３２を堆積する（図１１（ｄ））。さらに、
反応性イオンエッチング法を用いて第２のＲｕＯ2 膜３
２を後退させ、Ｒｕ膜１９の表面がＲｕＯ2 膜３１，３
２で被覆された構造を形成する（図１１（ｅ））。Next, the Ru film 19 is formed in an atmosphere containing oxygen.
Is deposited on the entire surface, and then the amount of oxygen in the atmosphere is
RuO 2 film 31 is deposited, and the Ru film 19 and the first RuO
A laminated film with the two films 31 is formed (FIG. 10B). Next, the laminated film of the Ru film 19 and the first RuO 2 film 31 is processed into a columnar shape (FIG. 10C). Thereafter, a second RuO 2 film 32 is deposited on the entire surface (FIG. 11D). further,
Second RuO 2 film 3 using reactive ion etching
2 is retracted, and the surface of the Ru film 19 becomes RuO 2 films 31 and 3.
2 is formed (FIG. 11E).
【００３４】次いで、全面にＳｒＴｉＯ3 膜３３をＣＶ
Ｄ法で成膜する（図１２（ｆ））。ＳｒＴｉＯ3 膜３３
の成膜条件は、昇温時の酸素分圧１０-2Ｐａ以下，基板
の昇温速度５００℃／ｍｉｎ，成膜温度５００℃，成膜
速度１０ｎｍ／ｍｉｎ，成膜中の酸素分圧１Ｐａ、及び
成膜圧力０．５Ｐａである。なお、構造によってはスパ
ッタ法を用いてＳｒＴｉＯ3 膜３３を成膜しても良い。Next, an SrTiO 3 film 33 is formed on the entire surface by CV.
A film is formed by the method D (FIG. 12F). SrTiO 3 film 33
The film forming conditions are as follows: oxygen partial pressure at the time of temperature rise of 10 −2 Pa or less, substrate temperature rising rate of 500 ° C./min, film forming temperature of 500 ° C., film forming rate of 10 nm / min, oxygen partial pressure of 1 Pa during film formation. , And a film forming pressure of 0.5 Pa. Depending on the structure, the SrTiO 3 film 33 may be formed by using a sputtering method.
【００３５】そして、全面に酸素を含む雰囲気中でＲｕ
膜２１を全面に堆積し、上部電極となるよう加工する
（図１２（ｇ））。本実施形態が第２実施形態と異なる
点は下部電極にＲｕＯ2 ／Ｒｕ積層構造を採用した点と
ＳｒＴｉＯ3 膜をキャパシタ絶縁膜に採用した点であ
る。（Ｂａ，Ｓｒ）ＴｉＯ3 膜よりも結晶化温度の低い
ＳｒＴｉＯ3 膜を用いていることより、成膜温度を４５
０℃まで下げても多結晶ＳｒＴｉＯ3 膜を得ることがで
きる。Then, Ru is applied in an atmosphere containing oxygen entirely.
A film 21 is deposited on the entire surface and processed so as to become an upper electrode (FIG. 12G). This embodiment is different from the second embodiment in that a RuO 2 / Ru stacked structure is used for the lower electrode and an SrTiO 3 film is used for the capacitor insulating film. Since the SrTiO 3 film having a lower crystallization temperature than that of the (Ba, Sr) TiO 3 film is used, the film formation temperature is set to 45.
Even if the temperature is lowered to 0 ° C., a polycrystalline SrTiO 3 film can be obtained.
【００３６】Ｒｕ膜とＲｕＯ2 膜との積層膜を下部電極
として用いた場合も第２実施形態と同様、高容量且つ低
リーク電流であるキャパシタを形成することが可能であ
ることが確認された。It has been confirmed that a capacitor having a high capacitance and a low leakage current can be formed in the same manner as in the second embodiment even when the laminated film of the Ru film and the RuO 2 film is used as the lower electrode. .
【００３７】また、昇温温度が１００℃／ｍｉｎ以上昇
温時の酸素分圧を１０-2Ｐａ以下にすることでも、昇温
時に下部のＲｕ電極が酸化されてモフォロジーの劣化を
抑えることができる。また、成膜中の酸素分圧を０．５
Ｐａ以下，基板温度が４３０〜６００℃，成膜時間を５
分以内にするこでも同様にリーク電流が少なく、容量の
高いキャパシタを形成することができる。Also, by setting the oxygen partial pressure when the temperature rise temperature is 100 ° C./min or more to 10 −2 Pa or less, the lower Ru electrode is oxidized at the time of temperature rise, thereby suppressing the deterioration of morphology. it can. Further, the oxygen partial pressure during film formation is set to 0.5.
Pa or lower, the substrate temperature is 430 to 600 ° C., and the film formation time is 5
Even within minutes, a capacitor having a small leakage current and a high capacitance can be formed.
【００３８】なお、本発明は、上記実施形態に限定され
るものではない。例えば、Ｒｕ系電極に関して説明した
が、ＲｕをＩｒに置き換えても同様に本発明を実施する
ことができる。この場合はＲｕ電極の代わりにＩｒ電
極、表面がＲｕＯ2 に被覆されたＲｕ電極の代わりに、
表面がＩｒＯ2 に被覆されたＩｒ電極にすれば良い。ま
た、容易に類推できるように、Ｒｕ電極表面にＲｕＯ2
が被覆されている場合やＩｒ電極表面にＲｕＯ2 が被覆
されている場合にも同様に本発明を実施することができ
る。その他、本発明は、その要旨を逸脱しない範囲で、
種々変形して実施することが可能である。The present invention is not limited to the above embodiment. For example, although the description has been given with respect to the Ru-based electrode, the present invention can be similarly implemented by replacing Ru with Ir. In this case, instead of the Ru electrode, instead of the Ir electrode, and the Ru electrode whose surface is coated with RuO 2 ,
Surface may be the Ir electrode covered with IrO 2. Also, as can be easily analogized, RuO 2 is applied to the Ru electrode surface.
The present invention can be carried out in the same manner when the surface is coated or when the surface of the Ir electrode is coated with RuO 2 . In addition, the present invention does not depart from the gist thereof,
Various modifications are possible.
【００３９】[0039]
【発明の効果】以上説明したように本発明によれば、表
面粗さが少なくなり、誘電率の高い膜が得られるプロセ
ス条件でキャパシタの絶縁膜を形成することによって、
リーク電流が低く、容量が大きいキャパシタを形成する
ことができる。As described above, according to the present invention, by forming an insulating film of a capacitor under process conditions in which a film having a low surface roughness and a high dielectric constant can be obtained,
A capacitor with low leakage current and large capacitance can be formed.
【図１】Ｒｕ膜の表面粗さの基板温度依存性を示す特性
図。FIG. 1 is a characteristic diagram showing the substrate temperature dependence of the surface roughness of a Ru film.
【図２】比誘電率の成膜温度依存性を示す特性図。FIG. 2 is a characteristic diagram showing the dependency of the relative dielectric constant on the film formation temperature.
【図３】表面粗さの成膜時の酸素分圧依存性を示す特性
図。FIG. 3 is a characteristic diagram showing the oxygen partial pressure dependence of surface roughness during film formation.
【図４】表面粗さの成膜速度依存性を示す特性図。FIG. 4 is a characteristic diagram showing the dependency of the surface roughness on the deposition rate.
【図５】表面粗さの基板昇温時の酸素分圧依存性を示す
特性図。FIG. 5 is a characteristic diagram showing the dependency of the surface roughness on the oxygen partial pressure when the substrate is heated.
【図６】表面粗さの基板の昇温速度依存性を示す特性
図。FIG. 6 is a characteristic diagram showing the dependency of surface roughness on the rate of temperature rise of a substrate.
【図７】第２実施形態に係わるキャパシタの製造工程を
示す工程断面図。FIG. 7 is a process cross-sectional view showing the process of manufacturing the capacitor according to the second embodiment.
【図８】第２実施形態に係わるキャパシタの製造工程を
示す工程断面図。FIG. 8 is a process cross-sectional view showing a process of manufacturing the capacitor according to the second embodiment.
【図９】キャパシタのリーク電流特性を示す特性図。FIG. 9 is a characteristic diagram showing leakage current characteristics of a capacitor.
【図１０】第３実施形態に係わるキャパシタの製造工程
を示す工程断面図。FIG. 10 is a process cross-sectional view showing the process of manufacturing the capacitor according to the third embodiment.
【図１１】第３実施形態に係わるキャパシタの製造工程
を示す工程断面図。FIG. 11 is a process cross-sectional view showing the process of manufacturing the capacitor according to the third embodiment.
【図１２】第３実施形態に係わるキャパシタの製造工程
を示す工程断面図。FIG. 12 is a process cross-sectional view showing the process of manufacturing the capacitor according to the third embodiment.
【図１３】従来の問題点を説明する図。FIG. 13 is a diagram illustrating a conventional problem.
【図１４】従来の問題点を説明する図。FIG. 14 is a diagram illustrating a conventional problem.
１０…ｐタイプシリコン基板 １１…素子分離領域 １２…ゲート絶縁膜 １３…ゲート電極 １４…ｎ+ 拡散層 １５…第１の層間絶縁膜 １６…ビット線 １７…第２の層間絶縁膜 １８…ｎ+ 多結晶シリコン １９…Ｒｕ膜 ２０…（Ｂａ，Ｓｒ）ＴｉＯ3 膜 ２１…Ｒｕ膜 ３１…第１のＲｕＯ2 膜 ３２…第２のＲｕＯ2 膜 ３３…ＳｒＴｉＯ3 膜Reference Signs List 10 p-type silicon substrate 11 element isolation region 12 gate insulating film 13 gate electrode 14 n + diffusion layer 15 first interlayer insulating film 16 bit line 17 second interlayer insulating film 18 n + polysilicon 19 ... Ru film 20 ... (Ba, Sr) TiO 3 film 21 ... Ru film 31 ... first RuO 2 film 32 ... second RuO 2 film 33 ... SrTiO 3 film
Claims (6)
或いはＩｒとＩｒＯ2 との積層構造からなるキャパシタ
の下部電極上に、該キャパシタの絶縁膜としてペロブス
カイト構造の絶縁体を形成する半導体装置の製造方法で
あって、 前記絶縁体を結晶化温度以上６００℃未満の基板温度で
形成することを特徴とする半導体装置の製造方法。1. A semiconductor in which an insulator having a perovskite structure is formed as an insulating film of a capacitor on a lower electrode of a capacitor having a stacked structure of Ru, Ir, Ru and RuO 2 or a stacked structure of Ir and IrO 2. A method for manufacturing a semiconductor device, comprising: forming the insulator at a substrate temperature equal to or higher than a crystallization temperature and lower than 600 ° C.
膜を形成する場合、 前記基板温度が４７０℃以上６００℃未満であることを
特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 2, wherein (Ba, Sr) TiO 3 is used as the insulator.
2. The method according to claim 1, wherein when forming a film, the substrate temperature is 470 ° C. or higher and lower than 600 ° C.
る場合、 前記基板温度が４３０℃以上６００℃未満であることを
特徴とする請求項１記載の半導体装置の製造方法。3. The method according to claim 1, wherein when forming an SrTiO 3 film as said insulator, said substrate temperature is 430 ° C. or more and less than 600 ° C.
ａ以下であることを特徴とする請求項１記載の半導体装
置の製造方法。4. The method according to claim 1, wherein the oxygen partial pressure during the formation of the insulator is 0.5 P
2. The method according to claim 1, wherein a is equal to or less than a.
とを特徴とする請求項１に記載の半導体装置の製造方
法。5. The method for manufacturing a semiconductor device according to claim 1, wherein a film forming time of said insulator is within 5 minutes.
１００℃／ｍｉｎ以上であることを特徴とする請求項１
記載の半導体装置の製造方法。6. The method according to claim 1, wherein the heating rate is 100 ° C./min or more when heating to the substrate temperature.
The manufacturing method of the semiconductor device described in the above.
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|---|---|---|---|
| JP9149164A JPH10340994A (en) | 1997-06-06 | 1997-06-06 | Manufacture of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9149164A JPH10340994A (en) | 1997-06-06 | 1997-06-06 | Manufacture of semiconductor device |
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|---|---|
| JPH10340994A true JPH10340994A (en) | 1998-12-22 |
Family
ID=15469204
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056612A1 (en) * | 2001-12-28 | 2003-07-10 | Genitech Co., Ltd. | Method of forming copper interconnections for semiconductor integrated circuits on a substrate |
| US8927403B2 (en) | 2005-03-15 | 2015-01-06 | Asm International N.V. | Selective deposition of noble metal thin films |
| US9129897B2 (en) | 2008-12-19 | 2015-09-08 | Asm International N.V. | Metal silicide, metal germanide, methods for making the same |
| US9379011B2 (en) | 2008-12-19 | 2016-06-28 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
| US9587307B2 (en) | 2005-03-15 | 2017-03-07 | Asm International N.V. | Enhanced deposition of noble metals |
| US9607842B1 (en) | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
-
1997
- 1997-06-06 JP JP9149164A patent/JPH10340994A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056612A1 (en) * | 2001-12-28 | 2003-07-10 | Genitech Co., Ltd. | Method of forming copper interconnections for semiconductor integrated circuits on a substrate |
| US8927403B2 (en) | 2005-03-15 | 2015-01-06 | Asm International N.V. | Selective deposition of noble metal thin films |
| US9469899B2 (en) | 2005-03-15 | 2016-10-18 | Asm International N.V. | Selective deposition of noble metal thin films |
| US9587307B2 (en) | 2005-03-15 | 2017-03-07 | Asm International N.V. | Enhanced deposition of noble metals |
| US9129897B2 (en) | 2008-12-19 | 2015-09-08 | Asm International N.V. | Metal silicide, metal germanide, methods for making the same |
| US9379011B2 (en) | 2008-12-19 | 2016-06-28 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
| US9634106B2 (en) | 2008-12-19 | 2017-04-25 | Asm International N.V. | Doped metal germanide and methods for making the same |
| US10553440B2 (en) | 2008-12-19 | 2020-02-04 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
| US10043880B2 (en) | 2011-04-22 | 2018-08-07 | Asm International N.V. | Metal silicide, metal germanide, methods for making the same |
| US9607842B1 (en) | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
| US10199234B2 (en) | 2015-10-02 | 2019-02-05 | Asm Ip Holding B.V. | Methods of forming metal silicides |
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