JPH10340929A - Wiring board for mounting electronic part - Google Patents
Wiring board for mounting electronic partInfo
- Publication number
- JPH10340929A JPH10340929A JP10046382A JP4638298A JPH10340929A JP H10340929 A JPH10340929 A JP H10340929A JP 10046382 A JP10046382 A JP 10046382A JP 4638298 A JP4638298 A JP 4638298A JP H10340929 A JPH10340929 A JP H10340929A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- hole
- bump
- electrode pad
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品を搭載す
るための電子部品搭載用配線基板であって、特にバンプ
を形成する電極パッドを有する電子部品搭載用配線基板
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting electronic components, and more particularly to a wiring board for mounting electronic components having electrode pads for forming bumps.
【０００２】[0002]
【従来の技術】図５に基づいて従来の技術を説明する。
従来技術の電子部品搭載用の従来の配線基板３１は、こ
の従来の配線基板３１の上部表面に半導体回路部品、抵
抗、コンデンサあるいはモジュール部品などの電子部品
４０をリフローはんだ付けをして表面面付実装するか、
または電子部品４０と電子部品搭載面にある上面外層導
体３３のボンディング・ランドにボンディング・ワイヤ
４１で接続してワイヤ・ボンディング実装する。この電
子部品搭載面にある上面外層導体３３とバンプ形成側の
下面外層導体３５とは、貫通孔３２のスルーホールめっ
き層３４で電気的に導通されている。この下面外層導体
３５の所定箇所の２次元の格子上交点に多数の平面的な
電極パッド３６が設定配置されている。この電子部品４
０を搭載する従来の配線基板３１の外部へ接続するため
の端子である平面的な電極パッド３６の表面に突出接点
（以下、バンプと記す）を形成する。代表的なバンプ４
５として、球形状のはんだボール４５Ａが一般的に使用
されているがその他に、たまご形状、半球形状、長円球
形状などのバンプ４５も使用されている。前記バンプ４
５を平面的な電極パッド３６に取り付ける場合、電極パ
ッド３６に接するバンプ４５の先端面が球面形状となっ
ているため位置決めが非常に難しく問題となっている。2. Description of the Related Art A conventional technique will be described with reference to FIG.
A conventional wiring board 31 for mounting electronic parts according to the prior art is provided with an electronic component 40 such as a semiconductor circuit component, a resistor, a capacitor or a module component on the upper surface of the conventional wiring substrate 31 by reflow soldering. Implement or
Alternatively, the electronic component 40 is connected to the bonding lands of the upper outer layer conductor 33 on the electronic component mounting surface by bonding wires 41 and mounted by wire bonding. The upper surface outer layer conductor 33 on the electronic component mounting surface and the lower surface outer layer conductor 35 on the bump formation side are electrically connected by a through-hole plating layer 34 of the through hole 32. A large number of planar electrode pads 36 are set and arranged at predetermined two-dimensional grid intersections of the lower surface outer layer conductor 35. This electronic component 4
A projecting contact (hereinafter, referred to as a bump) is formed on the surface of a planar electrode pad 36, which is a terminal for connecting to the outside of the conventional wiring board 31 on which the 0 is mounted. Representative bump 4
5, a solder ball 45A having a spherical shape is generally used. In addition, a bump 45 having an egg shape, a hemispherical shape, an oval shape or the like is also used. The bump 4
When the electrode 5 is attached to the planar electrode pad 36, positioning is very difficult because the tip surface of the bump 45 in contact with the electrode pad 36 has a spherical shape.
【０００３】従来は、ＩＣフラットパッケージ等の高密
度電子部品や電子部品を搭載したモジュール配線基板な
どの、いわゆる電子部品４０を搭載した従来の配線基板
３１の外部への接続端子と親配線基板（マザー・ボー
ド）２２の接続用ランド２６との接続には、導電性ペー
スト、例えばクリームはんだ２８を用いたリフローはん
だ付けが利用されていたが、近年、ＩＣフラットパッケ
ージ等の高密度化、小型化により接続端子数の増加、接
続端子間いわゆる端子ピッチ間隔が狭くなり、電子部品
４０のリード端子径が細く、かつ変形しやすくなって従
来のはんだ付け技術の限界に直面し、はんだ付け不良率
が高くなっていた。Conventionally, connection terminals to the outside of a conventional wiring board 31 on which a so-called electronic component 40 is mounted, such as a high-density electronic component such as an IC flat package and a module wiring board on which the electronic component is mounted, and a parent wiring board ( Reflow soldering using a conductive paste, for example, cream solder 28, has been used to connect the mother board 22 to the connection lands 26. In recent years, however, the density and size of IC flat packages and the like have been reduced. As a result, the number of connection terminals increases, so-called terminal pitch interval between the connection terminals becomes narrower, the lead terminal diameter of the electronic component 40 becomes thinner and easily deformed, and the limit of the conventional soldering technology is faced. Was higher.
【０００４】そこで注目を集めている接続技術として、
電子部品４０を搭載した従来の配線基板３１の下面に外
部へ接続するための端子として多数の平面的な電極パッ
ド３６に、はんだ等により形成された球形状のバンプ、
例えば、はんだボール４５Ａを２次元に配置しておい
て、このはんだボール４５Ａのバンプと親配線基板２２
の接続用ランド２６にクリームはんだ２８を塗布した接
続端子群とを突き合わせてから、リフローはんだ付けに
より平面的な面付実装を行なうことが多くなっている。
球形状バンプを２次元に配置する方式はＢＧＡ（ball・
grid・array）パッケージ方式と呼び電子部品の高密度
化、小型化および、はんだ付け不良率の低減による品質
の向上が望める。[0004] As a connection technology that has attracted attention,
A plurality of planar electrode pads 36 as terminals for external connection to the lower surface of the conventional wiring board 31 on which the electronic component 40 is mounted, spherical bumps formed by solder or the like,
For example, the solder balls 45A are two-dimensionally arranged, and the bumps of the solder balls 45A and the parent wiring board 22 are arranged.
In many cases, a flat surface mounting is performed by reflow soldering after abutting a connection terminal group coated with a cream solder 28 on the connection land 26.
The method of arranging spherical bumps in two dimensions is BGA (ball
It is called a “grid / array” package system, and it is expected that the quality of electronic components will be improved by increasing the density and miniaturizing them, and by reducing the defective soldering rate.
【０００５】通常、ＩＣフラットパッケージ等の高密度
化、小型化された電子部品４０を従来の配線基板３１に
実装する際、はんだ付け用のフラックス、はんだがスル
ーホールめっきの施こされている貫通孔３２を通じて電
子部品４０の搭載面に流出したり、また搭載した電子部
品４０やボンディング・ワイヤ４１をモールド樹脂で被
覆して保護する際にバンプ形成側へのモールド樹脂の流
出を防止するため、貫通孔３２に充填物３９を充填しな
ければならい。その後、外層導体表面の必要な接続ラン
ドや電極パッド３６以外にはソルダーレジスト１７を施
すことが一般的である。[0005] Usually, when mounting a high-density and miniaturized electronic component 40 such as an IC flat package on a conventional wiring board 31, a flux for soldering and a through-hole plated with through-hole plating are used. In order to prevent the resin from flowing to the mounting surface of the electronic component 40 through the hole 32 and to prevent the resin from flowing toward the bump formation side when the mounted electronic component 40 and the bonding wire 41 are covered with the mold resin and protected. The through holes 32 must be filled with the filler 39. After that, it is common to apply a solder resist 17 to portions other than necessary connection lands and electrode pads 36 on the outer conductor surface.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら従来のＢ
ＧＡパッケージ方式の一体化された電子部品搭載用配線
基板では球形状のバンプ４５を２次元の格子上交点に平
面的に設定された電極パッド３６に取り付ける場合、電
極パッド３６に接するバンプ４５の先端面が球面形状と
なっているため位置決めが非常に難しくなっている。さ
らに、球形状のバンプ４５を従来の配線基板３１の所定
箇所に２次元に配置されている平面的な電極パッド３６
に正確に位置決めをし、固定する必要があるだけでな
く、バンプ４５の先端面の高さのバラツキやバンプを形
成するはんだの量の多少で、親配線基板２２の接続用ラ
ンド２６へリフローはんだ付けする際に隣接バンプ４５
または接続用ランド２６とショートしたり、従来の配線
基板３１に形成されているバンプ４５と接続用ランド２
６のクリームはんだ２８との接続不良が生じたり、球形
状のバンプ４５を用いた平面的な面付接続による接続技
術は接続信頼性の確保が課題となっている。また、電子
部品４０を従来の配線基板３１に実装する際、はんだ付
け用のフラックス、はんだが貫通孔３２を通じて電子部
品４０の搭載面に流出したり、搭載した電子部品４０や
ボンディング・ワイヤ４１をモールド樹脂で被覆して保
護する際にバンプ４５形成側へのモールド樹脂の流出を
防止するため、貫通孔３２に充填物３９を充填しなけれ
ばならず、生産効率の低下となっている。However, the conventional B
In the case of mounting a spherical bump 45 on an electrode pad 36 which is set two-dimensionally at an intersection on a two-dimensional grid in the integrated electronic component mounting wiring board of the GA package system, the tip of the bump 45 in contact with the electrode pad 36 Positioning is very difficult because the surface is spherical. Further, the spherical bumps 45 are formed on the planar electrode pads 36 two-dimensionally arranged at predetermined positions on the conventional wiring board 31.
In addition to the need for accurate positioning and fixing, the reflow soldering to the connection lands 26 of the parent wiring board 22 depends on the height of the bumps 45 and the amount of solder forming the bumps. When attaching, adjacent bump 45
Alternatively, the connection land 26 may be short-circuited or the bump 45 formed on the conventional wiring board 31 may be connected to the connection land 2.
In connection technology with the solder paste 28 of No. 6 or the connection technology by planar surface connection using the spherical bump 45, securing the connection reliability is an issue. When the electronic component 40 is mounted on the conventional wiring board 31, the flux for soldering or the solder flows out to the mounting surface of the electronic component 40 through the through hole 32, or the mounted electronic component 40 or the bonding wire 41 is removed. In order to prevent the mold resin from flowing out to the side where the bumps 45 are formed when covering and protecting with the mold resin, the through hole 32 must be filled with the filling material 39, which lowers the production efficiency.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
本発明においては、配線基板の外部へ接続する端子にバ
ンプを形成する配線基板に、絶縁性基材と、絶縁性基材
を貫通する穴と、絶縁性基材を貫通する穴の一方の端面
を塞ぐ表面外層導体とからなる非貫通穴である凹形状の
電極パッドを有する電子部品搭載用配線基板とする。上
記の絶縁性基材を貫通する穴の一方の端面を塞ぐ表面外
層導体側には、通常は電子部品を搭載する。また、上記
の電子部品搭載用配線基板は、片面配線基板，両面配線
基板，多層配線基板のいずれでも非貫通穴である凹形状
の電極パッドを形成することにより目的を達成すること
ができる。In order to solve the above-mentioned problems, according to the present invention, an insulating base material is formed on a wiring board for forming a bump on a terminal connected to the outside of the wiring board. An electronic component mounting wiring board having a concave electrode pad which is a non-through hole made of a hole and a surface outer layer conductor closing one end face of the hole penetrating the insulating base material. Usually, an electronic component is mounted on the surface outer layer conductor side that closes one end face of the hole penetrating the insulating base material. The above-mentioned electronic component mounting wiring board can achieve the object by forming a concave electrode pad that is a non-through hole in any of a single-sided wiring board, a double-sided wiring board, and a multilayer wiring board.
【０００８】両面配線基板，多層配線基板では、閉孔し
ている非貫通穴内にメッキ法や蒸着法などで導体層を形
成し、電子部品搭載面にある上面外層導体とバンプ形成
側にある下面外層導体とを、非貫通穴内の導体層で電気
的に導通させる非貫通導通穴とする。つまり、電子部品
を搭載するための配線基板に外部へ接続する端子にバン
プを形成する配線基板において、絶縁性基材と、絶縁性
基材を貫通する穴と、絶縁性基材を貫通する穴の一方の
端面を塞ぐ表面外層導体と、閉孔している非貫通穴内の
導体層とからなる非貫通導通穴である凹形状の電極パッ
ドを有する電子部品搭載用配線基板とする。電子部品を
搭載するための配線基板で、バンプ形成側にある下面外
層導体に形成されている電極パッドを、配線基板の基板
表面から絶縁性基材側内部に、その表面中央部を凹形状
に陥没して形成し、球面形状のバンプを凹形状の電極パ
ッド内部にはめ込むことにより、正しい電極パッド位置
に容易に位置決めをすることができる。 また、凹形状
の電極パッド部は、電子部品搭載面の表面外層導体とバ
ンプ形成側の表面外層導体とが非貫通穴内の導体層で導
通され、穴の一方の端面を表面外層導体で塞ぐため従来
の貫通スルーホール穴の充填物による穴埋めを省略する
ことが可能となる。In a double-sided wiring board and a multilayer wiring board, a conductor layer is formed in a closed non-through hole by a plating method or a vapor deposition method, and an upper outer conductor on an electronic component mounting surface and a lower surface on a bump forming side are formed. The outer layer conductor is a non-through conduction hole that is electrically connected to the conductor layer in the non-through hole. That is, in a wiring board in which bumps are formed on terminals connected to the outside on a wiring board for mounting electronic components, an insulating base material, a hole penetrating the insulating base material, and a hole penetrating the insulating base material. An electronic component mounting wiring board having a concave electrode pad which is a non-through conductive hole composed of a surface outer layer conductor closing one end face of the above and a conductor layer in the closed non-through hole. On the wiring board for mounting electronic components, electrode pads formed on the lower surface outer layer conductor on the bump formation side are placed from the substrate surface of the wiring board to the inside of the insulating base material side, and the center part of the surface is concave. By being formed in a depressed state and by fitting the spherical bump into the concave electrode pad, it is possible to easily position the electrode pad at the correct electrode pad position. In addition, the concave-shaped electrode pad portion is configured so that the outer surface layer conductor on the electronic component mounting surface and the outer surface layer conductor on the bump forming side are electrically conducted through the conductor layer in the non-through hole, and one end face of the hole is closed with the outer surface layer conductor. It is possible to omit the conventional filling of the through hole with the filling material.
【０００９】配線基板の基板表面から絶縁性基材側内部
に、その表面中央部を凹形状に陥没して形成し、球面形
状のバンプを凹形状の電極パッド内部にはめ込み、且つ
配線基板の外部へ接続するための端子となるバンプ形成
側にある下面外層導体に形成される電極パッドとして開
孔している穴端面の一部もしくは全周に接する表面外層
導体を設ける。つまり、電子部品を搭載するための配線
基板に外部へ接続するバンプを形成する配線基板におい
て、絶縁性基材と、絶縁性基材を貫通する穴と、絶縁性
基材を貫通する穴の一方の端面を塞ぐ表面外層導体と、
閉孔している非貫通穴内の導体層と、絶縁性基材を貫通
する穴の他方の開孔している穴端面の一部もしくは全周
に接して設けられた外層導体とからなる凹形状の電極パ
ッドを有する電子部品搭載用配線基板とする。A central portion of the surface of the wiring substrate is formed in a concave shape from the substrate surface to the inside of the insulating substrate side, a spherical bump is fitted into the concave electrode pad, and an external portion of the wiring substrate is formed. A surface outer layer conductor is provided as an electrode pad formed on the lower surface outer layer conductor on the bump forming side serving as a terminal for connecting to a part or the entire periphery of a hole end face opened. In other words, in a wiring board on which a bump to be connected to the outside is formed on a wiring board for mounting electronic components, one of an insulating base material, a hole passing through the insulating base material, and a hole passing through the insulating base material. A surface outer layer conductor closing the end face of
A concave shape comprising a conductor layer in a closed non-through hole and an outer conductor provided in contact with a part or the entire periphery of the other open hole end face of the hole penetrating the insulating base material. Electronic component mounting wiring board having the above electrode pads.
【００１０】多層配線基板では、バンプを形成する側の
表面外層導体と、内層導体との間に形成するブラインド
スルーホール穴を、バンプを形成する非貫通穴である凹
形状の電極パッドとして使用する電子部品搭載用配線基
板とすることもできる。In a multilayer wiring board, a blind through-hole formed between an outer conductor on the surface on which a bump is formed and an inner conductor is used as a concave electrode pad which is a non-through hole for forming a bump. It can also be a wiring board for mounting electronic components.
【００１１】さらに凹形状の電極パッドの深さを、この
凹設穴に挿入する球形状バンプの外径よりも小さくして
配線基板のバンプを形成する側の基板表面からバンプの
一部分が突出するようにし、この球面形状のバンプを挿
入し形成する深さを調節することにより２次元に配置さ
れる多数のバンプの突出する先端面の高さレベルを平坦
化でき、親配線基板の接続用ランドとの間隔が一定とな
り、リフローはんだ付け作業およびバンプの面接続によ
る位置決めと品質が安定化する。つまり、バンプを形成
する非貫通穴である凹形状の電極パッドにおいて、非貫
通穴の深さ（Ｓ）が上記バンプの外径（Ｄ）よりも若干
小さく形成する前記のいずれかに記載の電子部品搭載用
配線基板とする。Further, the depth of the concave electrode pad is made smaller than the outer diameter of the spherical bump inserted into the concave hole, and a part of the bump protrudes from the surface of the wiring substrate on which the bump is formed. By adjusting the depth at which the spherical bumps are inserted and formed, the height level of the protruding tip surfaces of the two-dimensionally arranged bumps can be flattened, and the connection lands of the parent wiring board can be flattened. , And the positioning and quality by the reflow soldering operation and the surface connection of the bumps are stabilized. That is, in the concave electrode pad which is a non-through hole for forming a bump, the depth (S) of the non-through hole is formed to be slightly smaller than the outer diameter (D) of the bump. It is a component mounting wiring board.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。まず、図１の本発明の電子部品搭載
状態の配線基板断面図において、抵抗、コンデンサ、半
導体回路部品、ＩＣフラットパッケージあるいはモジュ
ール部品などの電子部品４０を配線基板１０の上面に形
成された電子部品搭載面の表面外層導体３の所定箇所に
ボンディング・ワイヤ４１でワイヤ・ボンディング実装
をして接続した状態を示している。この電子部品４０の
各電極端子と、配線基板１０の所定箇所に形成されてい
る各接続ランドとの接続はワイヤ・ボンディングだけに
限らず導電性ペ−スト８であるクリームはんだによる表
面面付実装や、あるいは溶接実装などでもよい。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, in the cross-sectional view of the wiring board of the present invention shown in FIG. 1, an electronic component 40 such as a resistor, a capacitor, a semiconductor circuit component, an IC flat package or a module component is formed on the upper surface of the wiring board 10. The figure shows a state where wire bonding and mounting are performed by bonding wires 41 at predetermined positions on the outer conductor 3 on the mounting surface. The connection between each electrode terminal of the electronic component 40 and each connection land formed at a predetermined position on the wiring board 10 is not limited to wire bonding, but is also performed by a surface paste mounting using a conductive paste 8 such as cream solder. Alternatively, welding mounting may be used.
【００１３】電子部品搭載用の配線基板１０はガラスエ
ポキシ基材、フェノール基材、合成樹脂基材、テフロン
含有基材、ポリイミド樹脂基材、ＢＴレジン（ビスマレ
ィミド−トリアジン樹脂）基材、変性ＢＴレジン基材ま
たはセラミック等の絶縁性基材１であり、絶縁性基材１
の所定箇所にバンプを形成する側からレーザー加工を
し、電子部品搭載面の表面外層導体３に達する絶縁性基
材１を貫通する穴７を設ける。次に、めっきを施こし非
貫通穴内の導体層４と、絶縁性基材１の両方の表面の所
定箇所には所定の電子部品搭載面の表面外層導体３と、
バンプ形成側の表面外層体５とを印刷法や写真法により
形成し、電子部品搭載面の表面外層導体３とバンプ形成
側の表面外層導体５とを非貫通穴内の導体層４で電気的
に導通させる。上記に示すように配線基板１０の下部に
あるバンプ形成側の基板表面５Ａから絶縁性基材１の内
部に、その箇所の表面中央部がへこんだ非貫通穴となる
凹形状の電極パッド６を陥没して形成し、立体的（３次
元）な球面形状のバンプ４５取付用電極パッドとする。The wiring board 10 for mounting electronic parts is a glass epoxy base, a phenol base, a synthetic resin base, a Teflon-containing base, a polyimide resin base, a BT resin (bismaleimide-triazine resin) base, a modified BT resin. A base material or an insulating base material 1 such as a ceramic;
A laser processing is performed from a side where a bump is formed at a predetermined position, and a hole 7 penetrating the insulating base material 1 reaching the outer surface conductor 3 on the electronic component mounting surface is provided. Next, plating is performed on the conductor layer 4 in the non-through hole, and on a predetermined portion on both surfaces of the insulating base material 1, a surface outer layer conductor 3 on a predetermined electronic component mounting surface;
The outer surface layer body 5 on the bump formation side is formed by a printing method or a photographic method, and the outer surface layer conductor 3 on the electronic component mounting surface and the outer surface layer conductor 5 on the bump formation side are electrically connected by the conductor layer 4 in the non-through hole. Make it conductive. As described above, from the substrate surface 5A on the bump formation side below the wiring substrate 10 to the inside of the insulating base material 1, the concave electrode pad 6 which becomes a non-through hole in which the center of the surface is dented is formed. An electrode pad for mounting the bump 45 having a three-dimensional (three-dimensional) spherical shape formed by being depressed.
【００１４】また、配線基板１０の外部へ接続するため
の端子となるバンプ形成側にある表面外層導体５に形成
される凹形状の電極パッド６として配線基板下面にある
開孔している穴端面の一部もしくは全周に接して表面外
層導体を設ける。しかし、高密度のパタ−ン設計をする
場合は、バンプ形成側にある表面外層導体５にはバンプ
形成用のランドを設けず、凹形状の非貫通穴の内壁のみ
に非貫通穴内の導体層４を形成する、いわゆるランドレ
ス形状とすることもできる。つまり、電子部品を搭載す
るための配線基板に外部へ接続する端子にバンプを形成
する配線基板１０において絶縁性基材１と、絶縁性基材
を貫通する穴７と、絶縁性基材を貫通する穴７の一方の
端面を塞ぐ電子部品搭載面の表面外層導体３と、閉孔し
ている非貫通穴内の導体層４とからなる非貫通導通穴で
ある凹形状の電極パッド６を有する電子部品搭載用配線
基板とする。また、この配線基板１０には貫通孔は設け
ず非貫通穴として、電子部品４０を配線基板１０に実装
する際、はんだ付け用のフラックス、はんだが貫通孔を
通じて電子部品４０の搭載面に流出したり、搭載した電
子部品４０やボンディング・ワイヤ４１をモールド樹脂
で被覆して保護する際にバンプ４５形成側へのモールド
樹脂が流出することを防止する。A hole end face formed on the lower surface of the wiring board as a concave electrode pad 6 formed on a surface outer layer conductor 5 on the bump forming side serving as a terminal for connection to the outside of the wiring board 10. A surface outer layer conductor is provided in contact with a part or the entire periphery of the conductor. However, when a high-density pattern is designed, no bump-forming land is provided on the surface outer layer conductor 5 on the bump formation side, and only the inner wall of the concave non-through hole has a conductor layer in the non-through hole. 4, so-called landless shape. That is, in the wiring board 10 for forming a bump on a terminal connected to the outside on a wiring board for mounting an electronic component, the insulating base 1, the hole 7 penetrating the insulating base, and the insulating base 1 An electronic device having a concave electrode pad 6 which is a non-through conductive hole composed of a surface outer layer conductor 3 on an electronic component mounting surface for closing one end face of a hole 7 to be formed and a conductor layer 4 in a closed non-through hole. It is a component mounting wiring board. In addition, when the electronic component 40 is mounted on the wiring board 10, when the electronic component 40 is mounted on the wiring substrate 10, the soldering flux and the solder flow out to the mounting surface of the electronic component 40 through the through-hole. In addition, when the mounted electronic component 40 and the bonding wire 41 are covered with the mold resin and protected, the mold resin is prevented from flowing out to the bump 45 forming side.
【００１５】銅張り積層板を用いる場合は、バンプを形
成する側の表面外層導体５を写真法や印刷法でエッチン
グレジスト膜を形成し、次にエッチング処理をして中央
部が所定の穴径となる非導体部を形成する。次に、前記
非導体部をレーザー加工用のマスクとして、バンプ形成
側からレーザー加工をして絶縁性基材１を穿孔し、電子
部品搭載面の表面外層導体３に達する絶縁性基材を貫通
する穴７を設けた後、無電解めっき、電解めっきを施こ
し非貫通穴内の導体層４を形成する。その次に、絶縁性
基材１の表面の所定箇所には所定の電子部品搭載面の表
面外層導体３と、バンプ形成側の表面外層体５とを印刷
法や写真法により形成する。電子部品搭載面の表面外層
導体３とバンプ形成側の表面外層導体５とをこの非貫通
穴内の導体層４で従来の貫通スルーホール穴と同様に両
面の表面外層導体が電気的に接続し導通をはかるように
する。なお、すべての導体回路を形成してから所定のソ
ルダーレジスト１７を施す。If a copper-clad laminate is used, an etching resist film is formed on the surface outer layer conductor 5 on the side where the bumps are to be formed by a photographic method or a printing method, and then an etching process is performed so that the center portion has a predetermined hole diameter. Is formed. Next, using the non-conductive portion as a mask for laser processing, laser processing is performed from the bump forming side to pierce the insulating base material 1 and penetrate the insulating base material reaching the outer conductor 3 on the electronic component mounting surface. After the holes 7 are formed, electroless plating and electrolytic plating are performed to form the conductor layer 4 in the non-through holes. Next, a surface outer layer conductor 3 on a predetermined electronic component mounting surface and a surface outer layer body 5 on the bump forming side are formed at predetermined positions on the surface of the insulating base material 1 by a printing method or a photographic method. The surface outer layer conductor 3 on the electronic component mounting surface and the surface outer layer conductor 5 on the bump formation side are electrically connected to each other by the conductor layer 4 in the non-through hole in the same manner as the conventional through-hole hole. To be measured. After all the conductor circuits are formed, a predetermined solder resist 17 is applied.
【００１６】次に、配線基板１０に形成されている凹形
状の電極パッド６の内部に、はんだ付用フラックスまた
は導電性ペースト８を塗布あるいは充填し、そこに球形
状のバンプ４５をはめ込んだ状態で接着して仮固定をす
る。導電性ペースト８としては、銀ペースト、銅ペース
ト、はんだペースト、カーボンペースト、銀−銅の混合
ペースト、Ｓｎ−Ａｇ−Ｃｕ系、Ｓｎ−Ａｇ−Ｂｉ系の
ペーストなどがあるが一般的にはクリームはんだが使用
されている。なお、バンプ４５の材質として金、銅、黄
銅、軟銅、はんだ、鋼球に金属めっきをしたもの、樹脂
に金属めっきをしたものなどが用いられる。Next, a soldering flux or a conductive paste 8 is applied or filled into the concave electrode pads 6 formed on the wiring board 10, and spherical bumps 45 are fitted therein. And temporarily fix it. Examples of the conductive paste 8 include a silver paste, a copper paste, a solder paste, a carbon paste, a silver-copper mixed paste, a Sn-Ag-Cu-based paste, and a Sn-Ag-Bi-based paste. Solder is used. In addition, as a material of the bump 45, gold, copper, brass, soft copper, solder, a steel ball plated with metal, a resin plated with metal, or the like is used.
【００１７】本発明のバンプ４５形成用の電極パッド
は、その表面中央部が凹形状に陥没しているため球形状
のバンプ４５（はんだボール４５Ａ）を、その内部には
め込むことは簡単にでき、また凹形状の電極パッド６は
２次元の格子交点の正しい電極パッド位置に設定されて
いるので容易に位置決めをすることができる。さらに、
凹形状の電極パッド６の非貫通穴の内径は挿入する球形
状のバンプ４５の外径Ｄより若干（０．０５〜０．２０
ｍｍ）大きくし、凹形状の電極パッド６の内径とバンプ
４５の外径Ｄとの間隙を少なくして平面的な位置決め精
度を高くする。In the electrode pad for forming the bump 45 of the present invention, the center of the surface is depressed in a concave shape, so that the spherical bump 45 (solder ball 45A) can be easily fitted into the inside thereof. In addition, since the concave electrode pad 6 is set at the correct electrode pad position at the two-dimensional grid intersection, it can be easily positioned. further,
The inner diameter of the non-through hole of the concave electrode pad 6 is slightly larger than the outer diameter D of the spherical bump 45 to be inserted (0.05 to 0.20).
mm), the gap between the inner diameter of the concave electrode pad 6 and the outer diameter D of the bump 45 is reduced, and the planar positioning accuracy is increased.
【００１８】さらに、この凹形状の電極パッド６の配線
基板１０のバンプ形成側の基板表面から凹設穴底面まで
の非貫通穴の深さＳは、この凹設穴にはめ込む球形状バ
ンプ４５の外径Ｄより若干小さくして配線基板１０のバ
ンプ形成側の基板表面から、バンプ４５の先端面が若干
（０．２０〜０．４０ｍｍ）突出するように、バンプ４
５の大きさを選定するか、または所定の非貫通穴の深さ
Ｓとなるように凹設穴を加工したり、配線基板１０の板
厚を選択して決めることもできる。Further, the depth S of the non-through hole from the substrate surface on the bump forming side of the wiring substrate 10 of the concave electrode pad 6 to the bottom surface of the concave hole is determined by the depth of the spherical bump 45 fitted in the concave hole. The bumps 4 are slightly smaller than the outer diameter D so that the tip surfaces of the bumps 45 slightly (0.20 to 0.40 mm) protrude from the surface of the wiring board 10 on the bump formation side.
The size of the wiring board 10 can be determined by selecting the size of the wiring board 5, or by machining a recessed hole so as to have a predetermined non-through hole depth S, or by selecting the thickness of the wiring board 10.
【００１９】すなわち、図２に基づいて本発明による球
形状のバンプ４５を凹設する状態を説明する。配線基板
１０の凹形状の電極パッド６の内部に導電性ペースト８
を塗布してから球形状バンプ４５として例えば、球形状
のはんだボール４５Ａをはめ込み仮固定をした後、表面
がテフロン、セラミック、ガラスなどの非金属被膜で形
成されている平坦な治具４７に球形状のはんだボール４
５Ａの先端面が均一なレベルとなるように設定してリフ
ローはんだ付け等の熱処理によって、２次元に配置され
る多数の球形状のはんだボール４５Ａの突出する先端面
の高さが均一なレベルとなる。また、配線基板１０のバ
ンプ形成側の基板表面５Ａからバンプの先端面までの高
さＨを均一にするため治具４７には台座４８を設け、配
線基板１０の所定箇所を保持して熱処理を行なう。That is, a state in which the spherical bump 45 according to the present invention is recessed will be described with reference to FIG. The conductive paste 8 is provided inside the concave electrode pads 6 of the wiring board 10.
After applying, for example, a spherical solder ball 45A is fitted as the spherical bump 45 and temporarily fixed, and then the ball is placed on a flat jig 47 whose surface is formed of a non-metallic coating such as Teflon, ceramic, or glass. Shaped solder ball 4
The height of the protruding tip surfaces of a large number of two-dimensionally arranged solder balls 45A two-dimensionally arranged by heat treatment such as reflow soldering is set so that the tip surfaces of 5A are set to a uniform level. Become. Also, a pedestal 48 is provided on the jig 47 to make the height H from the substrate surface 5A on the bump formation side of the wiring substrate 10 to the tip end surface of the bump uniform, and a predetermined portion of the wiring substrate 10 is held and heat treatment is performed. Do.
【００２０】なお、多層配線基板の凹設穴の一例として
図３に基づいて説明する。配線基板１０に形成する凹形
状の電極パッド６の形状として、配線基板１０の板厚が
厚い場合や多層配線基板である場合は配線基板１０のバ
ンプ形成側の基板表面５Ａから凹設穴底面までの非貫通
穴の深さＳは、この凹形状の電極パッド６にはめ込むバ
ンプ４５の大きさで決定される。従って電子部品搭載面
の表面外層導体３とバンプ形成側の表面外層導体５とは
必ずしも電気的に導通しているとは限らず、凹形状の電
極パッド６の絶縁性基材１内部や凹設穴の反対面に絶縁
樹脂や基材が存在することになる。多層配線基板では、
内層導体２のなかでもバンプ形成側の表面外層導体５
と、バンプ形成側に最も近い内層導体２Ａとの間に形成
されるブラインドスルーホール穴９を凹形状の電極パッ
ド６として利用することもできる。１７はソルダーレジ
ストを示す。An example of a recessed hole in a multilayer wiring board will be described with reference to FIG. As the shape of the concave electrode pad 6 formed on the wiring board 10, when the thickness of the wiring board 10 is large or in the case of a multilayer wiring board, from the substrate surface 5A on the bump forming side of the wiring board 10 to the bottom of the recessed hole. The depth S of the non-through hole is determined by the size of the bump 45 fitted into the concave electrode pad 6. Therefore, the outer surface layer conductor 3 on the electronic component mounting surface and the outer surface layer conductor 5 on the bump formation side are not always electrically connected to each other. The insulating resin and the base material exist on the opposite surface of the hole. In a multilayer wiring board,
Among the inner layer conductors 2, the surface outer layer conductor 5 on the bump forming side
And a blind through-hole 9 formed between the inner conductor 2A closest to the bump formation side and the inner layer conductor 2A can be used as the electrode pad 6 having a concave shape. Reference numeral 17 denotes a solder resist.
【００２１】また、配線基板１０に形成される非貫通穴
の凹形状の電極パッド６の形状としては、非貫通穴の上
端縁と凹設穴の壁面とのなす断面角度が鈍角となる９０
゜〜１１０゜で形成することにより球形状のバンプ４５
を、凹形状の電極パッド６の一つである台形状の非貫通
穴内部に安定してはめ込むことは簡単にでき、台形状の
電極パッドの内径とバンプ４５の外径Ｄとの間隙が少な
くなり位置決め精度を高くすることができる。The shape of the concave electrode pad 6 of the non-through hole formed in the wiring board 10 is such that the cross-sectional angle between the upper edge of the non-through hole and the wall surface of the concave hole is obtuse.
Spherical bumps 45 formed by {-110}
Can be easily and stably fitted inside the trapezoidal non-through hole, which is one of the concave electrode pads 6, and the gap between the inner diameter of the trapezoidal electrode pad and the outer diameter D of the bump 45 is small. The positioning accuracy can be increased.
【００２２】さらに、絶縁性基材１の薄い片面配線基板
について図４に基づいて説明する。すなわち、絶縁性基
材１の板厚が０．１０〜０．６０ｍｍと薄い片面配線基
板ではバンプ４５を形成する側の表面外層導体５を省略
し、絶縁性基材１と、絶縁性基材を貫通する穴７と、こ
の絶縁性基材を貫通する穴の一方の端面を塞ぐ表面外層
導体つまり、電子部品搭載面の表面外層導体３と、から
なる非貫通穴である凹形状の電極パッド６を有する電子
部品搭載用配線基板とする。電子部品を搭載するための
配線基板にバンプを形成する場合は、上記の絶縁性基材
を貫通する穴７の一方の端面を塞ぐ表面外層導体側に
は、通常は電子部品４０を搭載し、本発明では、この絶
縁性基材を貫通する穴７の内壁には導体層を形成せず、
球形状バンプ４５は電子部品搭載面の表面外層導体３の
反対面の非貫通穴内の導体層に、はんだ付用フラックス
または導電性ペースト８を塗布あるいは充填し、そこに
球形状のバンプ４５をはめ込んだ状態で接着して仮固定
をする。また、上記の電子部品搭載用配線基板は、片面
配線基板の他にフレキシブル配線基板でも非貫通穴であ
る凹形状の電極パッド６を形成することにより目的を達
成することができる。Further, a thin single-sided wiring board of the insulating substrate 1 will be described with reference to FIG. That is, in the case of a single-sided wiring board in which the board thickness of the insulating base material 1 is as thin as 0.10 to 0.60 mm, the surface outer layer conductor 5 on the side where the bumps 45 are formed is omitted, and the insulating base material 1 and the insulating base material Concave electrode pad, which is a non-through hole composed of a hole 7 penetrating through the insulating substrate and a surface outer layer conductor closing one end face of the hole penetrating the insulating base material, that is, a surface outer layer conductor 3 on the electronic component mounting surface. 6 is a wiring board for mounting electronic components. When a bump is formed on a wiring board for mounting an electronic component, an electronic component 40 is usually mounted on the surface outer layer conductor side that closes one end face of the hole 7 penetrating the insulating base material, In the present invention, the conductor layer is not formed on the inner wall of the hole 7 penetrating the insulating base material,
The spherical bump 45 is formed by applying or filling a soldering flux or a conductive paste 8 to the conductor layer in the non-through hole on the opposite side of the surface outer layer conductor 3 on the electronic component mounting surface, and fitting the spherical bump 45 therein. Adhesively fix it temporarily. Further, the above-mentioned electronic component mounting wiring board can achieve the object by forming the concave electrode pad 6 which is a non-through hole in a flexible wiring board in addition to a single-sided wiring board.
【００２３】[0023]
【実施例】本発明における実施例として、配線基板１０
は板厚０．２ｍｍのＢＴレジン基材とし、ＢＧＡの端子
ピッチ１．０ｍｍで２次元のマトリクス状に配列できる
凹形状の電極パッド６を短パルスＣＯ2ガスレーザーで
穿孔し、銅めっきを施こし非貫通導通穴とした。バンプ
４５として、球形状のはんだボール４５Ａの外径φ０．
５０ｍｍを使用し、凹形状の電極パッド６の内径は０．
５５〜０．６５ｍｍとした。また、この凹形状の電極パ
ッド６の内部に、はんだボール４５Ａを仮固定する接着
剤として、はんだ付用フラックスを使用する場合には電
極パッド６の内径は０．５５〜０．６０ｍｍが良く、ク
リームはんだを使用する場合には０．６０〜０．６５ｍ
ｍが良好であった。DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a wiring board 10 will be described.
Is a BT resin base material with a plate thickness of 0.2 mm, and punches a concave electrode pad 6 that can be arranged in a two-dimensional matrix at a terminal pitch of BGA of 1.0 mm with a short pulse CO 2 gas laser and performs copper plating. This was a non-through conductive hole. As the bump 45, the outer diameter φ0.
The inner diameter of the concave electrode pad 6 is 0.5 mm.
It was 55-0.65 mm. When a soldering flux is used as an adhesive for temporarily fixing the solder ball 45A inside the concave electrode pad 6, the inner diameter of the electrode pad 6 is preferably 0.55 to 0.60 mm. 0.60 to 0.65 m when using cream solder
m was good.
【００２４】上記の凹形状の電極パッド６のバンプ形成
側の基板表面５Ａから凹設穴底面までの非貫通穴の深さ
Ｓは約０．３８ｍｍとなり、バンプ４５（はんだボール
４５Ａ）の外径Ｄのφ０．５０ｍｍより０．１２ｍｍ小
さくしたが、この数値が０．１０mm未満ではバンプ４５
が凹設穴の内部に埋没してバンプ４５の先端面の露出高
さが不足し、０．３０ｍｍを越えるとバンプ４５の外径
Ｄの半分以上が露出して凹形状の電極パッド６の内部に
仮固定する２次元の位置決め精度が悪くなる。従って、
配線基板１０のバンプ形成側の基板表面から凹設穴底面
までの非貫通穴の深さＳはバンプの外径Ｄより０．１０
〜０．３０ｍｍ小さくし、配線基板１０のバンプ形成側
の基板表面からバンプの先端面までの高さＨが０．２０
〜０．４０ｍｍ突出するようにバンプを形成することが
良好である。The depth S of the non-through hole from the substrate surface 5A on the bump forming side of the concave electrode pad 6 to the bottom surface of the concave hole is about 0.38 mm, and the outer diameter of the bump 45 (solder ball 45A). D was reduced by 0.12 mm from φ0.50 mm.
Is buried in the recessed hole and the exposed height of the tip surface of the bump 45 is insufficient. If it exceeds 0.30 mm, more than half of the outer diameter D of the bump 45 is exposed and the inside of the concave electrode pad 6 is exposed. , The two-dimensional positioning accuracy for temporary fixing is deteriorated. Therefore,
The depth S of the non-through hole from the substrate surface on the bump formation side of the wiring substrate 10 to the bottom of the concave hole is 0.10 from the outer diameter D of the bump.
0.30 mm, and the height H from the substrate surface on the bump forming side of the wiring substrate 10 to the tip end surface of the bump is 0.20 mm.
It is preferable to form the bumps so as to project by 0.40 mm.
【００２５】[0025]
【発明の効果】以上、図５で説明したように、従来の電
子部品４０を搭載した従来の配線基板３１の下面外層導
体３５に形成されている電極パッド３６は平面的で多数
の球形状バンプ４５を正確に位置決めをし、さらに球形
状バンプのバンプ形成側の基板表面５Ａから先端面の高
さまでのバラツキをなくして固定することは非常に難し
いが、本発明の図１〜図４で説明したように、従来の平
面的な電極パッドを配線基板１０の表面から絶縁性基材
１側内部に、その表面中央部を凹形状に陥没して非貫通
穴である凹形状の電極パッド６を形成し、凹形状の電極
パッド６内部に球形状バンプ４５を簡単にはめ込むこと
により、正しい電極パッド位置に容易に位置決めをする
ことができる。As described above with reference to FIG. 5, the electrode pads 36 formed on the outer conductor 35 on the lower surface of the conventional wiring board 31 on which the conventional electronic components 40 are mounted are flat and have many spherical bumps. Although it is very difficult to accurately position the 45 and fix it without any variation from the substrate surface 5A on the bump forming side of the spherical bump to the height of the tip end surface, it will be described with reference to FIGS. As described above, a conventional planar electrode pad is inserted from the surface of the wiring board 10 into the insulating substrate 1 side, and a concave electrode pad 6 which is a non-through hole by depressing the center of the surface into a concave shape. By forming and easily fitting the spherical bumps 45 into the concave electrode pads 6, the correct electrode pad positions can be easily positioned.
【００２６】また、本発明では凹形状の電極パッド６内
部に球形状バンプ４５を挿入形成する深さを治具４７に
より調節することにより、多数の球形状バンプ４５の突
出する先端面の高さレベルを平坦化でき、親配線基板２
２の接続用ランド２６との間隔が一定となり、電子部品
搭載用配線基板と親配線基板２２とのバンプ接続による
実装を簡単な構成によって確実に行い高い信頼性を確保
することができる。Also, in the present invention, the depth at which the spherical bumps 45 are inserted and formed in the concave electrode pads 6 is adjusted by the jig 47 so that the height of the projecting end surfaces of the numerous spherical bumps 45 is increased. Level can be flattened, parent wiring board 2
The distance between the second connection land 26 and the connection land 26 is constant, so that the electronic component mounting wiring board and the parent wiring board 22 can be securely mounted with a simple configuration by bump connection and high reliability can be secured.
【図１】本発明を説明する電子部品搭載状態の配線基板
断面図。FIG. 1 is a cross-sectional view of a wiring board in a state where electronic components are mounted, explaining the present invention.
【図２】本発明による球形状のバンプを凹設する状態を
示した断面図。FIG. 2 is a sectional view showing a state where a spherical bump according to the present invention is recessed.
【図３】本発明の多層配線基板凹設穴の例を示す配線基
板断面図。FIG. 3 is a cross-sectional view of a wiring board showing an example of a recessed hole in a multilayer wiring board of the present invention.
【図４】本発明の片面配線基板の電子部品搭載用配線基
板断面図。FIG. 4 is a cross-sectional view of a wiring board for mounting electronic components on a single-sided wiring board of the present invention.
【図５】従来の電子部品搭載用の配線基板断面図。FIG. 5 is a sectional view of a conventional wiring board for mounting electronic components.
１…絶縁性基材 ２…内層導体 ３…電子部品搭
載面の表面外層導体 ４…非貫通穴内の導体層 ５…バンプ形成側
の表面外層導体 ５Ａ…バンプ形成側の基板表面 ６…凹形状の電極
パッド ７…絶縁性基材を貫通する穴 ８…導電性ペース
ト ９…ブラインドスルーホール穴 １０…配線基板 １
７…ソルダーレジスト ２２…親配線基板（マザーボード） ２６…接続用ラン
ド ２８…クリームはんだ ３１…従来の配線基板 ３
２…貫通孔 ３３…上面外層導体 ３４…スルーホールめっき層 ３５…下面外層導体 ３６…電極パッド ３９…充填物 ４０…電子部品 ４１…ボン
ディング・ワイヤ ４５…バンプ ４５Ａ…はんだボール ４７…治具
４８…台座 Ｄ…バンプの外径 Ｓ…非貫通
穴の深さ Ｈ…バンプ形成側の基板表面からバンプの先端面までの
高さ。DESCRIPTION OF SYMBOLS 1 ... Insulating base material 2 ... Inner layer conductor 3 ... Surface outer layer conductor on electronic component mounting surface 4 ... Conductor layer in non-through hole 5 ... Surface outer layer conductor on bump formation side 5A ... Bump formation side substrate surface 6 ... Concave shape Electrode pad 7: hole penetrating insulating base material 8: conductive paste 9: blind through-hole hole 10: wiring board 1
7 Solder resist 22 Parent wiring board (mother board) 26 Connection land 28 Cream solder 31 Conventional wiring board 3
2 ... Through hole 33 ... Upper surface outer layer conductor 34 ... Through hole plating layer 35 ... Lower surface outer layer conductor 36 ... Electrode pad 39 ... Filler 40 ... Electronic component 41 ... Bonding wire 45 ... Bump 45A ... Solder ball 47 ... Jig 48 ... Pedestal D: Outer diameter of the bump S: Depth of the non-through hole H: Height from the substrate surface on the bump formation side to the tip end surface of the bump.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/46 Ｈ０１Ｌ 23/12 Ｌ ──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. 6 Identification code FI H05K 3/46 H01L 23/12 L
Claims (5)
を形成する配線基板において、絶縁性基材と、絶縁性基
材を貫通する穴と、絶縁性基材を貫通する穴の一方の端
面を塞ぐ表面外層導体と、からなる凹形状の電極パッド
を有することを特徴とする電子部品搭載用配線基板。1. A wiring board in which bumps are formed on terminals connected to the outside of the wiring board, an insulating base material, a hole penetrating the insulating base material, and one end face of a hole passing through the insulating base material. A wiring board for mounting electronic components, characterized by having a concave electrode pad comprising a surface outer layer conductor for closing the surface.
を形成する配線基板において、絶縁性基材と、絶縁性基
材を貫通する穴と、絶縁性基材を貫通する穴の一方の端
面を塞ぐ表面外層導体と、閉孔している非貫通穴内の導
体層と、からなる凹形状の電極パッドを有することを特
徴とする電子部品搭載用配線基板。2. A wiring board for forming a bump on a terminal connected to the outside of the wiring board, the insulating base material, a hole penetrating the insulating base material, and one end face of the hole penetrating the insulating base material. A wiring board for mounting an electronic component, comprising: a concave electrode pad formed of a surface outer layer conductor that closes a hole and a conductor layer in a closed non-through hole.
を形成する配線基板において、絶縁性基材と、絶縁性基
材を貫通する穴と、絶縁性基材を貫通する穴の一方の端
面を塞ぐ表面外層導体と、閉孔している非貫通穴内の導
体層と、絶縁性基材を貫通する穴の他方の開孔している
穴端面の一部もしくは全周に接して設けられた外層導体
と、からなる凹形状の電極パッドを有することを特徴と
する電子部品搭載用配線基板。3. A wiring board in which bumps are formed on terminals connected to the outside of the wiring board, an insulating base material, a hole passing through the insulating base material, and one end face of the hole passing through the insulating base material. Surface outer layer conductor that closes, a conductor layer in a closed non-through hole, and a portion or the entire circumference of the other open hole end face of the hole penetrating the insulating base material. An electronic component mounting wiring board, comprising: a concave electrode pad comprising an outer layer conductor.
を形成する多層配線基板において、バンプを形成する側
の表面外層導体と、内層導体との間に形成するブライン
ドスルーホール穴を、バンプを形成する凹形状の電極パ
ッドとして使用することを特徴とする電子部品搭載用配
線基板。4. A multilayer wiring board in which a bump is formed on a terminal connected to the outside of a wiring board, wherein a blind through-hole formed between the outer conductor on the surface on which the bump is formed and the inner conductor is formed with the bump. A wiring board for mounting electronic components, wherein the wiring board is used as a concave electrode pad to be formed.
通穴の深さ（Ｓ）が上記バンプの外径（Ｄ）よりも若干
小さく形成されていることを特徴とする請求項１から請
求項４のいずれかに記載の電子部品搭載用配線基板。5. The concave electrode pad, wherein the depth (S) of the non-through hole is formed to be slightly smaller than the outer diameter (D) of the bump. 4. The wiring board for mounting electronic components according to any one of 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10046382A JP2943788B2 (en) | 1997-04-10 | 1998-02-13 | Wiring board for mounting electronic components |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10683097 | 1997-04-10 | ||
| JP9-106830 | 1997-04-10 | ||
| JP10046382A JP2943788B2 (en) | 1997-04-10 | 1998-02-13 | Wiring board for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10340929A true JPH10340929A (en) | 1998-12-22 |
| JP2943788B2 JP2943788B2 (en) | 1999-08-30 |
Family
ID=26386489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10046382A Expired - Fee Related JP2943788B2 (en) | 1997-04-10 | 1998-02-13 | Wiring board for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2943788B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100726922B1 (en) * | 2000-12-19 | 2007-06-14 | 히다찌 케이블 리미티드 | Wiring board for a lga type semiconductor device, a lga type semiconductor device, and process for production of wiring board for a lga type semiconductor device |
| JP2007157620A (en) * | 2005-12-08 | 2007-06-21 | D D K Ltd | Electrical contact structure |
| US7463475B2 (en) | 2005-07-27 | 2008-12-09 | Murata Manufacturing Co., Ltd. | Multilayer electronic component, electronic device, and method for manufacturing multilayer electronic component |
| KR100900182B1 (en) | 2007-12-13 | 2009-06-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| JP2009246300A (en) * | 2008-03-31 | 2009-10-22 | Tdk Corp | Surface mounted part, method for manufacturing therefor, and mounting method |
| JP4854738B2 (en) * | 2006-06-15 | 2012-01-18 | 三洋電機株式会社 | Electronic components |
| JP2017515295A (en) * | 2014-02-18 | 2017-06-08 | クアルコム，インコーポレイテッド | Low profile package with passive devices |
| KR20210062130A (en) * | 2019-11-20 | 2021-05-31 | (주)에이티세미콘 | Semiconductor package |
-
1998
- 1998-02-13 JP JP10046382A patent/JP2943788B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100726922B1 (en) * | 2000-12-19 | 2007-06-14 | 히다찌 케이블 리미티드 | Wiring board for a lga type semiconductor device, a lga type semiconductor device, and process for production of wiring board for a lga type semiconductor device |
| US7463475B2 (en) | 2005-07-27 | 2008-12-09 | Murata Manufacturing Co., Ltd. | Multilayer electronic component, electronic device, and method for manufacturing multilayer electronic component |
| JP2007157620A (en) * | 2005-12-08 | 2007-06-21 | D D K Ltd | Electrical contact structure |
| JP4854738B2 (en) * | 2006-06-15 | 2012-01-18 | 三洋電機株式会社 | Electronic components |
| KR100900182B1 (en) | 2007-12-13 | 2009-06-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| JP2009246300A (en) * | 2008-03-31 | 2009-10-22 | Tdk Corp | Surface mounted part, method for manufacturing therefor, and mounting method |
| JP2017515295A (en) * | 2014-02-18 | 2017-06-08 | クアルコム，インコーポレイテッド | Low profile package with passive devices |
| KR20210062130A (en) * | 2019-11-20 | 2021-05-31 | (주)에이티세미콘 | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2943788B2 (en) | 1999-08-30 |
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