JPH10335263A - Manufacture of titanium silicide - Google Patents

Manufacture of titanium silicide

Info

Publication number
JPH10335263A
JPH10335263A JP10089622A JP8962298A JPH10335263A JP H10335263 A JPH10335263 A JP H10335263A JP 10089622 A JP10089622 A JP 10089622A JP 8962298 A JP8962298 A JP 8962298A JP H10335263 A JPH10335263 A JP H10335263A
Authority
JP
Japan
Prior art keywords
titanium silicide
silicide film
film
titanium
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10089622A
Other languages
Japanese (ja)
Inventor
Osei So
▼オー▼ 聲 宋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH10335263A publication Critical patent/JPH10335263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers

Abstract

PROBLEM TO BE SOLVED: To form a titanium silicide film which is stable and low in resistance even if it is lower than 0.25 μm in line width, by a method wherein ions are implanted into a titanium silicide film of C49 structure, which is unstable after it is subjected to a primary thermal treatment, to increase it in stress energy so as to lessen nucleuses which induce a phase transition in critical size. SOLUTION: A first titanium silicide film 117 on a gate electrode 113 and source/drain regions 115 is subjected to a secondary thermal treatment in a rapid thermal process to turn to a second titanium silicide film 119 which is of C54 structure and stable. At this point, nucleuses which induce a phase transition are lessened in critical radius through an ion implantation process, so that the titanium silicide film 117 is easily transformed in phase and turned to the titanium silicide film 119 of C54 structure, even if the titanium silicide film 117 is smaller tin line width than 0.25 μm, and the second titanium silicide film 119 which is 5 Ω/sq or so in contact resistance even if it smaller than 0.25 μm in line width can be manufactured. Lastly, the unreacted titanium metal film 117 on a side wall spacer 114 is removed, where the metal film 117 on the side wall spacer 114 may be removed off before an ion implantation process.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、シリサイド（ｓｉ
ｌｉｃｉｄｅ）の製造方法に係るもので、特に０．２５
μｍ以下のゲート線幅に適するチタンシリサイドの製造
方法に関する。TECHNICAL FIELD The present invention relates to a silicide (si)
liquidide), particularly 0.25
The present invention relates to a method for producing titanium silicide suitable for a gate line width of μm or less.

【０００２】[0002]

【従来の技術】最近、半導体素子の微細化及び高速化に
伴って配線材料の低抵抗化の研究が活発に行われてい
る。例えば、多層配線の上層部配線の場合、該配線を構
成するアルミニウムの高信頼性化のため、前記アルミニ
ウムのグレーン（ｇｒａｉｎ）サイズを大型化したり、
グレーンを高配向化させており、さらには高信頼性を確
保すると共に低抵抗化を実現するために銅への材料変更
も検討されている。又、ゲート電極とビットラインのよ
うな下層部配線の場合は、高集積化に伴うプロセスの低
温化のため、モリブテンとタングステンを用いたシリサ
イドからチタン、コバルト、またはニッケルを用いたシ
リサイドへの材料の変更が検討されている。2. Description of the Related Art Recently, with the miniaturization and high-speed operation of semiconductor devices, research on reducing the resistance of wiring materials has been actively conducted. For example, in the case of an upper layer wiring of a multilayer wiring, the grain size of the aluminum is increased in order to increase the reliability of aluminum constituting the wiring,
The grain is highly oriented, and furthermore, a material change to copper is being studied in order to secure high reliability and realize low resistance. In the case of the lower layer wiring such as the gate electrode and the bit line, the material is changed from silicide using molybdenum and tungsten to silicide using titanium, cobalt, or nickel in order to lower the temperature of the process accompanying high integration. Changes are being considered.

【０００３】前記モリブデンとタングステンのシリサイ
ドは８００℃以下のプロセス温度で８０μΩ／cm以下の
比抵抗を得ることが難しいが、チタンシリサイド（Ｔｉ
Ｓｉ2 ）では斜方晶Ｃ５４型構造で１３〜２０μΩ／cm
と比抵抗を低くできる。したがって、シリサイドの中で
もチタンシリサイドが最も積極的に研究されており、か
つ０．３５μｍ世代の大部分のＣＭＯＳロジック素子に
採用されている。しかし、チタンシリサイドでも、素子
の大きさが一層微細化されるに従いシート抵抗が上昇す
るという問題点が顕著に現れている。It is difficult to obtain a specific resistance of 80 .mu..OMEGA. / Cm or less at a process temperature of 800.degree. C. or less with molybdenum and tungsten silicide.
Si 2 ) has an orthorhombic C54 type structure and 13 to 20 μΩ / cm.
And the specific resistance can be reduced. Therefore, among silicides, titanium silicide has been most actively studied, and has been adopted in most CMOS logic devices of the 0.35 μm generation. However, even with titanium silicide, the problem that the sheet resistance increases as the size of the element is further miniaturized has been prominent.

【０００４】図４は、ＭＯＳトランジスタのゲート電極
及びソース／ドレイン領域上にチタンシリサイドを形成
する従来のチタンシリサイドの製造方法を示す断面図で
あり、図５はこの従来の方法で製造した場合におけるゲ
ートシート抵抗のゲート長さ依存性を示す特性図であ
る。FIG. 4 is a cross-sectional view showing a conventional method of manufacturing titanium silicide for forming a titanium silicide on a gate electrode and a source / drain region of a MOS transistor. FIG. 5 shows a case where the titanium silicide is manufactured by the conventional method. FIG. 4 is a characteristic diagram showing gate length dependence of a gate sheet resistance.

【０００５】図４の製造方法を説明すると、まず、図４
（ａ）に示すように、半導体基板１１のゲート形成位置
上にゲート酸化膜１２とゲート電極１３を形成する。次
に、ゲート電極１３上とソース／ドレイン領域上とでチ
タンシリサイドを分離するために、図４（ｂ）に示すよ
うに、ゲート電極１３の側壁に酸化膜の側壁スペーサ１
４を形成する。その後、ゲート電極１３と側壁スペーサ
１４とをマスクとして半導体基板１１内に不純物を注入
してソース／ドレイン領域１５を形成する。次いで、ス
パッタリング法によりチタン金属膜を基板１１上の全面
に形成した後、ソース／ドレイン領域１５のドーピング
レベルを維持するために３０秒以内の短い時間でＲＴＰ
（ｒａｐｉｄ ｔｈｅｒｍａｌ ｐｒｏｃｅｓｓ）によ
り６００〜８００℃の１次熱処理をし、さらに高温で２
回目の熱処理をする。この熱処理により、ゲート電極１
３とソース／ドレイン領域１５上のチタン金属膜は、ゲ
ート電極１３とソース／ドレイン領域１５のシリコンと
反応し、図４（ｃ）に示すようにチタンシリサイド膜１
６となる。その後、側壁スペーサ１４部分などの未反応
チタン金属膜を除去する。[0005] To explain the manufacturing method of FIG.
As shown in FIG. 1A, a gate oxide film 12 and a gate electrode 13 are formed on a gate formation position of a semiconductor substrate 11. Next, in order to separate titanium silicide on the gate electrode 13 and on the source / drain regions, as shown in FIG.
4 is formed. Thereafter, using the gate electrode 13 and the sidewall spacers 14 as a mask, impurities are implanted into the semiconductor substrate 11 to form source / drain regions 15. Next, after a titanium metal film is formed on the entire surface of the substrate 11 by a sputtering method, the RTP is shortened within 30 seconds to maintain the doping level of the source / drain regions 15.
(Rapid thermal process) to perform a primary heat treatment at 600 to 800 ° C.
The second heat treatment is performed. By this heat treatment, the gate electrode 1
3 and the titanium metal film on the source / drain regions 15 react with the gate electrode 13 and the silicon in the source / drain regions 15 to form the titanium silicide film 1 as shown in FIG.
It becomes 6. After that, the unreacted titanium metal film such as the side wall spacer 14 is removed.

【０００６】このような製造方法では、ＲＴＰによる前
記１次熱処理時、成膜されたチタン金属膜と、ゲート電
極１３及びソース／ドレイン領域１５のシリコン間の拡
散によりＣ４９構造の不安定なチタンシリサイド（Ｔｉ
Ｓｉｘ）が形成される。その理由は図５内の右側上部の
ラマン分光の結果のように、Ｃ５４構造への相転移が未
だ生じていないからであり、このＣ４９構造のチタンシ
リサイドは図５に示すように比抵抗が３０〜６０Ω／ｓ
ｑ程度と高い。このＣ４９構造の不安定なチタンシリサ
イドを前記のように２次熱処理すると、Ｃ５４構造を有
する安定したシリサイドが生成される。このときの抵抗
は図５に示すように５Ω／ｓｑ程度と非常に低い。In such a manufacturing method, an unstable titanium silicide having a C49 structure is formed due to diffusion between the titanium metal film formed during the first heat treatment by RTP and silicon in the gate electrode 13 and the source / drain region 15. (Ti
Six) is formed. The reason is that the phase transition to the C54 structure has not yet occurred, as shown in the result of Raman spectroscopy on the upper right side in FIG. 5, and the titanium silicide having the C49 structure has a specific resistance of 30 as shown in FIG. ~ 60Ω / s
It is as high as q. When the above-described unstable titanium silicide having the C49 structure is subjected to the second heat treatment as described above, a stable silicide having the C54 structure is generated. The resistance at this time is as low as about 5 Ω / sq as shown in FIG.

【０００７】[0007]

【発明が解決しようとする課題】しかし、０．２５μｍ
以下の線幅では、相転移を生じさせる臨界核の生成大き
さが線幅よりも大きくて、核生成及び成長機構を通じた
Ｃ４９構造からＣ５４構造への相転移が生じないため、
図５に示すように、チタンシリサイドの抵抗値が急激に
増加するという問題点があった。However, 0.25 μm
In the following line widths, the size of critical nuclei for generating a phase transition is larger than the line width, and no phase transition from the C49 structure to the C54 structure occurs through the nucleation and growth mechanism.
As shown in FIG. 5, there is a problem that the resistance value of titanium silicide increases rapidly.

【０００８】本発明は上記の点に鑑みなされたもので、
その目的は、０．２５μｍ以下の線幅でもＣ５４構造へ
の相転移が容易に生じるようにして、チタンシリサイド
の抵抗値を最小化し得るチタンシリサイドの製造方法を
提供することにある。[0008] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of manufacturing titanium silicide that can easily cause a phase transition to a C54 structure even at a line width of 0.25 μm or less and minimize the resistance value of titanium silicide.

【０００９】[0009]

【課題を解決するための手段】上記課題を解決し上記目
的を達成するために本発明は、半導体基板上に任意のシ
リコンパターンを形成する工程と、前記シリコンパター
ン及び前記半導体基板上にチタン金属膜を形成する工程
と、前記チタン金属膜を１次熱処理して不安定な結晶構
造の第１チタンシリサイド膜を形成する工程と、前記第
１チタンシリサイド膜に不純物をイオン注入する工程
と、このイオン注入後、前記第１チタンシリサイド膜を
２次熱処理して安定した結晶構造の第２チタンシリサイ
ド膜を形成する工程とを具備することを特徴とするチタ
ンシリサイドの製造方法とする。SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a process for forming an arbitrary silicon pattern on a semiconductor substrate, and a method for forming a titanium metal on the silicon pattern and the semiconductor substrate. Forming a film, performing a first heat treatment on the titanium metal film to form a first titanium silicide film having an unstable crystal structure, and ion-implanting impurities into the first titanium silicide film. Forming a second titanium silicide film having a stable crystal structure by subjecting the first titanium silicide film to a second heat treatment after the ion implantation.

【００１０】図１は、自由エネルギと核の大きさの関係
を示す特性図である。この図を参照して本発明の原理を
数式的に説明すると、次の通りである。まず、相変化の
発生する３次元的な単純なモデルを仮定した時、円形の
核から成長する相変態を表現する自由エネルギ（ΔＧ）
は次の式１のようである。FIG. 1 is a characteristic diagram showing the relationship between free energy and the size of a nucleus. The principle of the present invention will be described mathematically with reference to FIG. First, assuming a simple three-dimensional model in which a phase change occurs, the free energy (ΔG) expressing the phase transformation growing from a circular nucleus
Is as in the following equation 1.

【数１】 （但し、ｅはストレイン係数で、Ｅは弾性係数である） ここで、一番目の項は単位体積当たり相変化時に必要と
されるエネルギを示し、二番目の項は表面エネルギを示
し、最後の項は人為的なイオン注入により生じたストレ
スエネルギを示す。(Equation 1) (Where e is the strain coefficient and E is the elastic modulus) Here, the first term indicates the energy required for the phase change per unit volume, the second term indicates the surface energy, and the last The term indicates stress energy generated by artificial ion implantation.

【００１１】このとき、エネルギが平衡状態であると仮
定すれば、前記自由エネルギの変化率は０であるから、
相転移が生じる最小大きさの核の半径である臨界核半径
（γ* ）は次の式２のようである。At this time, assuming that the energy is in an equilibrium state, the rate of change of the free energy is zero.
The critical nuclear radius (γ * ), which is the radius of the minimum size nucleus at which a phase transition occurs, is given by the following equation 2.

【数２】 (Equation 2)

【００１２】この式２によると、最小大きさの核の半径
は、変化させにくい△Ｇγ、γの代わりに、ストレスエ
ネルギ（ｅＥ）を大きくすることにより減少させ得るこ
とがわかる。即ち、図１に示すように、ストレスエネル
ギを考慮しない状態（細い実線）と比較すると、ストレ
スエネルギを増加させると（太い実線）、前記相転移の
生じる最小臨界核の大きさを減らすことができる。本発
明は、この原理を利用したもので、１次熱処理後の不安
定なＣ４９構造のチタンシリサイド膜に対して不純物の
イオン注入を施して、ストレスエネルギを増加させるこ
とにより、相転移が生じる臨界核の大きさを減少させ
て、０．２５μｍ以下の線幅でも低抵抗の安定したチタ
ンシリサイドを形成するものである。According to Equation 2, it can be seen that the radius of the minimum size nucleus can be reduced by increasing the stress energy (eE) instead of ΔGγ, γ, which is hard to change. That is, as shown in FIG. 1, when the stress energy is increased (thick solid line), the size of the minimum critical nucleus where the phase transition occurs can be reduced as compared with a state where the stress energy is not considered (thin solid line). . The present invention utilizes this principle, and performs ion implantation of impurities into an unstable titanium silicide film having a C49 structure after the first heat treatment to increase stress energy, thereby causing critical phase transition to occur. By reducing the size of the nucleus, a low-resistance and stable titanium silicide is formed even with a line width of 0.25 μm or less.

【００１３】[0013]

【発明の実施の形態】以下本発明の実施の形態を図面を
参照して詳細に説明する。図２および図３は本発明の実
施の形態を工程順に示す断面図である。本発明の実施の
形態では、まず、図２（ａ）に示すように、フィールド
酸化膜（図示せず）が形成された半導体基板１１１のア
クティブ領域中、ゲート形成位置に通常のゲートパター
ン工程によりゲート酸化膜１１２とゲート電極１１３を
形成する。Embodiments of the present invention will be described below in detail with reference to the drawings. 2 and 3 are sectional views showing an embodiment of the present invention in the order of steps. In the embodiment of the present invention, first, as shown in FIG. 2A, in the active region of the semiconductor substrate 111 on which a field oxide film (not shown) is formed, a gate forming position is formed by a normal gate pattern process. A gate oxide film 112 and a gate electrode 113 are formed.

【００１４】次いで、基板１１１上の全面に酸化膜を成
長させた後食刻して、図２（ｂ）に示すようにゲート電
極１１３とゲート酸化膜１１２の側壁に側壁スペーサ１
１４を形成する。その後、ゲート電極１１３と側壁スペ
ーサ１１４をマスクとして半導体基板１１１のアクティ
ブ領域に不純物を注入することにより、該基板１１１の
アクティブ領域内にソース／ドレイン領域１１５を形成
する。Next, an oxide film is grown on the entire surface of the substrate 111 and then etched to form a sidewall spacer 1 on the sidewalls of the gate electrode 113 and the gate oxide film 112 as shown in FIG.
14 is formed. Thereafter, using the gate electrode 113 and the sidewall spacer 114 as a mask, impurities are implanted into the active region of the semiconductor substrate 111 to form source / drain regions 115 in the active region of the substrate 111.

【００１５】次いで、基板１１１上の全面にスパッタリ
ング法によりチタン金属膜を成膜した後、トランジスタ
のソース／ドレイン領域１１５のドーピングレベルを維
持するために３０秒以内の短い時間でＲＴＰにより６０
０〜８００°Ｃの１次熱処理を施す。この１次熱処理に
より、ゲート電極１１３およびソース／ドレイン領域１
１５上のチタン金属膜は、ゲート電極１１３およびソー
ス／ドレイン領域１１５のシリコンと反応し、図３
（ａ）に示すように、シート抵抗の大きいＣ４９構造の
第１チタンシリサイド膜１１７となる。一方、酸化膜か
らなる側壁スペーサ１１４上のチタン金属膜は反応せ
ず、チタン金属膜１１６として残る。Next, after a titanium metal film is formed on the entire surface of the substrate 111 by a sputtering method, RTP is performed by RTP within a short time of 30 seconds or less in order to maintain the doping level of the source / drain region 115 of the transistor.
A first heat treatment at 0 to 800 ° C. is performed. By this first heat treatment, the gate electrode 113 and the source / drain region 1
3 reacts with the silicon of the gate electrode 113 and the source / drain region 115, and
As shown in (a), the first titanium silicide film 117 having a C49 structure with a large sheet resistance is obtained. On the other hand, the titanium metal film on the sidewall spacer 114 made of an oxide film does not react and remains as a titanium metal film 116.

【００１６】その後、第１チタンシリサイド膜１１７に
対してＡｓ，Ｐ，Ｂ，ＢＦ2 ，ＳｉＨ4 ，ＧｅＨ4 のう
ち何れか一つの不純物を図３（ａ）に示すようにイオン
注入して、第１チタンシリサイド膜１１７のストレスエ
ネルギを増加させる。図３（ａ）中、符号１１８はＡ
ｓ，Ｐ，Ｂ，ＢＦ2 ，ＳｉＨ4 ，ＧｅＨ4 のイオン注入
粒子を示す。Thereafter, any one of As, P, B, BF 2 , SiH 4 , and GeH 4 is ion-implanted into the first titanium silicide film 117 as shown in FIG. The stress energy of the first titanium silicide film 117 is increased. In FIG. 3A, reference numeral 118 denotes A
2 shows ion-implanted particles of s, P, B, BF 2 , SiH 4 , and GeH 4 .

【００１７】ここで、通常、厚さ５００Å程度のチタン
シリサイド膜が素子製造で採用されているから、本実施
の形態でも第１チタンシリサイド膜１１７を５００Å程
度の厚さに形成する。また、不純物は例えばＡｓの場合
８０〜１００ｋｅＶ程度のエネルギで２ｅ12程度のドー
プ量で注入させる。このイオン注入の条件は、場合によ
っては変更可能である。そして、このようなイオン注入
工程を行うと、第１チタンシリサイド膜１１７のストレ
スエネルギが増加するので、Ｃ４９構造の第１チタンシ
リサイド膜１１７がＣ５４構造の安定したシリサイド膜
に変化するのに必要な臨界核半径（γ* ）は最小線幅
（０．２５μｍ）よりも小さくなる。Here, since a titanium silicide film having a thickness of about 500.degree. Is usually employed in the manufacture of the device, the first titanium silicide film 117 is formed to a thickness of about 500.degree. The impurity causes implanted at the doping amount of about 2e 12 at an energy of cases about 80~100keV e.g. As. The conditions for this ion implantation can be changed in some cases. When such an ion implantation step is performed, the stress energy of the first titanium silicide film 117 increases, so that it is necessary for the first titanium silicide film 117 having the C49 structure to change to a stable silicide film having the C54 structure. The critical nuclear radius (γ * ) is smaller than the minimum line width (0.25 μm).

【００１８】次いで、再びＲＴＰで高温の２次熱処理を
して、ゲート電極１１３およびソース／ドレイン領域１
１５上の第１チタンシリサイド膜１１７を図３（ｂ）に
示すように、Ｃ５４構造の安定した第２チタンシリサイ
ド膜１１９に変化させる。このとき、図３（ａ）のイオ
ン注入工程で相転移の生じる臨界核半径が小さくなった
ので、０．２５μｍ以下の線幅でもＣ５４構造への相転
移が容易に生じ、０．２５μｍ以下の線幅でも約５Ω／
ｓｑ程度のコンタクト抵抗を示す第２チタンシリサイド
膜１１９の製造が可能となる。Next, a high-temperature secondary heat treatment is again performed by RTP, so that the gate electrode 113 and the source / drain regions 1 are formed.
As shown in FIG. 3B, the first titanium silicide film 117 on the substrate 15 is changed to a stable second titanium silicide film 119 having a C54 structure. At this time, since the critical nucleus radius at which phase transition occurs in the ion implantation step of FIG. 3A is reduced, the phase transition to the C54 structure easily occurs even at a line width of 0.25 μm or less, and a phase transition of 0.25 μm or less occurs. About 5Ω /
The second titanium silicide film 119 having a contact resistance of about sq can be manufactured.

【００１９】最後に、側壁スペーサ１１４上の未反応チ
タン金属膜１１５を図３（ｂ）に示すように除去する。
この未反応チタン金属膜１１５の除去は、第１チタンシ
リサイド膜１１７の形成後、イオン注入を行う前に、あ
るいは、イオン注入後、２次熱処理を行う前に行っても
よい。Finally, the unreacted titanium metal film 115 on the side wall spacer 114 is removed as shown in FIG.
The removal of the unreacted titanium metal film 115 may be performed after forming the first titanium silicide film 117 and before performing ion implantation, or after performing ion implantation and before performing the second heat treatment.

【００２０】なお、本実施の形態は、ＭＯＳトランジス
タにおいて、ポリシリコンパターンのゲート電極１１３
および基板シリコンのソース／ドレイン領域１１５上に
チタンシリサイド膜を形成する場合であるが、本発明
は、その他の素子におけるチタンシリサイド膜の製造法
に利用できることはいうまでもない。In this embodiment, the MOS transistor has a gate electrode 113 of a polysilicon pattern.
And a case where a titanium silicide film is formed on the source / drain regions 115 of the substrate silicon. Needless to say, the present invention can be used for a method of manufacturing a titanium silicide film in other devices.

【００２１】[0021]

【発明の効果】以上詳細に説明したように、本発明のチ
タンシリサイドの製造方法によれば、１次熱処理後の不
安定なＣ４９構造のチタンシリサイドに対してイオン注
入を施して、ストレスエネルギを増加させることによ
り、相転移の生じる臨界核大きさを減少させるようにし
たので、０．２５μｍ以下の線幅でも容易に低抵抗の安
定したチタンシリサイドを形成することができる。As described above in detail, according to the method for manufacturing titanium silicide of the present invention, the ion energy is implanted into the unstable titanium silicide having the C49 structure after the first heat treatment to reduce the stress energy. By increasing the critical nucleus size at which the phase transition occurs, a low-resistance and stable titanium silicide can be easily formed even with a line width of 0.25 μm or less.

【図面の簡単な説明】[Brief description of the drawings]

【図１】自由エネルギと核の大きさの関係を示す特性
図。FIG. 1 is a characteristic diagram showing the relationship between free energy and the size of a nucleus.

【図２】本発明に係るチタンシリサイドの製造方法の実
施の形態を示す断面図。FIG. 2 is a sectional view showing an embodiment of the method for producing titanium silicide according to the present invention.

【図３】本発明に係るチタンシリサイドの製造方法の実
施の形態を示し、図２に続く工程を示す断面図。FIG. 3 is a sectional view showing the embodiment of the method for producing titanium silicide according to the present invention, and showing a step following FIG. 2;

【図４】従来のチタンシリサイドの製造方法を示す断面
図。FIG. 4 is a cross-sectional view showing a conventional method for manufacturing titanium silicide.

【図５】従来の方法で製造した場合におけるゲートシー
ト抵抗のゲート長さ依存性を示す特性図。FIG. 5 is a characteristic diagram showing a gate length dependency of a gate sheet resistance when manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

１１１ 半導体基板 １１３ ゲート電極 １１５ ソース／ドレイン領域 １１６ チタン金属膜 １１７ 第１チタンシリサイド膜 １１８ イオン注入粒子 １１９ 第２チタンシリサイド膜 Reference Signs List 111 semiconductor substrate 113 gate electrode 115 source / drain region 116 titanium metal film 117 first titanium silicide film 118 ion-implanted particles 119 second titanium silicide film

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に任意のシリコンパターン
を形成する工程と、前記シリコンパターン及び前記半導
体基板上にチタン金属膜を形成する工程と、 前記チタン金属膜を１次熱処理して不安定な結晶構造の
第１チタンシリサイド膜を形成する工程と、 前記第１チタンシリサイド膜に不純物をイオン注入する
工程と、 前記イオン注入後、前記第１チタンシリサイド膜を２次
熱処理して安定した結晶構造の第２チタンシリサイド膜
を形成する工程とを具備することを特徴とするチタンシ
リサイドの製造方法。A step of forming an arbitrary silicon pattern on a semiconductor substrate; a step of forming a titanium metal film on the silicon pattern and the semiconductor substrate; A step of forming a first titanium silicide film having a crystal structure; a step of ion-implanting an impurity into the first titanium silicide film; and a second heat treatment of the first titanium silicide film after the ion implantation to achieve a stable crystal structure. Forming a second titanium silicide film. 【請求項２】 前記第１チタンシリサイド膜形成後、前
記イオン注入を行う前に、あるいは、イオン注入後、２
次熱処理を行う前に、あるいは、２次熱処理実施後に未
反応チタン金属膜の除去工程を行うことを特徴とする請
求項１記載のチタンシリサイドの製造方法。2. After the formation of the first titanium silicide film, before the ion implantation, or after the ion implantation,
2. The method for producing titanium silicide according to claim 1, wherein a step of removing the unreacted titanium metal film is performed before performing the next heat treatment or after performing the second heat treatment. 【請求項３】 前記不純物は、Ａｓ，Ｐ，Ｂ，ＢＦ2 ，
ＳｉＨ4 ，ＧｅＨ4のうち何れか一つであることを特徴
とする請求項１記載のチタンシリサイドの製造方法。3. The method according to claim 1, wherein the impurities are As, P, B, BF 2 ,
SiH 4, the manufacturing method of the titanium silicide according to claim 1, characterized in that the one of GeH 4.
JP10089622A 1997-05-21 1998-04-02 Manufacture of titanium silicide Pending JPH10335263A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1997P-19798 1997-05-21
KR1019970019798A KR100231904B1 (en) 1997-05-21 1997-05-21 Method of forming ti silicide layer on a semiconductor device

Publications (1)

Publication Number Publication Date
JPH10335263A true JPH10335263A (en) 1998-12-18

Family

ID=19506575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10089622A Pending JPH10335263A (en) 1997-05-21 1998-04-02 Manufacture of titanium silicide

Country Status (2)

Country Link
JP (1) JPH10335263A (en)
KR (1) KR100231904B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395776B1 (en) * 2001-06-28 2003-08-21 동부전자 주식회사 Method for manufacturing a silicide layer of semiconductor device
US9645086B2 (en) 2013-08-30 2017-05-09 Kabushiki Kaisha Toshiba Componential analysis method, componential analysis apparatus and non-transitory computer-readable recording medium

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425147B1 (en) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR20010057688A (en) * 1999-12-23 2001-07-05 황인길 Method for forming titanium salicide of semiconductor device
JP2001189284A (en) * 1999-12-27 2001-07-10 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
KR100691936B1 (en) * 2000-11-29 2007-03-08 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395776B1 (en) * 2001-06-28 2003-08-21 동부전자 주식회사 Method for manufacturing a silicide layer of semiconductor device
US9645086B2 (en) 2013-08-30 2017-05-09 Kabushiki Kaisha Toshiba Componential analysis method, componential analysis apparatus and non-transitory computer-readable recording medium

Also Published As

Publication number Publication date
KR19980084129A (en) 1998-12-05
KR100231904B1 (en) 1999-12-01

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