JPH1032977A - Power factor improving circuit - Google Patents
Power factor improving circuitInfo
- Publication number
- JPH1032977A JPH1032977A JP8206604A JP20660496A JPH1032977A JP H1032977 A JPH1032977 A JP H1032977A JP 8206604 A JP8206604 A JP 8206604A JP 20660496 A JP20660496 A JP 20660496A JP H1032977 A JPH1032977 A JP H1032977A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- peak
- peak voltage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/30—Reactive power compensation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は昇圧型の力率改善回路に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boost type power factor improving circuit.
【０００２】[0002]
【従来の技術】従来より昇圧型コンバータ回路を使用し
た力率改善回路がいくつか提案されている。この一例と
して公開特許公報平成６年第９８５４２号に開示されて
いるような力率改善回路がある。当該出願の要旨を示す
図２において、力率改善回路はチョークコイルL1の入力
電圧Viを基準電圧として用い、このViと出力電圧Voとを
比較することでドライブ回路を駆動しトランジスタQ1の
オン、オフ制御を行って入力電圧に比例した出力電圧Vo
を出力する回路となっている。2. Description of the Related Art Hitherto, several power factor improving circuits using a boost converter circuit have been proposed. An example of this is a power factor correction circuit as disclosed in Japanese Patent Laid-Open Publication No. 98542/1994. In FIG. 2 showing the gist of the application, the power factor improving circuit uses the input voltage Vi of the choke coil L1 as a reference voltage, drives the drive circuit by comparing this Vi with the output voltage Vo, and turns on the transistor Q1. Output voltage Vo proportional to input voltage by performing off control
Is output.
【０００３】[0003]
【発明が解決しようとする課題】しかしながらこのよう
な力率改善回路では、出力電圧Voは入力電圧Viに比例す
るため、Viの変動範囲が広い場合ではVoはViに対して差
が大きくなり、後段の素子耐圧を大きくしなくてはなら
ない。However, in such a power factor improving circuit, since the output voltage Vo is proportional to the input voltage Vi, when the fluctuation range of Vi is wide, Vo becomes larger than Vi. The withstand voltage of the subsequent element must be increased.
【０００４】また、Viの変動がVoでは増幅されることを
考えれば、このような従来の昇圧コンバータ型の力率改
善回路では、電源回路として従来のコンデンサインプッ
ト型と比較しても安定度が損なわれることがある。[0004] Considering that the fluctuation of Vi is amplified by Vo, such a conventional boost converter type power factor correction circuit has a higher stability than a conventional capacitor input type as a power supply circuit. May be impaired.
【０００５】本発明は上記課題に鑑み、入力電圧の変動
が広い場合でも所望の出力電圧が小型の電気、電子素子
で構成できる力率改善回路を提供することを目的とす
る。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a power factor improving circuit in which a desired output voltage can be constituted by a small electric or electronic element even when the input voltage varies widely.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明では、交流電源を電源とし、チョークコイル
と、トランジスタ、ＰＷＭ制御回路を使用して出力電圧
を昇圧、平滑する力率改善回路において、前記ＰＷＭ制
御回路が、チョークコイルの前段のピーク電圧を検出す
るピーク電圧検出回路と、チョークコイル後段の平滑電
圧を検出しこの電圧値と前記ピーク電圧検出回路の出力
値とを比較する減算回路と、当該減算回路からの出力値
と基準電圧を作り出す基準電圧発生回路からの出力値と
を比較する比較回路と、当該比較回路からの出力をＰＷ
Ｍ発信させるＰＷＭ発振回路と、当該ＰＷＭ発振回路の
出力により前記トランジスタを駆動するドライブ回路と
から構成されたことを特徴とする力率改善回路とする。According to the present invention, there is provided a power factor improving circuit for boosting and smoothing an output voltage by using a choke coil, a transistor, and a PWM control circuit. In the above, the PWM control circuit detects a peak voltage at a stage preceding the choke coil, and a subtraction which detects a smoothed voltage at a stage subsequent to the choke coil and compares this voltage value with an output value of the peak voltage detection circuit. A comparison circuit for comparing an output value from the subtraction circuit with an output value from a reference voltage generation circuit for generating a reference voltage;
A power factor improving circuit comprising a PWM oscillation circuit for transmitting M and a drive circuit for driving the transistor by an output of the PWM oscillation circuit.
【０００７】[0007]
【実施例】本発明の力率改善回路を図１に示す。図１に
おいて、交流電源E1に整流器が接続され、この後段に整
流器DSからの出力電圧を昇圧するチョークコイルL1とト
ランジスタQ1、ダイオードD1、平滑用コンデンサC1が設
けられている。また、前記チョークコイルL1の前後段に
はＰＷＭ制御回路が備えられている。このＰＷＭ制御回
路は、整流器DSとチョークコイルL1との間の電圧を検出
するピーク電圧検出回路10と、チョークコイルL1の後段
の電圧を検出しこの電圧値と前記ピーク電圧検出回路10
からの電圧値とを比較し差異をとる減算回路20と、常に
一定の基準電圧を作り出す基準電圧発生回路40と、前記
減算回路20と基準電圧発生回路40とを比較する比較回路
30と、この比較回路30からの出力をＰＷＭ発振させるＰ
ＷＭ発振回路50と、このＰＷＭ発振回路50からの信号に
よりトランジスタQ1を駆動する信号を作り出すドライブ
回路60と、から構成されている。なお図１中の交流電源
E1と整流器DS、チョークコイルL1、トランジスタQ1、ダ
イオードD1、コンデンサC1は従来の技術で述べた図２の
ものと同一もしくは相当分を示している。1 shows a power factor improving circuit according to the present invention. In FIG. 1, a rectifier is connected to an AC power supply E1, and a choke coil L1 for boosting an output voltage from the rectifier DS, a transistor Q1, a diode D1, and a smoothing capacitor C1 are provided at a subsequent stage. A PWM control circuit is provided before and after the choke coil L1. The PWM control circuit includes a peak voltage detecting circuit 10 for detecting a voltage between the rectifier DS and the choke coil L1, and a voltage at a subsequent stage of the choke coil L1 for detecting the voltage value and the peak voltage detecting circuit 10.
A subtraction circuit 20 that compares the voltage value with the reference voltage value, a reference voltage generation circuit 40 that always generates a constant reference voltage, and a comparison circuit that compares the subtraction circuit 20 with the reference voltage generation circuit 40.
30 and P which causes the output from the comparison circuit 30 to perform PWM oscillation.
It comprises a WM oscillating circuit 50 and a drive circuit 60 for generating a signal for driving the transistor Q1 by a signal from the PWM oscillating circuit 50. The AC power supply in FIG.
E1 and rectifier DS, choke coil L1, transistor Q1, diode D1, and capacitor C1 are the same as or equivalent to those of FIG. 2 described in the related art.
【０００８】前記ピーク電圧検出回路10は、整流器DSか
らの出力電圧Viを分圧する分圧抵抗R4とR5と、演算増幅
器IC1、ダイオードD2、コンデンサC2、他の抵抗R3、R
6、R7とから構成され、整流器DSからの出力電圧Viのピ
ーク値を維持（ホールド）している。減算回路20は、チ
ョークコイルL1の後段（平滑後）の電圧を検出する分圧
抵抗R1とR2と、これら分圧抵抗からの出力値と前記ピー
ク電圧検出回路10からの出力とを比較する演算増幅器IC
2と、他の抵抗R8とR9とから構成されている。比較回路3
0は、基準電圧発生回路40から得られる基準となる電圧
と、前記減算回路20からの出力値とを比較する演算増幅
器IC3とから構成され、この出力がIC3と鋸波発生回路と
で構成されるＰＷＭ発振回路50を介してドライブ回路60
に接続されている。The peak voltage detecting circuit 10 includes voltage dividing resistors R4 and R5 for dividing the output voltage Vi from the rectifier DS, an operational amplifier IC1, a diode D2, a capacitor C2, and other resistors R3 and R3.
6, R7, and maintain (hold) the peak value of the output voltage Vi from the rectifier DS. The subtraction circuit 20 calculates the voltage dividing resistors R1 and R2 for detecting the voltage at the subsequent stage (after smoothing) of the choke coil L1, and compares the output value from these voltage dividing resistors with the output from the peak voltage detecting circuit 10. Amplifier IC
2 and other resistors R8 and R9. Comparison circuit 3
0 is composed of a reference voltage obtained from the reference voltage generation circuit 40 and an operational amplifier IC3 for comparing the output value from the subtraction circuit 20, and this output is composed of IC3 and a sawtooth wave generation circuit. Drive circuit 60 via a PWM oscillation circuit 50
It is connected to the.
【０００９】以下に本願発明の動作を説明する。交流電
源E1からの電圧は整流器DSにより整流された後に分圧抵
抗R4とR5により分圧され、演算増幅器IC1とダイオードD
2、コンデンサC2によりピーク電圧を検出し、ホールド
する。ここで得られるピーク電圧V'pの値は、交流電源E
1のピーク電圧に比例したものとなる。ここで当該ピー
ク電圧V'pをピーク基準電圧として減算回路20へ出力し
減算処理され、この結果が比較回路30に出力され、基準
電圧発生回路40の電圧と比較されるが、このときの基準
電圧発生回路40の値をEとすれば、最終出力電圧Vo、入
力電圧Viの√2倍となるピーク入力電圧VP、分圧抵抗R1
とR2、R4、R5、R6、R7、R8、R9との関係は、次の「数
１」と「数２」のような式で表される。The operation of the present invention will be described below. The voltage from the AC power supply E1 is rectified by the rectifier DS and then divided by the voltage dividing resistors R4 and R5, and the operational amplifier IC1 and the diode D
2. Detect and hold the peak voltage with the capacitor C2. The value of the peak voltage V'p obtained here is
1 is proportional to the peak voltage. Here, the peak voltage V′p is output as a peak reference voltage to the subtraction circuit 20 and subjected to subtraction processing, and the result is output to the comparison circuit 30 and compared with the voltage of the reference voltage generation circuit 40. Assuming that the value of the voltage generation circuit 40 is E, the final output voltage Vo, the peak input voltage VP which is √2 times the input voltage Vi, and the voltage dividing resistor R1
And R2, R4, R5, R6, R7, R8, and R9 are represented by the following equations (Formula 1) and (Formula 2).
【数１】 (Equation 1)
【数２】 (Equation 2)
【００１０】また、昇圧電圧を一定となるように制御を
行うと、入力電圧Viと最終出力電圧Voとの関係は、次の
「数３」のような式で表される。When the boost voltage is controlled to be constant, the relationship between the input voltage Vi and the final output voltage Vo is expressed by the following equation (3).
【数３】 (Equation 3)
【００１１】以上の「数１」と「数２」、「数３」より
分圧抵抗R1とR2、R4、R5、R6、R7、R8、R9とは、次の
「数４」のような関係になる。From the above "Equation 1", "Equation 2" and "Equation 3", the voltage dividing resistors R1 and R2, R4, R5, R6, R7, R8 and R9 are represented by the following "Equation 4". Become a relationship.
【数４】 (Equation 4)
【００１２】本発明は以上のような関係を保つことで力
率改善回路を構成している。The present invention constitutes a power factor improving circuit by maintaining the above relation.
【００１３】[0013]
【発明の効果】上記構成によりVo−√2Viが一定で、そ
の差を小さくすることで、後段の素子耐圧を従来通りと
することが可能になる。また、入力電圧Viの変動特性に
おいては、従来のコンデンサインプット型と同等以上の
性能が得られる。さらに、チョークコイルL1やトランジ
スタQ1への負担が軽減されるために小型化、且つ低損失
化が実現できる。According to the above configuration, Vo-√2Vi is constant, and by reducing the difference, the breakdown voltage of the subsequent stage can be made the same as before. Further, in the fluctuation characteristics of the input voltage Vi, performance equal to or higher than that of the conventional capacitor input type can be obtained. Further, since the load on the choke coil L1 and the transistor Q1 is reduced, the size and the loss can be reduced.
【図１】本発明の力率改善回路を示す。FIG. 1 shows a power factor correction circuit of the present invention.
【図２】従来の力率改善回路を示す。FIG. 2 shows a conventional power factor correction circuit.
図において同一符号は同一、または相当部分を示す。 E1 交流電源 DS 整流器 L1 チョークコイル Q1 トランジスタ D1 ダイオード C1 コンデンサ 10 ピーク電圧検出回路 20 減算回路 30 比較回路 40 基準電圧発生回路 50 ＰＷＭ発信回路 60 ドライブ回路 In the drawings, the same reference numerals indicate the same or corresponding parts. E1 AC power supply DS rectifier L1 choke coil Q1 transistor D1 diode C1 capacitor 10 peak voltage detection circuit 20 subtraction circuit 30 comparison circuit 40 reference voltage generation circuit 50 PWM transmission circuit 60 drive circuit
Claims (1)
トランジスタ、ＰＷＭ制御回路を使用して出力電圧を昇
圧、平滑する力率改善回路において、 前記ＰＷＭ制御回路が、チョークコイルの前段のピーク
電圧を検出するピーク電圧検出回路と、チョークコイル
後段の平滑電圧を検出しこの電圧値と前記ピーク電圧検
出回路の出力値とを比較する減算回路と、基準電圧を作
り出す基準電圧発生回路と、前記減算回路からの出力値
と当該基準電圧発生回路からの出力値とを比較する比較
回路と、当該比較回路からの出力をＰＷＭ発信させるＰ
ＷＭ発振回路と、当該ＰＷＭ発振回路の出力により前記
トランジスタを駆動するドライブ回路とから構成された
ことを特徴とする力率改善回路。An AC power supply is used as a power supply, and a choke coil is provided.
A power factor improving circuit for boosting and smoothing an output voltage using a transistor and a PWM control circuit, wherein the PWM control circuit detects a peak voltage at a stage preceding the choke coil, and a smoothed voltage at a stage subsequent to the choke coil. And a subtraction circuit for detecting this voltage value and comparing the output value of the peak voltage detection circuit with a reference voltage generation circuit for producing a reference voltage; an output value from the subtraction circuit and an output value from the reference voltage generation circuit And a P that causes the output from the comparison circuit to be transmitted by PWM.
A power factor improving circuit, comprising: a WM oscillation circuit; and a drive circuit that drives the transistor by an output of the PWM oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8206604A JP3007934B2 (en) | 1996-07-16 | 1996-07-16 | Power factor improvement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8206604A JP3007934B2 (en) | 1996-07-16 | 1996-07-16 | Power factor improvement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1032977A true JPH1032977A (en) | 1998-02-03 |
| JP3007934B2 JP3007934B2 (en) | 2000-02-14 |
Family
ID=16526147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8206604A Expired - Lifetime JP3007934B2 (en) | 1996-07-16 | 1996-07-16 | Power factor improvement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3007934B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1221759A2 (en) * | 2001-01-09 | 2002-07-10 | Nec Corporation | DC/DC converter and self-luminous display apparatus |
| JP2003009534A (en) * | 2001-06-25 | 2003-01-10 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
| KR100376531B1 (en) * | 1998-11-09 | 2003-05-17 | 주식회사 포스코 | A apparatus and method for rectifing in semibridge type |
| US7151360B2 (en) | 2003-07-18 | 2006-12-19 | Lg Electronics Inc. | Power supply for power factor correction and driving method thereof |
| JP2008253043A (en) * | 2007-03-30 | 2008-10-16 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
| WO2009145763A1 (en) * | 2008-05-28 | 2009-12-03 | Hewlett-Packard Development Company, L.P. | Impedance correction |
| JP2021530189A (en) * | 2018-06-28 | 2021-11-04 | テキサス インスツルメンツ インコーポレイテッド | Peak detection methods, devices, and circuits |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515966A (en) * | 2013-08-21 | 2014-01-15 | 安徽国科电力设备有限公司 | Base building type control system and method of direct voltage |
-
1996
- 1996-07-16 JP JP8206604A patent/JP3007934B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100376531B1 (en) * | 1998-11-09 | 2003-05-17 | 주식회사 포스코 | A apparatus and method for rectifing in semibridge type |
| EP1221759A2 (en) * | 2001-01-09 | 2002-07-10 | Nec Corporation | DC/DC converter and self-luminous display apparatus |
| EP1221759A3 (en) * | 2001-01-09 | 2002-11-13 | Nec Corporation | DC/DC converter and self-luminous display apparatus |
| US6541920B2 (en) | 2001-01-09 | 2003-04-01 | Nec Corporation | DC/DC converter and self-luminous display apparatus |
| JP2003009534A (en) * | 2001-06-25 | 2003-01-10 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
| US7151360B2 (en) | 2003-07-18 | 2006-12-19 | Lg Electronics Inc. | Power supply for power factor correction and driving method thereof |
| JP2008253043A (en) * | 2007-03-30 | 2008-10-16 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
| WO2009145763A1 (en) * | 2008-05-28 | 2009-12-03 | Hewlett-Packard Development Company, L.P. | Impedance correction |
| US8797017B2 (en) | 2008-05-28 | 2014-08-05 | Hewlett-Packard Development Company, L.P. | Impedance Stabilization |
| JP2021530189A (en) * | 2018-06-28 | 2021-11-04 | テキサス インスツルメンツ インコーポレイテッド | Peak detection methods, devices, and circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3007934B2 (en) | 2000-02-14 |
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