JPH1032371A - Composite circuit board and its manufacture - Google Patents
Composite circuit board and its manufactureInfo
- Publication number
- JPH1032371A JPH1032371A JP5528997A JP5528997A JPH1032371A JP H1032371 A JPH1032371 A JP H1032371A JP 5528997 A JP5528997 A JP 5528997A JP 5528997 A JP5528997 A JP 5528997A JP H1032371 A JPH1032371 A JP H1032371A
- Authority
- JP
- Japan
- Prior art keywords
- thick
- circuit pattern
- insulating substrate
- thin
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁基板上に小電
流用（信号用）の回路パターンと大電流用の回路パター
ンを有する複合回路基板と、その製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite circuit board having a circuit pattern for a small current (for a signal) and a circuit pattern for a large current on an insulating substrate, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】絶縁基板上に小電流用回路パターンと大
電流用回路パターンを形成する場合には、当然のことな
がら、大電流用回路パターンの導体断面積を小電流用回
路パターンより大きくする必要がある。その手段として
は二通りの方法がある。一つの方法は、小電流用回路パ
ターンと大電流用回路パターンの銅箔の厚さを同じと
し、大電流用回路パターンの幅を広くする方法である。
もう一つの方法は、大電流用回路パターンの厚さを小電
流用回路パターンより厚くする方法である（特開平６−
２６８３５５号公報、特開平６−３３４３１１号公
報）。2. Description of the Related Art When a circuit pattern for a small current and a circuit pattern for a large current are formed on an insulating substrate, the conductor cross section of the circuit pattern for the large current is naturally made larger than the circuit pattern for the small current. There is a need. There are two ways to do this. One method is to increase the width of the large current circuit pattern by making the thickness of the copper foil of the small current circuit pattern and the large current circuit pattern the same.
Another method is to make the thickness of the large current circuit pattern thicker than that of the small current circuit pattern.
268355, JP-A-6-334411).
【０００３】[0003]
【発明が解決しようとする課題】しかし厚さを同じにし
て大電流用回路パターンの幅を広くする方法では、汎用
の比較的薄い銅箔（厚さ３５〜７０μｍ）を使用した場
合には、大電流用パターンの幅が広くなり、複合回路基
板が大型化するという問題がある。また比較的厚い銅箔
を使用した場合には、小電流用の微細回路パターンが形
成しにくくなるという問題がある。However, in the method of increasing the width of the circuit pattern for large current by making the thickness the same, when a general-purpose relatively thin copper foil (thickness: 35 to 70 μm) is used, There is a problem that the width of the pattern for large current becomes wide and the size of the composite circuit board becomes large. Further, when a relatively thick copper foil is used, there is a problem that it is difficult to form a fine circuit pattern for a small current.
【０００４】一方、大電流用回路パターンの厚さを厚く
する方法では、小電流用回路パターンの表面と大電流用
回路パターンの表面に段差ができる（絶縁基板表面から
の高さが小電流用回路パターンより大電流用回路パター
ンの方が高くなる）ため、次のような問題がある。すな
わち、複合回路基板の場合も、回路パターンを形成した
あとに、ソルダーレジスト形成やシルク印刷が必要であ
るが、このときに小電流用の薄肉回路パターンと大電流
用の厚肉回路パターンの段差がこれらの作業に悪影響を
及ぼす。On the other hand, in the method of increasing the thickness of the circuit pattern for large current, a step is formed between the surface of the circuit pattern for small current and the surface of the circuit pattern for large current (the height from the surface of the insulating substrate is small). Since the circuit pattern for large current is higher than the circuit pattern), there is the following problem. That is, in the case of a composite circuit board as well, after forming a circuit pattern, it is necessary to form a solder resist or to perform silk printing. At this time, a step between a thin circuit pattern for a small current and a thick circuit pattern for a large current is required. Adversely affect these tasks.
【０００５】例えば、液状のソルダーレジストインクを
印刷またはカーテンコートし、露光、現像してソルダー
レジストパターンを形成する場合、段差部分への気泡の
巻き込みが発生しやすく、かつ厚肉回路パターンの角部
分の厚さが極端に薄くなるという問題があった。またシ
ルク印刷時には、段差のある面にインクを印刷すること
になるため、段差部分で文字のかすれ、にじみ等が発生
し、商品価値が低下するだけでなく、小さな文字の印刷
が不可能になったり、最悪の場合は文字の判読ができな
い等の問題が生じる。For example, when a solder resist pattern is formed by printing or curtain-coating a liquid solder resist ink and exposing and developing the solder resist pattern, air bubbles are liable to be trapped in the step portion and the corner portion of the thick circuit pattern is formed. There is a problem that the thickness of the substrate becomes extremely thin. In addition, during silk printing, ink is printed on the stepped surface, so characters may be blurred or blurred at the stepped parts, which not only reduces product value but also makes it impossible to print small characters. In the worst case, characters may not be legible.
【０００６】また回路パターン表面の段差による弊害は
部品実装時にも発生する。近年では装置の小型化、高速
化などから表面実装部品を使用する場合が多いが、表面
実装部品を回路基板に実装するためには、回路基板のパ
ッドにクリームはんだを印刷する必要がある。クリーム
はんだの印刷は、パッドに相当する位置に穴をあけたメ
タルマスクを回路基板上に載せ、その上からスキージで
クリームはんだを塗り付けることにより行うが、回路パ
ターン表面に段差があると、クリームはんだの印刷量
（塗布量）を調整できないだけでなく、最悪の場合クリ
ームはんだが印刷できない場合もある。[0006] Further, adverse effects due to steps on the surface of the circuit pattern also occur during component mounting. In recent years, surface mount components are often used in order to reduce the size and speed of the device. However, in order to mount the surface mount components on a circuit board, it is necessary to print cream solder on pads of the circuit board. Cream solder printing is performed by placing a metal mask with a hole in the position corresponding to the pad on the circuit board and applying cream solder with a squeegee from above, but if there is a step on the circuit pattern surface, the cream solder Not only cannot adjust the printing amount (coating amount), but in the worst case, cream solder cannot be printed.
【０００７】本発明の目的は、以上のような問題点に鑑
み、絶縁基板上に小電流用の薄肉回路パターンと大電流
用の厚肉回路パターンとを有していて、薄肉回路パター
ンと厚肉回路パターンの表面に実質的に段差のない複合
回路基板と、そのような複合回路基板を製造する方法を
提供することにある。In view of the above problems, an object of the present invention is to provide a thin circuit pattern for a small current and a thick circuit pattern for a large current on an insulating substrate. It is an object of the present invention to provide a composite circuit board having substantially no level difference on the surface of a thick circuit pattern and a method for manufacturing such a composite circuit board.
【０００８】[0008]
【課題を解決するための手段】この目的を達成する本発
明の複合回路基板は、絶縁基板上に小電流用の薄肉回路
パターンと大電流用の厚肉回路パターンとを有してお
り、前記薄肉回路パターンはその厚さ分が絶縁基板の表
面から突出しており、前記厚肉回路パターンはその厚さ
のうち実質的に薄肉回路パターンの厚さに相当する分が
絶縁基板の表面から突出し、残る厚さ分が絶縁基板に埋
め込まれていることを特徴とするものである。このよう
な構成にすれば、薄肉回路パターンの表面と厚肉回路パ
ターンの表面が実質的に同レベルに位置するようにな
り、従来の問題が解消できる。前記厚肉回路パターンの
絶縁基板から突出した部分は、薄肉回路パターンと同一
材料で形成されていることが望ましい。このようにする
と、当該複合回路基板を後述のように容易かつ安価に生
産できる。A composite circuit board according to the present invention that achieves this object has a thin circuit pattern for a small current and a thick circuit pattern for a large current on an insulating substrate. The thin circuit pattern has its thickness protruding from the surface of the insulating substrate, and the thick circuit pattern has a thickness corresponding to the thickness of the thin circuit pattern substantially protruding from the surface of the insulating substrate, The remaining thickness is embedded in the insulating substrate. With such a configuration, the surface of the thin circuit pattern and the surface of the thick circuit pattern are positioned at substantially the same level, and the conventional problem can be solved. The portion of the thick circuit pattern protruding from the insulating substrate is preferably formed of the same material as the thin circuit pattern. In this case, the composite circuit board can be easily and inexpensively produced as described later.
【０００９】このような複合回路基板は次のようにして
製造することができる。すなわち本発明の複合回路基板
の製造方法は、支持板に薄肉金属箔を張り付ける工程、
薄肉金属箔上に得ようとする厚肉回路パターンに対応し
たパターンの増肉導体層を形成する工程、増肉導体層を
形成した側の面に絶縁基板を設ける工程、前記支持板を
除去して、増肉導体層が絶縁基板に埋め込まれ、薄肉金
属箔が表面に積層された積層板を得る工程、その積層板
の薄肉金属箔をパターンエッチングして、前記増肉導体
層のない領域に薄肉回路パターンを形成すると共に、増
肉導体層に沿って厚肉回路パターンを形成する工程、を
含むことを特徴とする。Such a composite circuit board can be manufactured as follows. That is, the method of manufacturing a composite circuit board of the present invention includes a step of attaching a thin metal foil to the support plate,
A step of forming a thickened conductor layer having a pattern corresponding to the thick circuit pattern to be obtained on the thin metal foil, a step of providing an insulating substrate on the surface on which the thickened conductor layer is formed, and removing the support plate A step of obtaining a laminated board in which the thickened conductor layer is embedded in the insulating substrate and the thin metal foil is laminated on the surface, pattern-etching the thin metal foil of the laminated board to an area without the thickened conductor layer Forming a thin circuit pattern and forming a thick circuit pattern along the thickened conductor layer.
【００１０】この製造方法において、増肉導体層の形成
は、打ち抜き又は切り抜き加工で作製された金属バーの
半田付け、厚めっき、導電ペースト印刷焼成、金属溶射
などにより行うことができるが、生産性、電気的な信頼
性の面からは厚めっきによる方法が好適である。また前
記金属溶射、導電ペースト印刷焼成による場合は、それ
らの表面に凹凸が多いことから、絶縁基板に対する固定
強度の向上を期待できる。In this manufacturing method, the thickened conductor layer can be formed by soldering, thick plating, conductive paste printing, metal spraying, or the like of a metal bar formed by punching or cutting. From the viewpoint of electrical reliability, a method using thick plating is preferable. Further, in the case of the metal spraying and the printing and firing of the conductive paste, since the surface thereof has many irregularities, an improvement in fixing strength to the insulating substrate can be expected.
【００１１】厚めっきによる場合は、本発明の製造方法
は、支持板に薄肉金属箔を張り付ける工程、薄肉金属箔
上に得ようとする厚肉回路パターンに対応するパターン
が残るようにめっきレジストを形成する工程、薄肉金属
箔を電極として電解めっきを行い、めっきレジストで覆
われていない領域に厚めっき層を形成する工程、めっき
レジストを除去する工程、厚めっき層を形成した側の面
にプリプレグを積層し、加熱加圧して、絶縁基板を形成
する工程、前記支持板を除去して、厚めっき層が絶縁基
板に埋め込まれ、薄肉金属箔が表面に積層された積層板
を得る工程、その積層板の薄肉金属箔をパターンエッチ
ングして、前記厚めっき層のない領域に薄肉回路パター
ンを形成すると共に、厚めっき層に沿って厚肉回路パタ
ーンを形成する工程、を含むことを特徴とする。In the case of thick plating, the manufacturing method of the present invention comprises a step of attaching a thin metal foil to a support plate, and a plating resist so that a pattern corresponding to a thick circuit pattern to be obtained on the thin metal foil remains. Forming a thick plating layer in an area that is not covered with a plating resist, performing a plating process using a thin metal foil as an electrode, removing the plating resist, and forming a thick plating layer on the side on which the thick plating layer is formed. Laminating the prepreg, heating and pressing to form an insulating substrate, removing the support plate, embedding a thick plating layer in the insulating substrate, and obtaining a laminated plate in which a thin metal foil is laminated on the surface, The thin metal foil of the laminate is subjected to pattern etching to form a thin circuit pattern in a region where there is no thick plating layer, and to form a thick circuit pattern along the thick plating layer. , Characterized in that it comprises a.
【００１２】[0012]
〔実施形態１〕図１〜図１２は本発明の一実施形態を示
す。この実施形態は、図１２に示すように、絶縁基板１
３の両面に小電流用の薄肉回路パターン２３Ａ、２３Ｂ
と大電流用の厚肉回路パターン２５Ａ、２５Ｂを有する
複合回路基板を製造する例である。[Embodiment 1] FIGS. 1 to 12 show an embodiment of the present invention. In this embodiment, as shown in FIG.
3. Thin circuit patterns 23A and 23B for small current on both sides
This is an example of manufacturing a composite circuit board having thick circuit patterns 25A and 25B for a large current.
【００１３】まず図１に示すように、２枚の支持板１
Ａ、１Ｂを用意し、各々の片面に接着剤等により１オン
ス（公称厚さ３５μｍ）の汎用銅箔３Ａ、３Ｂを張り付
ける。支持板１Ａ、１Ｂにはステンレス板、又はアルミ
ニウム板又はベーク板等を用いることができる。First, as shown in FIG. 1, two support plates 1
A and 1B are prepared, and one-sided (35 μm nominal thickness) general-purpose copper foils 3A and 3B are attached to one side of each with an adhesive or the like. As the support plates 1A and 1B, a stainless plate, an aluminum plate, a bake plate, or the like can be used.
【００１４】次に図２に示すように、銅箔３Ａ、３Ｂ上
に、得ようとする厚肉回路パターンと逆のパターン（ミ
ラーパターン）が残るようにめっきレジスト５Ａ、５Ｂ
を形成する。めっきレジスト５Ａ、５Ｂは、銅箔３Ａ、
３Ｂ上にドライフィルムを張り付け、厚肉回路パターン
のミラーパターンを露光、現像することにより形成す
る。めっきレジスト５Ａ、５Ｂの厚さは、ドライフィル
ムの積層枚数により設定することができ、後に形成する
厚めっき層の厚さと同じかそれより厚くなるように設定
する。例えば銅箔３Ａ、３Ｂ上に厚さ１７５μｍの厚め
っき層を形成する場合には、厚さ５０μｍのドライフィ
ルムを４枚積層して、露光、現像すればよい。Next, as shown in FIG. 2, plating resists 5A, 5B are formed on copper foils 3A, 3B so that a pattern (mirror pattern) opposite to the thick circuit pattern to be obtained remains.
To form The plating resists 5A and 5B are copper foil 3A,
It is formed by attaching a dry film on 3B and exposing and developing a mirror pattern of a thick circuit pattern. The thickness of the plating resists 5A and 5B can be set by the number of laminated dry films, and is set to be equal to or larger than the thickness of a thick plating layer to be formed later. For example, in the case of forming a thick plating layer having a thickness of 175 μm on the copper foils 3A and 3B, four dry films having a thickness of 50 μm may be laminated, exposed and developed.
【００１５】次に薄肉銅箔３Ａ、３Ｂを電極として電解
めっきを行い、めっきレジスト５Ａ、５Ｂで覆われてい
ない領域に、図３に示すように銅の厚めっき層７Ａ、７
Ｂを形成する。この例では厚めっき層７Ａ、７Ｂの厚さ
は１７５μｍである。その後、めっきレジスト５Ａ、５
Ｂを除去すると、図４に示すように、銅箔３Ａ、３Ｂ上
に得ようとする厚肉回路パターンに対応するパターンの
厚めっき層７Ａ、７Ｂが得られる。次に、積層時の位置
決めのため、厚めっき層７Ａ、７Ｂの位置を基準に、合
わせフィルムを使用してガイド穴（図示せず）を形成す
る。また位置合わせ用の基準マークを製品側にめっき時
に併せて形成し、これを座ぐり、Ｘ線等で検出し、ガイ
ド穴を形成してもよい。Next, electrolytic plating is performed using the thin copper foils 3A, 3B as electrodes, and the copper thick plating layers 7A, 7A are formed in the areas not covered with the plating resists 5A, 5B as shown in FIG.
Form B. In this example, the thickness of the thick plating layers 7A and 7B is 175 μm. Then, plating resists 5A, 5A
When B is removed, as shown in FIG. 4, thick plating layers 7A and 7B having a pattern corresponding to the thick circuit pattern to be obtained on copper foils 3A and 3B are obtained. Next, for positioning during lamination, guide holes (not shown) are formed using a laminated film with reference to the positions of the thick plating layers 7A and 7B. Further, a reference mark for alignment may be formed on the product side at the time of plating, and this may be spotted, detected by X-rays or the like, and a guide hole may be formed.
【００１６】次に図５に示すように、厚めっき層７Ａ、
７Ｂを形成した側の面を内側にして対向させ、その間に
厚さ２００μｍのプリプレグ９を６〜８枚挟んで積層す
る。積層するプリプレグのうち最上層と最下層のプリプ
レグには、厚めっき層７Ａ、７Ｂが入る穴１１を形成し
ておく。これは積層時に銅箔３Ａ、３Ｂにしわが発生す
るのを防止するためである。Next, as shown in FIG. 5, the thick plating layer 7A,
The prepregs 9 having a thickness of 200 μm are sandwiched and laminated between the prepregs 9 with the surface on the side where 7B is formed facing inward. Holes 11 for receiving the thick plating layers 7A and 7B are formed in the uppermost and lowermost prepregs among the prepregs to be laminated. This is to prevent the copper foils 3A and 3B from wrinkling during lamination.
【００１７】なお、銅箔３Ａ、３Ｂおよび厚めっき層７
Ａ、７Ｂの表面には、プリプレグ９との接着性を向上さ
せるため、積層前に黒化処理などの粗面化処理を施して
おくことが好ましい。The copper foils 3A and 3B and the thick plating layer 7
The surfaces of A and 7B are preferably subjected to a surface roughening treatment such as a blackening treatment before lamination in order to improve the adhesion to the prepreg 9.
【００１８】また銅箔３Ａ、３Ｂとして、１オンス（公
称厚さ３５μｍ）以上のものを使用し、積層時にしわが
発生しなければ、最上層、最下層のプリプレグに穴１１
を形成する必要はない。銅箔３Ａ、３Ｂの厚さは、実装
する部品や、回路パターンの配線密度、小電流用回路パ
ターンの電流値などにより選択すればよい。実際には、
微細パターンの要求を満足する厚さで、積層時にしわが
発生しない厚さという点から３５〜７０μｍ程度の厚さ
の汎用銅箔を使用することが望ましい。Further, copper foils 3A and 3B each having a thickness of 1 ounce (nominal thickness 35 μm) or more are used. If wrinkles do not occur during lamination, holes 11 are formed in the prepregs of the uppermost and lowermost layers.
Need not be formed. The thickness of the copper foils 3A and 3B may be selected according to the components to be mounted, the wiring density of the circuit pattern, the current value of the small current circuit pattern, and the like. actually,
It is desirable to use a general-purpose copper foil having a thickness that satisfies the requirements of the fine pattern and that has a thickness of about 35 to 70 μm from the viewpoint that wrinkles do not occur during lamination.
【００１９】次に、図５のように積層したものをホット
プレスで加熱加圧して、図６に示すように絶縁基板１３
を形成すると共に、絶縁基板１３と銅箔３Ａ、３Ｂ、厚
めっき層７Ａ、７Ｂを一体化する。このあと支持板１
Ａ、１Ｂを除去すると図７のようになる。すなわち、厚
めっき層７Ａ、７Ｂが絶縁基板１３の肉厚の中に埋め込
まれ、銅箔３Ａ、３Ｂが表面に積層された銅張り積層板
が得られる。なお支持板１Ａ、１Ｂの除去を容易にする
には、支持板１Ａ、１Ｂに銅箔３Ａ、３Ｂを張り付ける
ときに、加熱すると接着力が低下するタイプの接着剤
（例えば熱硬化性樹脂が配合された接着剤）を用いると
よい。そうすると、図５の積層体を加熱加圧するときの
熱で、支持板１Ａ、１Ｂと銅箔３Ａ、３Ｂとの接着力が
低下するので、支持板１Ａ、１Ｂを容易に剥がすことが
できる。また支持板１Ａ、１Ｂを除去するためには、接
着力の弱い接着剤を使用すること、溶剤で除去できる接
着剤を使用すること等も考えられる。Next, the laminate as shown in FIG. 5 is heated and pressed by a hot press, and as shown in FIG.
And the insulating substrate 13 is integrated with the copper foils 3A and 3B and the thick plating layers 7A and 7B. After this, support plate 1
FIG. 7 shows the result of removing A and 1B. That is, a copper-clad laminate in which the thick plating layers 7A and 7B are embedded in the thickness of the insulating substrate 13 and the copper foils 3A and 3B are laminated on the surface is obtained. In order to facilitate the removal of the support plates 1A and 1B, a type of adhesive (for example, a thermosetting resin which reduces the adhesive strength when heated when the copper foils 3A and 3B are attached to the support plates 1A and 1B). It is preferable to use a blended adhesive). Then, since the adhesive force between the support plates 1A and 1B and the copper foils 3A and 3B is reduced by the heat when the laminate of FIG. 5 is heated and pressed, the support plates 1A and 1B can be easily peeled off. Further, in order to remove the support plates 1A and 1B, it is conceivable to use an adhesive having a low adhesive strength, or to use an adhesive which can be removed with a solvent.
【００２０】これ以降の工程は通常の回路基板の製造工
程と同様である。すなわち図８のように所定の位置にス
ルーホール用の貫通孔１５、１７を形成した後、貫通孔
１５、１７の内面に図９のように銅めっき層１９を設け
て、スルーホールを形成する。この銅めっき層１９は銅
箔３Ａ、３Ｂの表面にも形成される。次に両面にドライ
フィルムを張り付けてパターン露光、現像を行い、図１
０に示すように薄肉回路パターン（小電流用）と厚肉回
路パターン（大電流用）に対応するパターンのエッチン
グレジスト２１を形成する。このあとエッチングをする
と図１１のように銅箔３Ａ、３Ｂの不要な部分が除去さ
れる。これにより厚めっき層７Ａ、７Ｂのない領域に薄
肉回路パターンが形成されると共に、厚めっき層７Ａ、
７Ｂに沿って厚肉回路パターンが形成される。次にエッ
チングレジスト２１を除去すると、図１２のような複合
回路基板が得られる。The subsequent steps are the same as the ordinary circuit board manufacturing steps. That is, after forming through holes 15 and 17 for through holes at predetermined positions as shown in FIG. 8, a copper plating layer 19 is provided on the inner surfaces of the through holes 15 and 17 as shown in FIG. 9 to form through holes. . This copper plating layer 19 is also formed on the surfaces of the copper foils 3A and 3B. Next, a dry film is attached to both sides and pattern exposure and development are performed.
As shown in FIG. 0, an etching resist 21 having a pattern corresponding to the thin circuit pattern (for small current) and the thick circuit pattern (for large current) is formed. When etching is performed thereafter, unnecessary portions of the copper foils 3A and 3B are removed as shown in FIG. As a result, a thin circuit pattern is formed in a region without the thick plating layers 7A and 7B, and the thick plating layers 7A and 7B are formed.
A thick circuit pattern is formed along 7B. Next, when the etching resist 21 is removed, a composite circuit board as shown in FIG. 12 is obtained.
【００２１】この複合回路基板は、絶縁基板１３の両面
に小電流用の薄肉回路パターン２３Ａ、２３Ｂと大電流
用の厚肉回路パターン２５Ａ、２５Ｂを有している。薄
肉回路パターン２３Ａ、２３Ｂの厚さは図１２からも明
らかなように銅箔３Ａ、３Ｂにそれぞれ銅めっき層１９
がプラスされた厚さである。また厚肉回路パターン２５
Ａ、２５Ｂの厚さは銅箔３Ａ、３Ｂにそれぞれ厚めっき
層７Ａ、７Ｂと銅めっき層１９がプラスされた厚さであ
る。薄肉回路パターン２３Ａ、２３Ｂはその厚さ分が絶
縁基板１３の表面から突出している。厚肉回路パターン
２５Ａ、２５Ｂは全厚さのうち薄肉回路パターン２３
Ａ、２３Ｂと同じ厚さ分が絶縁基板１３の表面から突出
し、残る厚さ分が絶縁基板１３に埋め込まれた状態とな
っている。これにより薄肉回路パターン２３Ａ、２３Ｂ
の表面と厚肉回路パターン２５Ａ、２５Ｂの表面が同レ
ベルに位置することになる。この複合回路基板では、厚
肉回路パターンの部分のうち絶縁基板１３から突出して
いる部分の厚さ方向の材料構成が薄肉回路パターンの厚
さ方向の材料構成と同一である。This composite circuit board has thin circuit patterns 23A and 23B for small current and thick circuit patterns 25A and 25B for large current on both sides of the insulating substrate 13. As can be seen from FIG. 12, the thickness of the thin circuit patterns 23A and 23B is the copper plating layer 19 on the copper foils 3A and 3B, respectively.
Is the added thickness. Also, the thick circuit pattern 25
The thickness of A, 25B is a thickness obtained by adding thick plating layers 7A, 7B and copper plating layer 19 to copper foils 3A, 3B, respectively. The thicknesses of the thin circuit patterns 23A and 23B protrude from the surface of the insulating substrate 13. The thick circuit patterns 25A and 25B are the thin circuit patterns 23 of the total thickness.
The same thickness as A and 23B protrudes from the surface of the insulating substrate 13, and the remaining thickness is embedded in the insulating substrate 13. Thereby, the thin circuit patterns 23A and 23B
And the surfaces of the thick circuit patterns 25A and 25B are located at the same level. In this composite circuit board, the material composition in the thickness direction of the portion of the thick circuit pattern projecting from the insulating substrate 13 is the same as the material composition in the thickness direction of the thin circuit pattern.
【００２２】この複合回路基板には、このあと、ソルダ
ーレジストの形成、シルク文字の印刷、ノンスルーホー
ル穴加工、はんだレベラー等の表面処理、外形加工等が
施されるが、これらの工程では、絶縁基板の表面から突
出する回路パターンの厚さが通常の回路基板と同様に薄
く、かつ回路パターンの表面に段差がないため、通常の
設備を使用して容易に加工を行うことができる。The composite circuit board is then subjected to solder resist formation, silk character printing, non-through hole hole processing, surface treatment such as a solder leveler, external processing, etc. In these steps, Since the thickness of the circuit pattern protruding from the surface of the insulating substrate is as thin as that of a normal circuit board, and there is no step on the surface of the circuit pattern, the processing can be easily performed using ordinary equipment.
【００２３】〔実施形態２〕図１３〜図２４は本発明の
他の実施形態を示す。この実施形態は、図２４に示すよ
うに絶縁基板１３の両面に小電流用の薄肉回路パターン
２３Ａ、２３Ｂを有し、片面に大電流用の厚肉回路パタ
ーン２５を有する複合回路基板を製造する例である。[Embodiment 2] FIGS. 13 to 24 show another embodiment of the present invention. In this embodiment, as shown in FIG. 24, a composite circuit board having thin circuit patterns 23A and 23B for small current on both sides of an insulating substrate 13 and a thick circuit pattern 25 for large current on one side is manufactured. It is an example.
【００２４】まず図１３に示すように、１枚の支持板１
を用意し、その片面に接着剤等により１オンス（公称厚
さ３５μｍ）の汎用銅箔３Ａを張り付ける。支持板１の
材質は実施形態１と同じである。次に図１４に示すよう
に、銅箔３Ａ上に、得ようとする厚肉回路パターンに対
応するパターンが残るようにめっきレジスト５を形成す
る。めっきレジスト５の形成方法や厚さも実施形態１と
同じである。First, as shown in FIG.
Is prepared, and one-sided (nominal thickness 35 μm) general-purpose copper foil 3A is adhered to one surface thereof with an adhesive or the like. The material of the support plate 1 is the same as that of the first embodiment. Next, as shown in FIG. 14, a plating resist 5 is formed on the copper foil 3A so that a pattern corresponding to a thick circuit pattern to be obtained remains. The formation method and the thickness of the plating resist 5 are the same as those in the first embodiment.
【００２５】次に薄肉銅箔３Ａを電極として電解めっき
を行い、めっきレジスト５で覆われていない領域に、図
１５に示すように銅の厚めっき層７を形成する。この例
も厚めっき層７の厚さは１７５μｍである。その後、め
っきレジスト５を除去すると、図１６に示すように、銅
箔３Ａ上に得ようとする厚肉回路パターンに対応するパ
ターンの厚めっき層７が得られる。次に、積層時の位置
決めのためのガイド穴（図示せず）を形成する。Next, electrolytic plating is performed using the thin copper foil 3A as an electrode, and a thick copper plating layer 7 is formed in a region not covered with the plating resist 5, as shown in FIG. Also in this example, the thickness of the thick plating layer 7 is 175 μm. Thereafter, when the plating resist 5 is removed, as shown in FIG. 16, a thick plating layer 7 having a pattern corresponding to the thick circuit pattern to be obtained on the copper foil 3A is obtained. Next, guide holes (not shown) for positioning during lamination are formed.
【００２６】次に図１７に示すように、厚めっき層７を
形成した側の面と、別に用意した片面銅張り積層板２７
の絶縁基板２９側の面を対向させ、その間に厚さ２００
μｍのプリプレグ９を２〜３枚挟んで積層する。銅張り
積層板２７の銅箔３Ｂは銅箔３Ａと同じ厚さもしくは厚
さ７０μｍ以下の汎用銅箔である。なお、積層するプリ
プレグのうち銅箔３Ａ側に位置する１枚のプリプレグに
厚めっき層７が入る穴１１を形成すること、銅箔３Ａお
よび厚めっき層７の表面に黒化処理などを施すこと、銅
箔３Ａの好ましい厚さなどは実施形態１と同じである。Next, as shown in FIG. 17, the surface on which the thick plating layer 7 is formed is separated from the single-sided copper-clad laminate 27 prepared separately.
Faces on the insulating substrate 29 side, and a thickness of 200
Two or three μm prepregs 9 are sandwiched and laminated. The copper foil 3B of the copper-clad laminate 27 is a general-purpose copper foil having the same thickness as the copper foil 3A or a thickness of 70 μm or less. It is to be noted that, among the prepregs to be laminated, a hole 11 for receiving the thick plating layer 7 is formed in one prepreg located on the copper foil 3A side, and a blackening process or the like is performed on the surfaces of the copper foil 3A and the thick plating layer 7. The preferred thickness of the copper foil 3A is the same as that of the first embodiment.
【００２７】次に、図１７のように積層したものをホッ
トプレスで加熱加圧して、図１８に示すように絶縁基板
１３（絶縁基板２９とプリプレグ９が一体化されたも
の）を形成すると共に、絶縁基板１３と銅箔３Ａ、３
Ｂ、厚めっき層７とを一体化する。このあと支持板１を
除去すると図１９のようになる。すなわち、厚めっき層
７が絶縁基板１３の肉厚の中に埋め込まれ、銅箔３Ａ、
３Ｂが表面に積層された銅張り積層板が得られる。Next, the laminated structure as shown in FIG. 17 is heated and pressed by a hot press to form an insulating substrate 13 (integrated insulating substrate 29 and prepreg 9) as shown in FIG. , Insulating substrate 13 and copper foil 3A, 3
B, The thick plating layer 7 is integrated. After that, when the support plate 1 is removed, it becomes as shown in FIG. That is, the thick plating layer 7 is embedded in the thickness of the insulating substrate 13, and the copper foil 3A,
A copper-clad laminate having 3B laminated on the surface is obtained.
【００２８】これ以降の工程は実施形態１と同様であ
る。すなわち図２０のように所定の位置にスルーホール
用の孔１５、１７を形成した後、孔１５、１７の内面に
図２１に示すように銅めっき層１９を形成する。この銅
めっき層１９は銅箔３Ａ、３Ｂの表面にも形成される。
次に両面にドライフィルムを張り付けてパターン露光、
現像を行い、図２２に示すように薄肉回路パターン（小
電流用）と厚肉回路パターン（大電流用）に対応するパ
ターンのエッチングレジスト２１を形成する。このあと
エッチングをすると図２３のように銅箔３Ａ、３Ｂの不
要な部分が除去される。これにより厚めっき層７のない
領域に薄肉回路パターンが形成されると共に、厚めっき
層７に沿って厚肉回路パターンが形成される。次にエッ
チングレジスト２１を除去すると、図２４のような複合
回路基板が得られる。The subsequent steps are the same as in the first embodiment. That is, after forming holes 15 and 17 for through holes at predetermined positions as shown in FIG. 20, a copper plating layer 19 is formed on the inner surfaces of the holes 15 and 17 as shown in FIG. This copper plating layer 19 is also formed on the surfaces of the copper foils 3A and 3B.
Next, paste a dry film on both sides and pattern exposure,
Development is performed to form an etching resist 21 having a pattern corresponding to the thin circuit pattern (for small current) and the thick circuit pattern (for large current) as shown in FIG. When etching is performed thereafter, unnecessary portions of the copper foils 3A and 3B are removed as shown in FIG. Thus, a thin circuit pattern is formed in a region where the thick plating layer 7 is not formed, and a thick circuit pattern is formed along the thick plating layer 7. Next, when the etching resist 21 is removed, a composite circuit board as shown in FIG. 24 is obtained.
【００２９】すなわちこの複合回路基板は、絶縁基板１
３の両面に小電流用の薄肉回路パターン２３Ａ、２３Ｂ
を有し、片面に大電流用の厚肉回路パターン２５を有し
ている。薄肉回路パターン２３Ａ、２３Ｂの厚さは図２
４からも明らかなように銅箔３Ａ、３Ｂにそれぞれ銅め
っき層１９がプラスされた厚さである。また厚肉回路パ
ターン２５の厚さは銅箔３Ａに厚めっき層７と銅めっき
層１９がプラスされた厚さである。薄肉回路パターン２
３Ａ、２３Ｂはその厚さ分が絶縁基板１３の表面から突
出している。厚肉回路パターン２５はその厚さのうち薄
肉回路パターン２３Ａと同じ厚さ分が絶縁基板１３の表
面から突出し、残る厚さ分が絶縁基板１３に埋め込まれ
た状態となっている。これにより薄肉回路パターン２３
Ａの表面と厚肉回路パターン２５の表面が同レベルに位
置することになる。That is, the composite circuit board is composed of the insulating substrate 1
3. Thin circuit patterns 23A and 23B for small current on both sides
And a thick circuit pattern 25 for a large current on one side. The thickness of the thin circuit patterns 23A and 23B is shown in FIG.
As is clear from FIG. 4, the thickness is such that the copper plating layers 19 are added to the copper foils 3A and 3B, respectively. The thickness of the thick circuit pattern 25 is a thickness obtained by adding the thick plating layer 7 and the copper plating layer 19 to the copper foil 3A. Thin circuit pattern 2
3A and 23B project from the surface of the insulating substrate 13 by the thickness thereof. The thick circuit pattern 25 has the same thickness as that of the thin circuit pattern 23 </ b> A protruding from the surface of the insulating substrate 13, and the remaining thickness is embedded in the insulating substrate 13. Thereby, the thin circuit pattern 23 is formed.
The surface of A and the surface of thick circuit pattern 25 are located at the same level.
【００３０】この複合回路基板には、このあと、ソルダ
ーレジストの形成、シルク文字の印刷、ノンスルーホー
ル穴加工、はんだレベラー等の表面処理、外形加工等が
施されるが、これらの工程では、絶縁基板の表面から突
出する回路パターンの厚さが通常の回路基板と同様に薄
く、かつ回路パターンの表面に段差がないため、通常の
設備を使用して容易に加工を行うことができる。After that, the composite circuit board is subjected to solder resist formation, silk character printing, non-through-hole hole processing, surface treatment such as a solder leveler, outer shape processing, and the like. Since the thickness of the circuit pattern protruding from the surface of the insulating substrate is as thin as that of a normal circuit board, and there is no step on the surface of the circuit pattern, the processing can be easily performed using ordinary equipment.
【００３１】〔実施形態３〕ところで前述のように、厚
肉回路パターンの全厚さのうち薄肉回路パターンの厚さ
に相当する分が絶縁基板の表面から突出し、残る厚さ分
が絶縁基板に埋め込まれている構造の複合回路基板にお
いては、例えば図２５に示すように、厚肉回路パターン
２５Ａ、２５Ｂと絶縁基板１３との熱膨張係数の差など
により、厚肉回路パターン２５Ａと薄肉回路パターン２
３Ａがつながる部分に僅かではあるが段差Ｄが生じるこ
とがある。このような段差Ｄが生じると、その部分で薄
肉回路パターン２３Ａに応力がかかることになり、薄肉
回路パターン２３Ａの幅が狭い場合には信頼性の点で問
題がある。[Embodiment 3] As described above, of the total thickness of the thick circuit pattern, a portion corresponding to the thickness of the thin circuit pattern protrudes from the surface of the insulating substrate, and the remaining thickness corresponds to the thickness of the insulating substrate. In a composite circuit board having a buried structure, for example, as shown in FIG. 25, the thick circuit pattern 25A and the thin circuit pattern 25A and 25B and the thin circuit pattern are formed due to a difference in thermal expansion coefficient between the insulating substrate 13 and the like. 2
There may be a slight step D at the portion where 3A is connected. When such a step D occurs, stress is applied to the thin circuit pattern 23A at that portion, and there is a problem in reliability when the width of the thin circuit pattern 23A is narrow.
【００３２】このような問題を改善するため図２６に示
す複合回路基板は、薄肉回路パターン２３Ａ、２３Ｂが
厚肉回路パターン２５Ａ、２５Ｂにつながる部分Ｊで、
薄肉回路パターン２３Ａ、２３Ｂの幅を当該部分Ｊから
離れた部分Ｋより広くしたものである。この例では、つ
ながる部分Ｊが三角形状になっている。このようにする
と、薄肉回路パターン２３Ａ、２３Ｂが厚肉回路パター
ン２５Ａ、２５Ｂにつながる部分に僅かな段差が生じた
としても、その部分の薄肉回路パターン２３Ａ、２３Ｂ
は幅が広く、強度が高くなっているため、割れや破断が
発生するおそれが少なくなり、信頼性を保持することが
できる。In order to solve such a problem, the composite circuit board shown in FIG. 26 has a portion J where the thin circuit patterns 23A and 23B are connected to the thick circuit patterns 25A and 25B.
The width of the thin circuit patterns 23A and 23B is wider than the portion K remote from the portion J. In this example, the connecting portion J has a triangular shape. In this way, even if a slight step is generated in a portion where the thin circuit patterns 23A and 23B are connected to the thick circuit patterns 25A and 25B, the thin circuit patterns 23A and 23B
Since the width is wide and the strength is high, the risk of cracking or breaking is reduced, and the reliability can be maintained.
【００３３】〔実施形態４〕また前述のように、厚肉回
路パターンの全厚さのうち薄肉回路パターンの厚さに相
当する分が絶縁基板の表面から突出し、残る厚さ分が絶
縁基板に埋め込まれている構造の複合回路基板において
は、絶縁基板上の銅箔をエッチングするときのエッチン
グレジスト（図１０の符号２１）の印刷パターンが、既
に絶縁基板に埋め込まれている厚肉回路パターンからず
れることがある。このようなずれが発生すると、図２７
に示すように、絶縁基板１３上の銅箔をエッチングした
ときに、厚肉回路パターン２５Ａの絶縁基板１３に埋め
込まれている部分が一部エッチングされて溝Ｓが出来て
しまうという問題がある。これにより導体断面積が減少
するだけでなく、この溝Ｓに例えばシルク印刷の文字が
かかると文字のにじみやかすれが発生する。また溝Ｓに
ソルダーレジストの見切りがかかると見切り線が乱れて
しまう。[Embodiment 4] As described above, of the total thickness of the thick circuit pattern, a portion corresponding to the thickness of the thin circuit pattern protrudes from the surface of the insulating substrate, and the remaining thickness corresponds to the thickness of the insulating substrate. In the composite circuit board having the embedded structure, the print pattern of the etching resist (reference numeral 21 in FIG. 10) when etching the copper foil on the insulating substrate is changed from the thick circuit pattern already embedded in the insulating substrate. May shift. When such a shift occurs, FIG.
As shown in (1), when the copper foil on the insulating substrate 13 is etched, there is a problem that a portion of the thick circuit pattern 25A embedded in the insulating substrate 13 is partially etched to form a groove S. As a result, not only the conductor cross-sectional area is reduced, but also, for example, when characters of silk printing are applied to the grooves S, blurring or blurring of the characters occurs. Also, if the solder resist is cut off in the groove S, the parting line will be disturbed.
【００３４】上記のような問題を改善するため図２８に
示す複合回路基板は、厚肉回路パターン２５Ａ、２５Ｂ
の、絶縁基板１３の表面から突出する部分の幅を、絶縁
基板１３に埋め込まれている部分の幅より広くして、厚
肉回路パターン２５Ａ、２５Ｂの、絶縁基板１３の表面
から突出する部分の縁が、絶縁基板１３に埋め込まれて
いる部分の縁より外側に位置するようにしたものであ
る。In order to solve the above problems, the composite circuit board shown in FIG. 28 has thick circuit patterns 25A and 25B.
Of the portions of the thick circuit patterns 25A and 25B that protrude from the surface of the insulating substrate 13 by making the width of the portion protruding from the surface of the insulating substrate 13 wider than the width of the portion embedded in the insulating substrate 13. The edge is located outside the edge of the portion embedded in the insulating substrate 13.
【００３５】このようにすれば、エッチングレジストの
印刷パターンが多少ずれても、厚肉回路パターン２５
Ａ、２５Ｂの絶縁基板１３に埋め込まれている部分がエ
ッチングされることがなくなり、上記の問題を解消でき
る。またこの構造にすれば、前述の段差Ｄに基づく問題
も解消できる。前記図２６のつながり部分Ｊの補強構造
と組み合わせるとさらに効果は大きい。In this way, even if the printing pattern of the etching resist is slightly shifted, the thick circuit pattern 25
The portions embedded in the insulating substrate 13 of A and 25B are not etched, and the above problem can be solved. Further, with this structure, the problem based on the step D described above can be solved. When combined with the reinforcing structure of the connecting portion J shown in FIG. 26, the effect is even greater.
【００３６】〔その他の実施形態〕なお以上の実施形態
では電解めっきで形成した厚めっき層を増肉導体層とし
たが、増肉導体層は無電解めっきで形成してもよく、厚
肉回路パターンの厚さをさらに厚くしたい場合には、導
電ペーストや金属溶射により導体断面積を増やすことも
可能である。また打ち抜き又は切り抜き加工で別途作製
した金属バーを薄肉金属箔に半田付けして増肉導体層と
してもよい。本発明では、熱に弱い基材を積層する前
に、厚肉導体層を形成するため、高温での導電ペースト
の焼成や、プラズマ溶射等が可能である。[Other Embodiments] In the above embodiments, the thick plated layer formed by electrolytic plating was used as the thickened conductor layer. However, the thickened conductor layer may be formed by electroless plating. If it is desired to further increase the thickness of the pattern, the conductor cross-sectional area can be increased by conductive paste or metal spraying. Alternatively, a metal bar separately prepared by punching or cutting may be soldered to a thin metal foil to form a thickened conductor layer. In the present invention, since the thick conductor layer is formed before the heat-sensitive base material is laminated, firing of the conductive paste at a high temperature, plasma spraying, or the like can be performed.
【００３７】まためっきレジストは、エッチング液に耐
え、めっき厚さ以上に形成できれば、ドライフィルム以
外のものを使用することができる。また回路パターン形
成時のエッチングレジストに関してもドライフィルムに
制限されるものではなく、電着法、はんだ剥離法などを
使用してもよい。As the plating resist, a material other than a dry film can be used as long as it can withstand an etching solution and can be formed to have a plating thickness or more. Further, the etching resist for forming the circuit pattern is not limited to the dry film, and an electrodeposition method, a solder peeling method, or the like may be used.
【００３８】また本発明に係る複合回路基板は次のよう
な製造方法でも製造することができる。すなわち、厚肉
金属板をハーフエッチングすることにより厚肉回路パタ
ーンと薄肉金属箔を形成し、厚肉回路パターン側の面に
絶縁基板を形成した後、前記薄肉金属箔をパターンエッ
チングして、厚肉回路パターンのない領域に薄肉回路パ
ターンを形成するという方法である。The composite circuit board according to the present invention can also be manufactured by the following manufacturing method. That is, a thick circuit pattern and a thin metal foil are formed by half-etching a thick metal plate, an insulating substrate is formed on the surface on the side of the thick circuit pattern, and then the thin metal foil is pattern-etched, This is a method of forming a thin circuit pattern in a region having no thick circuit pattern.
【００３９】[0039]
【発明の効果】以上説明したように本発明によれば、小
電流用の薄肉回路パターンと大電流用の厚肉回路パター
ンの表面が同じレベルに位置し、ソルダーレジストの形
成やシルク文字印刷を容易にかつ正確に行うことができ
ると共に、表面実装部品の実装も容易に行うことができ
る複合回路基板を提供できる。またこの複合回路基板は
本発明の製造方法により容易に製造できるので、本発明
は複合回路基板のコストの低減に寄与できる。また大電
流用の部品はネジによる締め付け接続を行うものが多い
が、内層に厚肉回路パターンを設けることにより絶縁材
の厚さを絶縁距離が確保される範囲で薄くでき、基板の
枯れによるネジ緩みを防止できる。As described above, according to the present invention, the surface of the thin circuit pattern for the small current and the surface of the thick circuit pattern for the large current are located at the same level, and the formation of the solder resist and the printing of the silk character are performed. It is possible to provide a composite circuit board that can be easily and accurately performed, and that can easily mount surface-mounted components. Further, since the composite circuit board can be easily manufactured by the manufacturing method of the present invention, the present invention can contribute to a reduction in cost of the composite circuit board. Many high-current components are connected by screws.However, by providing a thick circuit pattern in the inner layer, the thickness of the insulating material can be reduced as long as the insulation distance is secured. Loosening can be prevented.
【図１】 本発明の製造方法の一実施形態における第１
段階を示す断面図。FIG. 1 shows a first embodiment of a manufacturing method according to the present invention.
Sectional drawing which shows a stage.
【図２】 図１の次の段階を示す断面図。FIG. 2 is a sectional view showing the next stage of FIG. 1;
【図３】 図２の次の段階を示す断面図。FIG. 3 is a sectional view showing the next stage of FIG. 2;
【図４】 図３の次の段階を示す断面図。FIG. 4 is a sectional view showing the next stage of FIG. 3;
【図５】 図４の次の段階を示す断面図。FIG. 5 is a sectional view showing the next stage of FIG. 4;
【図６】 図５の次の段階を示す断面図。FIG. 6 is a sectional view showing the next stage of FIG. 5;
【図７】 図６の次の段階を示す断面図。FIG. 7 is a sectional view showing the next stage of FIG. 6;
【図８】 図７の次の段階を示す断面図。FIG. 8 is a sectional view showing the next stage of FIG. 7;
【図９】 図８の次の段階を示す断面図。FIG. 9 is a sectional view showing a step subsequent to FIG. 8;
【図１０】 図９の次の段階を示す断面図。FIG. 10 is a sectional view showing the next stage of FIG. 9;
【図１１】 図１０の次の段階を示す断面図。FIG. 11 is a sectional view showing a step subsequent to FIG. 10;
【図１２】 以上の段階を経て製造された本発明の複合
回路基板の一実施形態を示す断面図。FIG. 12 is a sectional view showing an embodiment of the composite circuit board of the present invention manufactured through the above steps.
【図１３】 本発明の製造方法の他の実施形態における
第１段階を示す断面図。FIG. 13 is a sectional view showing a first stage in another embodiment of the manufacturing method of the present invention.
【図１４】 図１３の次の段階を示す断面図。FIG. 14 is a sectional view showing a step subsequent to FIG. 13;
【図１５】 図１４の次の段階を示す断面図。FIG. 15 is a sectional view showing a step subsequent to FIG. 14;
【図１６】 図１５の次の段階を示す断面図。FIG. 16 is a sectional view showing a step subsequent to FIG. 15;
【図１７】 図１６の次の段階を示す断面図。FIG. 17 is a sectional view showing a step subsequent to FIG. 16;
【図１８】 図１７の次の段階を示す断面図。FIG. 18 is a sectional view showing a step subsequent to FIG. 17;
【図１９】 図１８の次の段階を示す断面図。FIG. 19 is a sectional view showing a step subsequent to FIG. 18;
【図２０】 図１９の次の段階を示す断面図。FIG. 20 is a sectional view showing a step subsequent to FIG. 19;
【図２１】 図２０の次の段階を示す断面図。FIG. 21 is a sectional view showing a step subsequent to FIG. 20;
【図２２】 図２１の次の段階を示す断面図。FIG. 22 is a sectional view showing a step subsequent to FIG. 21;
【図２３】 図２２の次の段階を示す断面図。FIG. 23 is a sectional view showing a step subsequent to FIG. 22;
【図２４】 以上の段階を経て製造された本発明の複合
回路基板の他の実施形態を示す断面図。FIG. 24 is a cross-sectional view showing another embodiment of the composite circuit board of the present invention manufactured through the above steps.
【図２５】 本発明に係る複合回路基板の第１の問題点
を説明するための、（Ａ）は平面図、（Ｂ）は（Ａ）の
Ｂ−Ｂ線断面図。25A is a plan view and FIG. 25B is a cross-sectional view taken along the line BB of FIG. 25A for explaining the first problem of the composite circuit board according to the present invention.
【図２６】 第１の問題点を解決した本発明に係る複合
回路基板の実施形態を示す、（Ａ）は平面図、（Ｂ）は
底面図、（Ｃ）は（Ａ）のＣ−Ｃ線断面図、（Ｄ）は
（Ａ）のＤ−Ｄ線断面図。26 (A) is a plan view, FIG. 26 (B) is a bottom view, and FIG. 26 (C) is CC of FIG. (D) is a DD sectional view of (A).
【図２７】 本発明に係る複合回路基板の第２の問題点
を説明するための断面図。FIG. 27 is a sectional view for explaining a second problem of the composite circuit board according to the present invention.
【図２８】 第２の問題点を解決した本発明に係る複合
回路基板の実施形態を示す、（Ａ）は平面図、（Ｂ）は
底面図、（Ｃ）は（Ａ）のＣ−Ｃ線断面図、（Ｄ）は
（Ａ）のＤ−Ｄ線断面図。28 (A) is a plan view, FIG. 28 (B) is a bottom view, and FIG. 28 (C) is CC of FIG. (D) is a DD sectional view of (A).
１Ａ、１Ｂ：支持板 ３Ａ、３Ｂ：銅箔 ５Ａ、５Ｂ：めっきレジスト ７Ａ、７Ｂ：厚めっき層 ９：プリプレグ １１：穴 １３：絶縁基板 １５、１７：スルーホール用の貫通孔 １９：スルーホール用銅めっき層 ２１：エッチングレジスト ２３Ａ、２３Ｂ：小電流用の薄肉回路パターン ２５Ａ、２５Ｂ：大電流用の厚肉回路パターン 1A, 1B: Support plate 3A, 3B: Copper foil 5A, 5B: Plating resist 7A, 7B: Thick plating layer 9: Pre-preg 11: Hole 13: Insulating substrate 15, 17: Through hole for through hole 19: For through hole Copper plating layer 21: Etching resist 23A, 23B: Thin circuit pattern for small current 25A, 25B: Thick circuit pattern for large current
Claims (5)
パターン（２３Ａ、２３Ｂ）と大電流用の厚肉回路パタ
ーン（２５Ａ、２５Ｂ）とを有する複合回路基板におい
て、前記薄肉回路パターン（２３Ａ、２３Ｂ）はその厚
さ分が絶縁基板（１３）の表面から突出しており、前記
厚肉回路パターン（２５Ａ、２５Ｂ）はその厚さのうち
実質的に薄肉回路パターンの厚さに相当する分が絶縁基
板（１３）の表面から突出し、残る厚さ分が絶縁基板
（１３）に埋め込まれていることを特徴とする複合回路
基板。1. A composite circuit board having a thin circuit pattern (23A, 23B) for a small current and a thick circuit pattern (25A, 25B) for a large current on an insulating substrate (13). (23A, 23B) project from the surface of the insulating substrate (13) by the thickness thereof, and the thick circuit pattern (25A, 25B) substantially corresponds to the thickness of the thin circuit pattern of the thickness. A composite circuit board characterized in that a portion of the thickness of the composite circuit board protrudes from the surface of the insulating substrate (13), and the remaining thickness is embedded in the insulating substrate (13).
肉回路パターン（２５Ａ、２５Ｂ）につながる部分で、
薄肉回路パターン（２３Ａ、２３Ｂ）の幅が当該部分か
ら離れた部分より広くなっていることを特徴とする請求
項１記載の複合回路基板。2. A portion where the thin circuit patterns (23A, 23B) are connected to the thick circuit patterns (25A, 25B).
The composite circuit board according to claim 1, wherein the width of the thin circuit pattern (23A, 23B) is wider than that of the portion away from the portion.
絶縁基板（１３）の表面から突出する部分の縁が、絶縁
基板（１３）に埋め込まれている部分の縁より外側に位
置していることを特徴とする請求項１記載の複合回路基
板。3. The method of manufacturing a thick circuit pattern (25A, 25B)
The composite circuit board according to claim 1, wherein an edge of a portion protruding from a surface of the insulating substrate (13) is located outside an edge of a portion embedded in the insulating substrate (13).
Ａ、３Ｂ）を張り付ける工程、 薄肉金属箔（３Ａ、３Ｂ）上に得ようとする厚肉回路パ
ターンに対応したパターンの増肉導体層（７Ａ、７Ｂ）
を形成する工程、 増肉導体層（７Ａ、７Ｂ）を形成した側の面に絶縁基板
（１３）を設ける工程、 前記支持板（１Ａ、１Ｂ）を除去して、増肉導体層（７
Ａ、７Ｂ）が絶縁基板（１３）に埋め込まれ、薄肉金属
箔（３Ａ、３Ｂ）が表面に積層された積層板を得る工
程、 その積層板の薄肉金属箔（３Ａ、３Ｂ）をパターンエッ
チングして、前記増肉導体層（７Ａ、７Ｂ）のない領域
に薄肉回路パターン（２３Ａ、２３Ｂ）を形成すると共
に、増肉導体層（７Ａ、７Ｂ）に沿って厚肉回路パター
ン（２５Ａ、２５Ｂ）を形成する工程、 を含む複合回路基板の製造方法。4. A thin metal foil (3) is formed on a support plate (1A, 1B).
A, 3B), a thickened conductor layer (7A, 7B) having a pattern corresponding to the thick circuit pattern to be obtained on the thin metal foil (3A, 3B).
Forming an insulating substrate (13) on the surface on which the thickened conductor layers (7A, 7B) are formed; removing the support plates (1A, 1B) to form a thickened conductor layer (7
A, 7B) embedded in an insulating substrate (13) to obtain a laminate having thin metal foils (3A, 3B) laminated on the surface, and pattern-etching the thin metal foils (3A, 3B) of the laminate. Thus, the thin circuit patterns (23A, 23B) are formed in the region without the thickened conductor layers (7A, 7B), and the thick circuit patterns (25A, 25B) are formed along the thickened conductor layers (7A, 7B). Forming a composite circuit board.
Ａ、３Ｂ）を張り付ける工程、 薄肉金属箔（３Ａ、３Ｂ）上に得ようとする厚肉回路パ
ターンに対応したパターンが残るようにめっきレジスト
（５Ａ、５Ｂ）を形成する工程、 薄肉金属箔（３Ａ、３Ｂ）を電極として電解めっきを行
い、めっきレジスト（５Ａ、５Ｂ）で覆われていない領
域に厚めっき層（７Ａ、７Ｂ）を形成する工程、 めっきレジスト（５Ａ、５Ｂ）を除去する工程、 厚めっき層（７Ａ、７Ｂ）を形成した側の面にプリプレ
グ（９）を積層し、加熱加圧して、絶縁基板（１３）を
形成する工程、 前記支持板（１Ａ、１Ｂ）を除去して、厚めっき層（７
Ａ、７Ｂ）が絶縁基板（１３）に埋め込まれ、薄肉金属
箔（３Ａ、３Ｂ）が表面に積層された積層板を得る工
程、 その積層板の薄肉金属箔（３Ａ、３Ｂ）をパターンエッ
チングして、前記厚めっき層（７Ａ、７Ｂ）のない領域
に薄肉回路パターン（２３Ａ、２３Ｂ）を形成すると共
に、厚めっき層（７Ａ、７Ｂ）に沿って厚肉回路パター
ン（２５Ａ、２５Ｂ）を形成する工程、 を含む複合回路基板の製造方法。5. A thin metal foil (3) on a support plate (1A, 1B).
A, 3B), a step of forming a plating resist (5A, 5B) on the thin metal foil (3A, 3B) so as to leave a pattern corresponding to the thick circuit pattern to be obtained, a thin metal foil Electroplating using (3A, 3B) as an electrode to form thick plating layers (7A, 7B) in areas not covered with plating resists (5A, 5B), removing plating resists (5A, 5B) A step of laminating a prepreg (9) on the surface on which the thick plating layers (7A, 7B) are formed, heating and pressing to form an insulating substrate (13), and removing the support plates (1A, 1B) To the thick plating layer (7
A, 7B) embedded in an insulating substrate (13) to obtain a laminate having thin metal foils (3A, 3B) laminated on the surface, and pattern-etching the thin metal foils (3A, 3B) of the laminate. Thus, thin circuit patterns (23A, 23B) are formed in regions without the thick plating layers (7A, 7B), and thick circuit patterns (25A, 25B) are formed along the thick plating layers (7A, 7B). A method for manufacturing a composite circuit board, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5528997A JPH1032371A (en) | 1996-05-17 | 1997-03-10 | Composite circuit board and its manufacture |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12376896 | 1996-05-17 | ||
| JP8-123768 | 1996-05-17 | ||
| JP5528997A JPH1032371A (en) | 1996-05-17 | 1997-03-10 | Composite circuit board and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1032371A true JPH1032371A (en) | 1998-02-03 |
Family
ID=26396185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5528997A Pending JPH1032371A (en) | 1996-05-17 | 1997-03-10 | Composite circuit board and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1032371A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217540A (en) * | 2001-01-17 | 2002-08-02 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing multilayer wiring board |
| US6900545B1 (en) * | 1999-06-25 | 2005-05-31 | International Business Machines Corporation | Variable thickness pads on a substrate surface |
| JP2006147881A (en) * | 2004-11-19 | 2006-06-08 | Multi:Kk | Printed wiring board and manufacturing method therefor |
| JP2007134410A (en) * | 2005-11-08 | 2007-05-31 | Multi:Kk | Printed wiring board with resistor circuit and method of manufacturing same |
| JP2008277737A (en) * | 2007-04-30 | 2008-11-13 | Samsung Electro Mech Co Ltd | Carrier member for transferring circuit, coreless printed board using the same, and methods of manufacturing the both |
| JP2011108704A (en) * | 2009-11-13 | 2011-06-02 | Nec Corp | Printed wiring board and method of manufacturing the same |
| WO2023203294A1 (en) * | 2022-04-21 | 2023-10-26 | Safran Electronics & Defense | Process for manufacturing a printed circuit board and printed circuit board |
-
1997
- 1997-03-10 JP JP5528997A patent/JPH1032371A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6900545B1 (en) * | 1999-06-25 | 2005-05-31 | International Business Machines Corporation | Variable thickness pads on a substrate surface |
| JP2002217540A (en) * | 2001-01-17 | 2002-08-02 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing multilayer wiring board |
| JP2006147881A (en) * | 2004-11-19 | 2006-06-08 | Multi:Kk | Printed wiring board and manufacturing method therefor |
| JP4713131B2 (en) * | 2004-11-19 | 2011-06-29 | 株式会社マルチ | Printed wiring board and method for manufacturing the printed wiring board |
| JP2007134410A (en) * | 2005-11-08 | 2007-05-31 | Multi:Kk | Printed wiring board with resistor circuit and method of manufacturing same |
| JP4713305B2 (en) * | 2005-11-08 | 2011-06-29 | 株式会社マルチ | Printed wiring board with resistance circuit and manufacturing method thereof |
| JP2008277737A (en) * | 2007-04-30 | 2008-11-13 | Samsung Electro Mech Co Ltd | Carrier member for transferring circuit, coreless printed board using the same, and methods of manufacturing the both |
| JP4646968B2 (en) * | 2007-04-30 | 2011-03-09 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Method for manufacturing carrier member for circuit transfer |
| JP2011108704A (en) * | 2009-11-13 | 2011-06-02 | Nec Corp | Printed wiring board and method of manufacturing the same |
| WO2023203294A1 (en) * | 2022-04-21 | 2023-10-26 | Safran Electronics & Defense | Process for manufacturing a printed circuit board and printed circuit board |
| FR3134945A1 (en) * | 2022-04-21 | 2023-10-27 | Safran Electronics & Defense | METHOD FOR MANUFACTURING A PRINTED CIRCUIT BOARD |
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