JPH10303037A - Thin film stacked type magnetic induction device and its manufacture - Google Patents
Thin film stacked type magnetic induction device and its manufactureInfo
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- JPH10303037A JPH10303037A JP10557297A JP10557297A JPH10303037A JP H10303037 A JPH10303037 A JP H10303037A JP 10557297 A JP10557297 A JP 10557297A JP 10557297 A JP10557297 A JP 10557297A JP H10303037 A JPH10303037 A JP H10303037A
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- Prior art keywords
- thin film
- film
- conductor
- thin
- coil
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スイッチング電源
のワンチップ化等のため、半導体製造技術を利用して集
積回路装置のチップに搭載するに適する薄膜積層形磁気
誘導素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film laminated magnetic induction element suitable for mounting on a chip of an integrated circuit device by using a semiconductor manufacturing technique for making a switching power supply into one chip or the like.
【０００２】[0002]
【従来の技術】チョッパ装置やスイッチング電源等の小
形の電子装置は、従来からインダクタや変圧器等の受動
素子と、個別半導体素子や集積回路等の能動素子とを、
組み合わせて構成されてきたが、能動素子側の半導体技
術の急速な進歩に比べて、受動素子側の技術進歩は立ち
遅れ気味である。特にインダクタや変圧器等の磁気誘導
素子は、集積回路装置と比べると体格が非常に大きいた
めに、電子装置の小形化を図る上で最大の隘路になって
いる。このため、電子装置のチョッピングやスイッチン
グの動作周波数を、１ＭＨｚ以上に高めて、小形化をい
わば側面から容易にするとともに、磁気誘導素子自体の
構造面でも種々の試みがなされている。2. Description of the Related Art Conventionally, small electronic devices such as a chopper device and a switching power supply have conventionally used passive devices such as inductors and transformers and active devices such as discrete semiconductor devices and integrated circuits.
Although they have been configured in combination, the technological progress on the passive device side is lagging behind the rapid progress in the semiconductor technology on the active device side. In particular, magnetic induction elements such as inductors and transformers are very large in size as compared with integrated circuit devices, and are the biggest bottleneck in miniaturizing electronic devices. For this reason, various attempts have been made to increase the operating frequency of chopping and switching of the electronic device to 1 MHz or more to facilitate miniaturization from the side, and also to improve the structure of the magnetic induction element itself.
【０００３】例えば、特開昭６１−２１９１１４号公報
に開示された技術では、磁性繊維を縦糸に、極細銅線を
横糸にして編んだ織物構造でインダクタが構成される。
特開平１−１５１２１１号公報の技術では、磁気誘導素
子がセラミックの積層構造体から構成される。また、特
開平２−２７５６０６号公報には、可撓性フィルムにコ
イルを担持させて、それらを両側から磁性シートで挟み
込んだ構造の平面形のインダクタが開示されている。For example, in the technique disclosed in Japanese Patent Application Laid-Open No. 61-219114, an inductor is constituted by a woven structure in which a magnetic fiber is woven by warp and an ultrafine copper wire is woven by weft.
In the technique disclosed in Japanese Patent Application Laid-Open No. 1-151211, the magnetic induction element is formed of a ceramic laminated structure. Japanese Patent Application Laid-Open No. 2-275606 discloses a planar inductor having a structure in which a coil is carried on a flexible film and they are sandwiched between magnetic sheets from both sides.
【０００４】これらの従来技術からもわかるように、磁
気誘導素子の小形化には個別素子をそれに適した構造に
する方向と、能動素子用の半導体チップ上に直接搭載な
いし作り付ける方向とがあるが、電子装置の全体構造を
小形化し、かつ面実装等の組み立ての手間を極力省いて
合理化できる点では、後者の方向が明らかに有利であ
り、前述の特開昭６１−２１９１１４号公報および特開
平１−１５１２１１号公報の技術は、個別素子を小形化
する方向なので余り有利でない。As can be seen from these prior arts, there are two directions for reducing the size of a magnetic induction element: a direction in which an individual element has a structure suitable for it; and a direction in which an individual element is directly mounted or formed on a semiconductor chip for an active element. However, the latter direction is clearly advantageous in that the overall structure of the electronic device can be reduced in size and the labor of assembling such as surface mounting can be reduced as much as possible, and the latter direction is clearly advantageous. The technique disclosed in Japanese Unexamined Patent Publication No. 1-151211 is not very advantageous because it tends to downsize individual elements.
【０００５】コイル導体を平面上でスパイラル状に形成
した平面インダクタンスと称する特開平２−２７５６０
６号公報の技術は本質は個別素子であるが、チップへの
搭載に適すると考えられる。しかし、これはポリイミド
フィルムの両面に銅のコイルを形成したものであって、
しかも、銅コイルの断面積は、３５μｍ×２５０μｍ、
コイルのピッチ５００μｍというような、数〜１０ｍｍ
角の小形チップに搭載できる程度までの小形化は、実際
にはかならずしも容易でなく、かつ個別素子である以上
は、チップと接合するための実装作業が不可欠になる。Japanese Patent Laid-Open No. 27560/1990 called a planar inductance in which a coil conductor is formed in a spiral shape on a plane.
Although the technology disclosed in Japanese Patent Publication No. 6 is essentially an individual element, it is considered suitable for mounting on a chip. However, this is a copper film formed on both sides of the polyimide film,
Moreover, the cross-sectional area of the copper coil is 35 μm × 250 μm,
Several to 10 mm, such as a coil pitch of 500 μm
Actually, it is not always easy to reduce the size to a size that can be mounted on a small chip with a corner, and if it is an individual element, mounting work for bonding to the chip is indispensable.
【０００６】かかる問題に加えて、高周波領域内で磁気
誘導素子に高いＱ（＝ω・Ｌ／Ｒ）値を持たせるのが困
難な問題である。ここでωは角周波数、Ｌはインダクタ
ンス、Ｒは抵抗である。すなわち、従来から磁気誘導素
子を小形化するには、先ず電子装置の動作周波数を上げ
て、小さなインダクタンス値でも所定のリアクタンス値
が得られるようにしているが、１ＭＨｚ以上の周波数領
域では、磁気回路やコイル内の高周波損失のために磁気
誘導素子のインダクタンス値が飽和し、抵抗値が増加す
るので、動作周波数を上げると、Ｑ値が飽和ないし逆に
減少してくる。このため、動作周波数を上げてもＱ値を
所定レベルに維持するために磁気誘導素子の体格を小さ
くできなくなってくる。特開平２−２７５６０６号公報
の平面インダクタンスにおいて、銅コイルを大きくした
理由の一つは、Ｑ値を高くするためであった。In addition to the above problem, it is difficult to give a high Q (= ω · L / R) value to the magnetic induction element in a high frequency region. Here, ω is an angular frequency, L is an inductance, and R is a resistance. That is, conventionally, in order to reduce the size of the magnetic induction element, first, the operating frequency of the electronic device is increased so that a predetermined reactance value can be obtained even with a small inductance value. Since the inductance value of the magnetic induction element is saturated and the resistance value increases due to high frequency loss in the coil, the Q value becomes saturated or conversely decreases when the operating frequency is increased. For this reason, even if the operating frequency is increased, the physical size of the magnetic induction element cannot be reduced in order to maintain the Q value at a predetermined level. One of the reasons for increasing the size of the copper coil in the planar inductance disclosed in Japanese Patent Application Laid-Open No. 2-275606 was to increase the Q value.
【０００７】[0007]
【発明が解決しようとする課題】近年、磁気誘導素子の
小形化の要求に応えて、半導体技術の適用により、半導
体基板上に磁気誘導素子を搭載した例も報告されてい
る。発明者の同僚も特願平８−１４９６２６において、
そのような薄膜磁気誘導素子を提案した。図３（ａ）な
いし（ｄ）は、その提案に記載された例のコイルの主な
製造工程を工程順に示した部分断面図である。半導体ウ
ェハ上に絶縁膜を介して下側磁性薄膜を積層し、更に下
側絶縁膜で覆ったものを基板１としている。基板１上に
中間絶縁膜となるポリイミド薄膜２を、コイル導体の高
さであるｔc の厚さに形成する［図３（ａ）］。In recent years, there has been reported an example in which a magnetic induction element is mounted on a semiconductor substrate by applying semiconductor technology in response to a demand for downsizing of the magnetic induction element. A colleague of the inventor also filed Japanese Patent Application No. 8-149626,
Such a thin film magnetic induction device was proposed. FIGS. 3A to 3D are partial cross-sectional views showing the main steps of manufacturing the coil of the example described in the proposal in the order of steps. A substrate 1 is formed by laminating a lower magnetic thin film on a semiconductor wafer via an insulating film and further covering the lower magnetic thin film with the lower insulating film. The polyimide thin film 2 as the intermediate insulating film is formed on the substrate 1 to a thickness of t c is the height of the coil conductor [Fig. 3 (a)].
【０００８】フォトレジスト３を塗布し、フォトマスク
を使用して露光、現像をおこなう。ポリイミド薄膜２
は、現像時にフォトレジスト３と同時にウェットエッチ
ングされ、ポリイミド薄膜２に幅ｄ、間隔ｓの溝４が形
成される［同図（ｂ）］。フォトレジスト３を除去する
［同図（ｃ）］。ポリイミド薄膜２の焼結乾燥後、溝４
内にメッキにより薄膜導体５となる銅を充填する［同２
（ｄ）］。A photoresist 3 is applied, and is exposed and developed using a photomask. Polyimide thin film 2
Is wet-etched simultaneously with the photoresist 3 during development, and a groove 4 having a width d and an interval s is formed in the polyimide thin film 2 [FIG. The photoresist 3 is removed [FIG. After sintering and drying of the polyimide thin film 2, the groove 4
Is filled with copper to be a thin film conductor 5 by plating [Id.
(D)].
【０００９】この後、薄膜導体５および中間絶縁膜６の
上に上側絶縁膜を介して上側磁性薄膜を堆積して、断面
がｔc ×ｄ、間隔がｓのコイルが形成される。先に記し
た式に従ってＱ値を高くするためには、角周波数ωを高
くすることは、勿論であるが、Ｌ値をなるべく大きく、
Ｒ値をなるべく小さくする必要がある。図３に示すよう
な薄膜インダクタの場合、Ｒ値を小さくするには、導体
の長さおよび巻き数を変えずに、導体の断面積ｔc ×ｄ
を大きくすればよい。Thereafter, an upper magnetic thin film is deposited on the thin film conductor 5 and the intermediate insulating film 6 via the upper insulating film, and a coil having a cross section of t c × d and an interval of s is formed. In order to increase the Q value according to the above-described equation, it is obvious that the angular frequency ω is increased, but the L value is increased as much as possible.
It is necessary to make the R value as small as possible. In the case of a thin-film inductor as shown in FIG. 3, in order to reduce the R value, the conductor cross-sectional area t c × d without changing the length and number of turns of the conductor.
Should be increased.
【００１０】しかし、通常ウェットエッチングで形成で
きる溝は、アスペクト比（＝ｔc ／ｄ）１が最大であ
り、アスペクト比の大きなコイル導体を形成するのは、
非常に困難であった。例えば、厚さｔc ＝３μｍとする
と、幅ｄは３μｍ以上となり、コイルを小型化する上で
制限が生じ、また、コイルの効率化も困難となる。ま
た、コイルの薄膜導体幅ｄを増加させた場合、近接効果
や表皮効果等による銅損により、却って交流抵抗を増大
させてしまうという問題をも生じる。However, a groove which can be usually formed by wet etching has a maximum aspect ratio (= t c / d) of 1, and a coil conductor having a large aspect ratio is formed by:
It was very difficult. For example, if the thickness t c is 3 μm, the width d becomes 3 μm or more, which imposes restrictions on miniaturization of the coil and also makes it difficult to increase the efficiency of the coil. Further, when the thin film conductor width d of the coil is increased, there is also a problem that the AC resistance is increased due to copper loss due to a proximity effect, a skin effect, or the like.
【００１１】このような現状に立脚して、本発明は集積
回路等の半導体装置のチップ上に直接かつ容易に作り込
むに適した薄膜積層構造をもち、かつ高周波領域内でも
Ｑ値を高く維持することができる磁気誘導素子およびそ
の製造方法を提供することを目的とする。Based on this situation, the present invention has a thin film laminated structure suitable for being directly and easily formed on a chip of a semiconductor device such as an integrated circuit, and maintains a high Q value even in a high frequency region. It is an object of the present invention to provide a magnetic induction element and a method of manufacturing the same.
【００１２】[0012]
【課題を解決するための手段】上記の課題解決のため本
発明は、シリコン基板上に形成された、コイル状に成形
された薄膜導体が一対の絶縁膜の相互間に挟み込まれた
構造を有する磁気誘導素子において、薄膜導体の断面の
幅ｄと厚さｔc との関係が ｔc ＞ｄであるものとす
る。In order to solve the above problems, the present invention has a structure in which a thin film conductor formed in a coil shape and formed on a silicon substrate is sandwiched between a pair of insulating films. in magnetic induction, the relationship between the width d and the thickness t c of the cross-section of the thin-film conductor is assumed to be t c> d.
【００１３】そのようにすれば、幅ｄを変えずに抵抗Ｒ
を低減できる。逆に一定の抵抗Ｒとした場合、幅ｄを小
さくでき、小形化に適する。特に、一対の絶縁膜の外側
に一対の磁性層を有するものとする。そのようにすれ
ば、薄膜積層型磁気誘導素子のインダクタンスを増大で
きる。本発明の薄膜積層型磁気誘導素子の製造方法とし
ては、下層側磁性薄膜を下層側絶縁膜で被覆し、下層側
絶縁膜上に中間絶縁膜を付け、その中間絶縁膜にコイル
のパターンに対応する溝幅より深さが深い溝を設け、そ
の溝に薄膜導体を充填し、薄膜導体の中間絶縁膜上に堆
積された部分を除去し、薄膜導体と中間絶縁膜とを上層
絶縁膜で被覆し、その上に上層側磁性薄膜を配設するも
のとする。In this case, the resistance R can be maintained without changing the width d.
Can be reduced. Conversely, when the resistance R is constant, the width d can be reduced, which is suitable for miniaturization. In particular, a pair of magnetic layers is provided outside a pair of insulating films. By doing so, the inductance of the thin-film laminated magnetic induction element can be increased. As a method of manufacturing the thin film laminated magnetic induction element of the present invention, the lower magnetic thin film is covered with a lower insulating film, an intermediate insulating film is provided on the lower insulating film, and the intermediate insulating film corresponds to a coil pattern. A groove deeper than the groove width to be filled, filling the groove with a thin film conductor, removing the portion of the thin film conductor deposited on the intermediate insulating film, and covering the thin film conductor and the intermediate insulating film with the upper insulating film Then, an upper magnetic thin film is provided thereon.
【００１４】そのようにすれば、幅ｄより厚さｔc の厚
い薄膜導体をもつ薄膜積層型磁気誘導素子が形成され
る。特に、中間絶縁膜の溝をリアクティブイオンエッチ
ング法によりおこなうものとすれば、異方性エッチング
が可能であり、アスペクト比の大きい溝を形成できる。[0014] By doing so, a thin film laminated magnetic induction with a thick film conductor thicknesses t c than the width d is formed. In particular, if the groove of the intermediate insulating film is formed by a reactive ion etching method, anisotropic etching can be performed, and a groove having a large aspect ratio can be formed.
【００１５】そして、薄膜導体の充填をリフロースパッ
タ法によりおこなうものとすれば、アスペクト比の大き
い溝への充填が可能である。また、薄膜導体の充填をＭ
ＯＣＶＤ法によりおこなうものとすれば、アスペクト比
の一層大きい溝への充填が可能である。更に、薄膜導体
の中間絶縁膜上に堆積された部分の除去を、化学機械的
研磨法（以下ＣＭＰ法と記す）によりおこなうものとす
れば、中間絶縁膜をストッパにするので、充填された薄
膜導体の厚さを殆ど損なわずにできる。If the thin film conductor is filled by reflow sputtering, it is possible to fill a groove having a large aspect ratio. The filling of the thin-film conductor is M
If it is performed by the OCVD method, it is possible to fill a groove having a larger aspect ratio. Further, if the portion of the thin film conductor deposited on the intermediate insulating film is removed by a chemical mechanical polishing method (hereinafter referred to as a CMP method), the intermediate insulating film is used as a stopper. The thickness of the conductor can be hardly impaired.
【００１６】[0016]
【発明の実施の形態】以下、実施例を参照しながら本発
明の実施の形態を詳細に説明する。 ［実施例１］図１は、本発明第一の実施例（以下実施例
１と記す）のコイルの断面図である。Embodiments of the present invention will be described below in detail with reference to examples. [Embodiment 1] FIG. 1 is a sectional view of a coil according to a first embodiment (hereinafter, referred to as Embodiment 1) of the present invention.
【００１７】図１において、１１はシリコンウェハであ
り、図示されない右方には、半導体素子が作製されてい
る。シリコンウェハ１１上にポリイミドからなる分離絶
縁膜１２を介して、パーマロイの下側磁性薄膜１３が積
層されており、その下側磁性薄膜１３を覆うポリイミド
からなる下側絶縁膜１４の上に、コイルが形成されてい
る。図では、コイルの断面のアルミニウムからなる薄膜
導体１５と、その間の酸化シリコン膜の中間絶縁膜１６
とが示されている。薄膜導体１５と中間絶縁膜１６との
上には、ポリイミドの上側絶縁膜１７を介してパーマロ
イの上側磁性薄膜１８が積層され、更にその上をポリイ
ミドの保護絶縁膜１９が覆っている。２０は、図示しな
い断面で薄膜導体１５の一端と接続しているコンタクト
である。In FIG. 1, reference numeral 11 denotes a silicon wafer, and a semiconductor element is formed on the right side (not shown). A lower magnetic thin film 13 made of permalloy is laminated on a silicon wafer 11 via an isolation insulating film 12 made of polyimide, and a coil is placed on a lower insulating film 14 made of polyimide which covers the lower magnetic thin film 13. Are formed. In the figure, a thin-film conductor 15 made of aluminum in a cross section of a coil and an intermediate insulating film 16 of a silicon oxide film therebetween are shown.
Are shown. A permalloy upper magnetic thin film 18 is laminated on the thin film conductor 15 and the intermediate insulating film 16 with a polyimide upper insulating film 17 interposed therebetween, and further a polyimide protective insulating film 19 covers the upper magnetic thin film 18. Reference numeral 20 denotes a contact connected to one end of the thin film conductor 15 in a cross section (not shown).
【００１８】この実施例１のコイルにおいて、特徴的な
点は、薄膜導体１５の高さｔc が、その幅ｄより約二倍
と大きいことである。図２（ａ）ないし（ｄ）は、実施
例１のコイルの製造方法を説明するための製造工程順の
部分断面図である。半導体ウェハ上に分離絶縁膜を介し
て下側磁性薄膜を積層し、更に下側絶縁膜で覆ったもの
を基板１０としている。なお、ポリイミド膜は、塗布と
焼成により、パーマロイ膜はスパッタ法により成膜でき
る。[0018] In the coil of Example 1, the characteristic feature, the height t c of the thin film conductor 15, is as large as about twice than its width d. FIGS. 2A to 2D are partial cross-sectional views illustrating a method of manufacturing the coil of the first embodiment in the order of manufacturing steps. A substrate 10 is formed by laminating a lower magnetic thin film on a semiconductor wafer via an isolation insulating film and further covering the lower magnetic thin film with the lower insulating film. The polyimide film can be formed by coating and baking, and the permalloy film can be formed by a sputtering method.
【００１９】基板１０上にコイル導体の所定の厚さｔc
に等しい厚さ（本実施例では２μｍ）の中間絶縁膜１６
となるシリコン酸化膜１６ａを形成する。後にコイル間
の絶縁となるこの酸化シリコン膜１６ａの形成方法は色
々あるが、基板１０の図示されない部分に既に半導体素
子が形成されていることから、３５０℃程度の低温下
で、モノシラン（ＳｉＨ4 ）と酸素（Ｏ2 ）との混合ガ
スの雰囲気内の減圧ＣＶＤ法により成膜するのがよい。
成膜時の圧力は１７０Ｐａである。次いで、フォトレジ
スト２３を塗布し、フォトマスクを使用して露光、現像
をおこない、所望の薄膜導体幅ｄ（この例の場合１μ
ｍ、間隔ｓ＝３μｍ）となるように、パターニングする
［図１（ａ）］。A predetermined thickness t c of the coil conductor is provided on the substrate 10.
(In this embodiment, 2 μm).
A silicon oxide film 16a is formed. There are various methods for forming the silicon oxide film 16a which will be used to insulate the coil later. However, since a semiconductor element has already been formed on a portion (not shown) of the substrate 10, monosilane (SiH 4 ) And oxygen (O 2 ) are preferably formed by a reduced-pressure CVD method in an atmosphere of a mixed gas.
The pressure during film formation is 170 Pa. Next, a photoresist 23 is applied, and exposure and development are performed using a photomask to obtain a desired thin film conductor width d (1 μm in this example).
m, interval s = 3 μm) (FIG. 1A).
【００２０】次いで、このフォトレジスト２３のパター
ンをマスクとして酸化シリコン膜１６ａをエッチング
し、溝２４を形成する。溝２４の側面を図のように垂直
にして狭い幅ｓを狙いどおり正確にするため、リアクテ
ィブイオンエッチング法を利用するのが有利である。こ
の際、異方性エッチング条件とするため、エッチングガ
スとして六ふっ化エタン（Ｃ2 Ｆ6 ）と三ふっ化メタン
（ＣＨＦ3 ）の混合ガスを用い、その雰囲気圧力は１５
０Ｐａ、電力密度は、０．２Ｗ／ｃｍ2 程度とするのが
良い［図１（ｂ）］。Next, using the pattern of the photoresist 23 as a mask, the silicon oxide film 16a is etched to form a groove 24. It is advantageous to use a reactive ion etching method in order to make the side surface of the groove 24 vertical as shown and to make the narrow width s exactly as intended. At this time, a mixed gas of ethane hexafluoride (C 2 F 6 ) and methane trifluoride (CHF 3 ) is used as an etching gas in order to set anisotropic etching conditions.
0 Pa and the power density are preferably about 0.2 W / cm 2 [FIG. 1 (b)].
【００２１】以上のように加工された基板１０の全面上
に、この実施例ではコイルの薄膜導体１５となるアルミ
ニウム（Ａｌ）をリフロースパッタ法によって２μｍの
膜厚に成膜する［図１（ｃ）］。条件は、基板温度５０
０℃、アルゴンガス圧力１Ｐａ、スパッタ電力３ｋＷで
ある。リフローのため下地として薄い多結晶シリコン層
を形成しておくとよい。またこの際、図では、１５ａで
示すようにシリコン酸化膜１６ａの上側にも薄膜導体が
被着する。リフロースパッタ法では、アスペクト比が１
以上、２程度までのコイル導体の形成が可能であり、本
実施例の幅１μｍ深さ２μｍの溝に充填することができ
る。On the entire surface of the substrate 10 processed as described above, in this embodiment, aluminum (Al) to be the thin film conductor 15 of the coil is formed to a thickness of 2 μm by a reflow sputtering method [FIG. )]. Conditions are: substrate temperature 50
0 ° C., argon gas pressure 1 Pa, sputtering power 3 kW. It is preferable to form a thin polycrystalline silicon layer as a base for reflow. At this time, a thin film conductor is also deposited on the upper side of the silicon oxide film 16a as shown by 15a in the figure. In the reflow sputtering method, the aspect ratio is 1
As described above, up to about two coil conductors can be formed, and can be filled in the groove having a width of 1 μm and a depth of 2 μm in this embodiment.
【００２２】その後、ＣＭＰ（化学機械研磨）法によ
り、表面を研磨してシリコン酸化膜１６ａの上側のＡｌ
膜１５ａを除去し、平坦化する［図１（ｄ）］。ＣＭＰ
法により平坦化をおこなうと、中間絶縁膜１６をストッ
パにするので、充填された薄膜導体１５の厚さを殆ど損
なわずにできる。しかも、中間絶縁膜１５と薄膜導体１
５との上面が平坦化されるので、例えば、コイルを積層
する場合等、その後のプロセスを容易にする。Thereafter, the surface is polished by a CMP (Chemical Mechanical Polishing) method to remove the Al on the upper side of the silicon oxide film 16a.
The film 15a is removed and flattened [FIG. 1 (d)]. CMP
When the planarization is performed by the method, since the intermediate insulating film 16 is used as a stopper, the thickness of the filled thin-film conductor 15 can be hardly impaired. Moreover, the intermediate insulating film 15 and the thin film conductor 1
5 is flattened, thereby facilitating subsequent processes, for example, when laminating coils.
【００２３】更に、半導体基板１を水洗してエッチング
液を完全に除去した後、前述と同様にポリイミド膜を基
板１０の全面に成膜して、上側絶縁膜１７とする。また
は、低温の減圧ＣＶＤ法により酸化シリコン膜を形成し
て薄膜導体１５間の中間絶縁膜１６と連続した上側絶縁
膜１７としてもよい。これ以降は図１のように上側磁性
薄膜１８を配設し、ポリイミド等の保護絶縁膜１９によ
りそれを被覆し、コンタクト２０を設けて薄膜積層型磁
気誘導素子の完成状態とすることでよい。Further, after the semiconductor substrate 1 is washed with water to completely remove the etchant, a polyimide film is formed on the entire surface of the substrate 10 in the same manner as described above to form the upper insulating film 17. Alternatively, an upper insulating film 17 continuous with the intermediate insulating film 16 between the thin film conductors 15 may be formed by forming a silicon oxide film by a low-pressure low-pressure CVD method. Thereafter, as shown in FIG. 1, an upper magnetic thin film 18 may be provided, covered with a protective insulating film 19 such as polyimide, and provided with a contact 20 to complete the thin-film laminated magnetic induction element.
【００２４】以上説明した薄膜積層型磁気誘導素子の製
造方法によれば、アスペクト比が１より大きい溝２２を
充填することができた。すなわち、高さｔc が幅ｄより
大きい薄膜導体１５のコイルを形成できた。これによ
り、薄膜導体１５の抵抗Ｒの値を低減して電流容量を増
加させ、かつそのＱ値を高めることができる。また、抵
抗Ｒを一定とすれば、幅ｄを小さくでき、コイルを小型
化する上で有利で、コイルの効率化もできる。更に、近
接効果や表皮効果等による銅損を低減できる効果もあ
る。According to the method of manufacturing a thin-film laminated magnetic induction device described above, the grooves 22 having an aspect ratio larger than 1 can be filled. That is, the coil of the thin film conductor 15 having the height t c larger than the width d was formed. As a result, the value of the resistance R of the thin film conductor 15 can be reduced to increase the current capacity and increase the Q value. Further, if the resistance R is fixed, the width d can be reduced, which is advantageous in reducing the size of the coil, and the efficiency of the coil can be increased. Further, there is an effect that copper loss due to a proximity effect, a skin effect, and the like can be reduced.
【００２５】また、膜厚ｔc が幅ｄより大きい薄膜導体
１５のコイルとすることによって、上下の磁性薄膜１
３、１８間に漏れるわたり磁束を低減でき、わたり磁束
による抵抗Ｒの増大を抑制できるという効果も得られ
る。なお、以上の実施例では、磁気誘導素子が単一のコ
イルをもつインダクタとして説明したが、薄膜導体から
形成する可能であればつづら折れ状等の種々な形状を採
用できる。さらに、実施例にしめされた具体的な寸法、
形状、構造、配置等はあくまで例示であって、本発明の
要旨内で適宜な変更ないし変形が可能である。Also, by forming the coil of the thin film conductor 15 having a thickness t c larger than the width d, the upper and lower magnetic thin films 1 are formed.
It is also possible to obtain the effect that the magnetic flux leaking between 3, 18 can be reduced and the increase in the resistance R due to the magnetic flux can be suppressed. In the above embodiment, the magnetic induction element has been described as an inductor having a single coil. However, if it is possible to form the magnetic induction element from a thin film conductor, various shapes such as a serpentine shape can be adopted. Further, specific dimensions set forth in the examples,
The shape, structure, arrangement, and the like are merely examples, and appropriate changes and modifications are possible within the gist of the present invention.
【００２６】［実施例２］実施例１と同様であるが、図
１（ｃ）において、コイルの薄膜導体１５となるＡｌの
堆積方法として、ＭＯＣＶＤ法を用いる。成膜条件は、
基板温度３００℃、供給ガスは、ジメチルアルミニウム
ハイドライド（ＡｌＨ（ＣＨ3 ）2 ）と水素（Ｈ2 ）と
の混合ガスである。その他の加工方法は、実施例１と同
じである。この方法により、アスペクト比が４程度まで
のコイル導体の形成が可能となった。[Embodiment 2] As in Embodiment 1, the MOCVD method is used as a method for depositing Al to be the thin film conductor 15 of the coil in FIG. The deposition conditions are
The substrate temperature is 300 ° C. and the supply gas is a mixed gas of dimethyl aluminum hydride (AlH (CH 3 ) 2 ) and hydrogen (H 2 ). Other processing methods are the same as those in the first embodiment. According to this method, a coil conductor having an aspect ratio of up to about 4 can be formed.
【００２７】これにより、薄膜導体１５の抵抗Ｒの値を
低減して電流容量を増加させ、かつそのＱ値を高める効
果、および、上下の磁性薄膜１３、１８間に漏れるわた
り磁束による抵抗Ｒの増大を抑制できるという効果が一
層大きなものとなる。 ［実施例３］実施例２と同様であるが、コイルの薄膜導
体の堆積方法として、銅のＭＯＣＶＤ法を用いる。成膜
条件は、基板温度３００℃、供給ガスは、ヘキサフロロ
アセチルアセトン銅（Ｃｕ（ｈｆａｃ）2 ）と水素（Ｈ
2 ）との混合ガスである。その他の加工方法は、実施例
２と同じである。この方法ても、アスペクト比が４程度
までのコイル導体の形成が可能となる。効果は実施例２
とほぼ同じである。As a result, the value of the resistance R of the thin-film conductor 15 is reduced to increase the current capacity and increase the Q value, and the resistance R due to the magnetic flux leaking between the upper and lower magnetic thin films 13 and 18 is reduced. The effect that the increase can be suppressed is further enhanced. [Embodiment 3] As in Embodiment 2, a MOCVD method of copper is used as a method for depositing a thin film conductor of a coil. The film formation conditions were a substrate temperature of 300 ° C., and supply gases of copper hexafluoroacetylacetone (Cu (hfac) 2 ) and hydrogen (H
2 ) mixed gas. Other processing methods are the same as in the second embodiment. Even with this method, a coil conductor having an aspect ratio of up to about 4 can be formed. The effect is Example 2
Is almost the same as
【００２８】[0028]
【発明の効果】以上説明したように本発明によれば、コ
イルの薄膜導体断面を幅より高さの高いものとすること
によって、おなじ幅であれば、抵抗を低減し、電流容量
を増加させ、かつＱ値の高いすなわち高効率の薄膜積層
型磁気誘導素子が得られる。また、わたり磁束による抵
抗の増大を抑制できるという効果も得られる。As described above, according to the present invention, by setting the cross section of the thin film conductor of the coil to be higher than the width, the resistance can be reduced and the current capacity can be increased if the width is the same. In addition, a thin-film laminated magnetic induction element having a high Q value, that is, a high efficiency can be obtained. Further, an effect of suppressing an increase in resistance due to a magnetic flux can be obtained.
【００２９】逆に、抵抗Ｒを一定とすれば、幅を小さく
できて、薄膜積層型磁気誘導素子を小型化する上で有利
である。Conversely, if the resistance R is fixed, the width can be reduced, which is advantageous in reducing the size of the thin-film laminated magnetic induction element.
【図１】本発明第一の実施例のコイルの断面図FIG. 1 is a sectional view of a coil according to a first embodiment of the present invention.
【図２】（ａ）ないし（ｄ）は実施例１のコイルの製造
方法を示す工程順の断面図FIGS. 2A to 2D are cross-sectional views in a process order illustrating a method of manufacturing the coil of Example 1. FIGS.
【図３】（ａ）ないし（ｄ）は従来のコイルの製造方法
による工程順の断面図FIGS. 3A to 3D are cross-sectional views in the order of steps according to a conventional coil manufacturing method.
１、１０ 基板 ２ ポリイミド膜 ３、２３ フォトレジスト ４、２４ 溝 ５、１５ 薄膜導体 １１ シリコンウェハ １２ 分離絶縁膜 １３ 下側磁性薄膜 １４ 下側絶縁膜 １５ａ 酸化シリコン膜上のＡｌ膜 １６ 中間絶縁膜 １６ａ 酸化シリコン膜 １７ 上側絶縁膜 １８ 下側磁性薄膜 １９ 保護絶縁膜 ２０ コンタクト DESCRIPTION OF SYMBOLS 1, 10 Substrate 2 Polyimide film 3, 23 Photoresist 4, 24 Groove 5, 15 Thin film conductor 11 Silicon wafer 12 Separation insulating film 13 Lower magnetic thin film 14 Lower insulating film 15a Al film on silicon oxide film 16 Intermediate insulating film 16a Silicon oxide film 17 Upper insulating film 18 Lower magnetic thin film 19 Protective insulating film 20 Contact
Claims (7)
成形された薄膜導体が一対の絶縁膜の相互間に挟み込ま
れた構造を有する磁気誘導素子において、薄膜導体の断
面の幅ｄと厚さｔc との関係が ｔc ＞ｄであることを
特徴とする薄膜積層型磁気誘導素子。1. A magnetic induction element having a structure in which a thin film conductor formed in a coil shape and formed on a silicon substrate is sandwiched between a pair of insulating films, the width d and the thickness of the cross section of the thin film conductor. thin film laminated magnetic induction, characterized in that the relationship between t c is t c> d.
ることを特徴とする請求項１記載の薄膜積層型磁気誘導
素子。2. The thin-film laminated magnetic induction element according to claim 1, further comprising a pair of magnetic layers outside the pair of insulating films.
性薄膜の相互間に挟み込んだ構造の磁気誘導素子の製造
方法であって、下層側磁性薄膜を下層側絶縁膜で被覆
し、下層側絶縁膜上に中間絶縁膜を付け、その中間絶縁
膜にコイルのパターンに対応する溝幅より深さが深い溝
を設け、その溝に薄膜導体を充填し、薄膜導体の中間絶
縁膜上に堆積された部分を除去し、薄膜導体と中間絶縁
膜とを上層絶縁膜で被覆し、その上に上層側磁性薄膜を
配設するようにしたことを特徴とする薄膜積層形磁気誘
導素子の製造方法。3. A method for manufacturing a magnetic induction element having a structure in which a thin film conductor formed into a coil shape is sandwiched between a pair of magnetic thin films, wherein the lower magnetic thin film is covered with a lower insulating film. An intermediate insulating film is provided on the side insulating film, a groove having a depth greater than the groove width corresponding to the coil pattern is provided in the intermediate insulating film, and the thin film conductor is filled in the groove. Manufacturing of a thin-film laminated magnetic induction element characterized in that the deposited portion is removed, the thin-film conductor and the intermediate insulating film are covered with an upper insulating film, and an upper magnetic thin film is disposed thereon. Method.
チング法によりおこなうことを特徴とする請求項３記載
の薄膜積層型磁気誘導素子の製造方法。4. The method according to claim 3, wherein the groove in the intermediate insulating film is formed by a reactive ion etching method.
りおこなうことを特徴とする請求項３または４に記載の
薄膜積層型磁気誘導素子の製造方法。5. The method according to claim 3, wherein the filling of the thin film conductor is performed by a reflow sputtering method.
なうことを特徴とする請求項３または４に記載の薄膜積
層型磁気誘導素子の製造方法。6. The method according to claim 3, wherein the filling of the thin film conductor is performed by MOCVD.
を除去を化学機械的研磨法によりおこなうことを特徴と
する請求項５または６に記載の薄膜積層型磁気誘導素子
の製造方法。7. The method according to claim 5, wherein the portion of the thin film conductor deposited on the intermediate insulating film is removed by a chemical mechanical polishing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10557297A JPH10303037A (en) | 1997-04-23 | 1997-04-23 | Thin film stacked type magnetic induction device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10557297A JPH10303037A (en) | 1997-04-23 | 1997-04-23 | Thin film stacked type magnetic induction device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10303037A true JPH10303037A (en) | 1998-11-13 |
Family
ID=14411247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10557297A Pending JPH10303037A (en) | 1997-04-23 | 1997-04-23 | Thin film stacked type magnetic induction device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10303037A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2830670A1 (en) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Integrated circuit with inductance comprises spiral channel in which metal deposit forms inductance winding |
| US6830970B2 (en) | 2001-10-10 | 2004-12-14 | Stmicroelectronics, S.A. | Inductance and via forming in a monolithic circuit |
| WO2007043405A1 (en) * | 2005-10-14 | 2007-04-19 | Matsushita Electric Industrial Co., Ltd. | Electronic component and method for manufacturing same |
| KR100720499B1 (en) | 2005-12-30 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Method for forming inductor |
| KR100880794B1 (en) * | 2002-07-05 | 2009-02-02 | 매그나칩 반도체 유한회사 | Inductor of secmiconductor device and method for forming the same |
| US11763982B2 (en) | 2018-04-12 | 2023-09-19 | Samsung Electro-Mechanics Co., Ltd. | Inductor and manufacturing method thereof |
-
1997
- 1997-04-23 JP JP10557297A patent/JPH10303037A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2830670A1 (en) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Integrated circuit with inductance comprises spiral channel in which metal deposit forms inductance winding |
| EP1302955A1 (en) * | 2001-10-10 | 2003-04-16 | STMicroelectronics S.A. | Inductance and its manufacturing method |
| US6830970B2 (en) | 2001-10-10 | 2004-12-14 | Stmicroelectronics, S.A. | Inductance and via forming in a monolithic circuit |
| US7404249B2 (en) | 2001-10-10 | 2008-07-29 | Stmicroelectronics S.A. | Method of manufacturing an inductance |
| KR100938501B1 (en) * | 2001-10-10 | 2010-01-25 | 에스티마이크로일렉트로닉스 에스.에이. | Inductor and its manufacturing method |
| KR100880794B1 (en) * | 2002-07-05 | 2009-02-02 | 매그나칩 반도체 유한회사 | Inductor of secmiconductor device and method for forming the same |
| WO2007043405A1 (en) * | 2005-10-14 | 2007-04-19 | Matsushita Electric Industrial Co., Ltd. | Electronic component and method for manufacturing same |
| JP2007109934A (en) * | 2005-10-14 | 2007-04-26 | Matsushita Electric Ind Co Ltd | Electronic component and manufacturing method thereof |
| KR100720499B1 (en) | 2005-12-30 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Method for forming inductor |
| US11763982B2 (en) | 2018-04-12 | 2023-09-19 | Samsung Electro-Mechanics Co., Ltd. | Inductor and manufacturing method thereof |
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