JPH1027888A - Laminated electrode for ferroelectrics capacity insulating film and ferroelectrics capacity element using the same - Google Patents
Laminated electrode for ferroelectrics capacity insulating film and ferroelectrics capacity element using the sameInfo
- Publication number
- JPH1027888A JPH1027888A JP8183229A JP18322996A JPH1027888A JP H1027888 A JPH1027888 A JP H1027888A JP 8183229 A JP8183229 A JP 8183229A JP 18322996 A JP18322996 A JP 18322996A JP H1027888 A JPH1027888 A JP H1027888A
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- JP
- Japan
- Prior art keywords
- insulating film
- ferroelectric capacitor
- capacitor insulating
- ferroelectrics
- laminated electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は強誘電体容量絶縁膜
用積層電極およびこれを用いた強誘電体容量素子に関
し、さらに詳しくは、強誘電体容量絶縁膜用電極の加工
性を向上するとともに、ペロブスカイト型等の強誘電体
膜の組成ずれを防止した、強誘電体容量絶縁膜用積層電
極およびこれを用いた強誘電体容量素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electrode for a ferroelectric capacitor insulating film and a ferroelectric capacitor using the same, and more particularly, to improving the processability of the electrode for a ferroelectric capacitor insulating film. The present invention relates to a laminated electrode for a ferroelectric capacitor insulating film in which a composition shift of a ferroelectric film such as a perovskite type is prevented, and a ferroelectric capacitor using the same.
【０００２】[0002]
【従来の技術】次世代のメモリ系半導体装置の記憶保持
用等の誘電体薄膜として、チタン酸鉛〔ＰｂＴｉ
Ｏ3 〕、ＰＺＴ〔Ｐｂ（Ｚｒx Ｔｉ1-x ）Ｏ3 〕、ＰＬ
ＺＴ〔ＰｂyＬａ1-y （Ｚｒx Ｔｉ1-x ）Ｏ3 〕、ある
いはＢａx Ｓｒ1-x ＴｉＯ3 等、一般式ＡＢＯ3 で表さ
れるペロブスカイト型酸化物薄膜や、ＳｒＢｉ2 Ｔａ2
Ｏ9 、Ｂｉ4 Ｔｉ3 Ｏ12等のビスマス系層状複合化合物
を採用する動向がある。これら複合酸化物薄膜の強誘電
性を利用し、ＤＲＡＭの電荷蓄積用キャパシタ誘電体膜
として、またＭＩＳ型トランジスタのゲート絶縁膜に用
いたＭＦＳトランジスタとして、あるいは分極反転のヒ
ステリシスを用いたＦＲＡＭとして、さらには焦電性を
利用した赤外線センサや圧電素子、光スイッチ等への利
用等が考えられている。これら強誘電体容量素子を用い
た電子デバイスの実用化には、特性に優れた強誘電体薄
膜の形成方法およびそのパターニング方法とともに、強
誘電体薄膜上の電極の選択およびこの電極のパターニン
グ方法が重要な課題である。2. Description of the Related Art Lead dielectric titanate [PbTi
O 3 ], PZT [Pb (Zr x Ti 1-x ) O 3 ], PL
ZT [Pb y La 1-y (Zr x Ti 1-x) O 3 ], or Ba x Sr 1-x TiO 3, etc., and perovskite oxide thin film represented by a general formula ABO 3, SrBi 2 Ta 2
There is a trend to employ bismuth-based layered composite compounds such as O 9 and Bi 4 Ti 3 O 12 . Utilizing the ferroelectricity of these composite oxide thin films, as a capacitor dielectric film for charge storage of a DRAM, as an MFS transistor used as a gate insulating film of a MIS transistor, or as an FRAM using hysteresis of domain inversion, Further, use for an infrared sensor, a piezoelectric element, an optical switch, or the like using pyroelectricity has been considered. Practical use of electronic devices using these ferroelectric capacitors involves a method of forming a ferroelectric thin film having excellent characteristics and a patterning method thereof, a selection of an electrode on the ferroelectric thin film, and a method of patterning the electrode. This is an important issue.
【０００３】従来より、強誘電体複合酸化物への電極材
料としては、その高温特性の安定性および耐酸化性の観
点から白金（Ｐｔ）を用いるのが一般的である。これは
電極形成後に酸化性雰囲気中で熱処理を施して、強誘電
体複合酸化物の結晶性を改善する処理が必要とされる場
合が多いからである。すなわち、通常の金属を強誘電体
複合酸化物の電極材料として採用すると、熱処理により
電極が酸化される。この結果、強誘電体複合酸化物と電
極金属の界面に、低誘電体層や常誘電体層が生成し、Ｄ
ＲＡＭやＦＲＡＭ等の素子特性が劣化する。白金電極を
用いれば、かかる酸化による誘電体特性の劣化の虞れは
少ない。[0003] Conventionally, platinum (Pt) is generally used as an electrode material for a ferroelectric composite oxide from the viewpoint of stability of high-temperature characteristics and oxidation resistance. This is because it is often necessary to perform a heat treatment in an oxidizing atmosphere after the formation of the electrodes to improve the crystallinity of the ferroelectric composite oxide. That is, when a normal metal is used as the electrode material of the ferroelectric composite oxide, the electrode is oxidized by the heat treatment. As a result, a low dielectric layer or a paraelectric layer is formed at the interface between the ferroelectric composite oxide and the electrode metal, and D
Device characteristics such as RAM and FRAM deteriorate. If a platinum electrode is used, there is little risk of deterioration of the dielectric properties due to such oxidation.
【０００４】このＰｔ薄膜のパターニングには、王水に
よるウェットエッチングか、Ａｒ等の希ガスによるスパ
ッタエッチング、イオンビームエッチング等が通常採用
される。For the patterning of the Pt thin film, wet etching with aqua regia, sputter etching with a rare gas such as Ar, ion beam etching, or the like is usually employed.
【０００５】しかしながら、ウェットエッチングによる
パターニングにおいてはレジストパターンの密着性やサ
イドエッチングの問題、さらには他のドライプロセスと
の整合性の問題がある。またＡｒ等の希ガスによる物理
的なパターニングにおいては、選択比や下地強誘電体薄
膜へのダメージ、パターニングされたＰｔ電極やレジス
トパターンへのＰｔのスパッタ再付着による寸法変換差
やパーティクル汚染等、解決すべき問題点が多い。再付
着への解決策としては、Ａｒ+ の入射角度をかえて多段
階エッチングする方法が例えば特開平５−１０９６６８
号公報に開示されている。この方法によれば、Ｐｔの再
付着はある程度防止できるが異方性形状は得られず、メ
モリ等の高集積度化には不向きである。また再付着して
しまったＰｔの側壁付着膜をジェットスクラバ等高圧噴
流水や、綿繊維によるローラブラシで除去する方法が例
えば特開平５−２１４０５号公報に開示されている。こ
の方法によれば異方性形状を保ったままのパターニング
は可能となるが、微視的に見ればＰｔの側壁付着膜の破
断面が新たに形成され、パターン形状の悪化が懸念され
る。またローラブラシによるダメージやパーティクル汚
染の虞れも未解決である。[0005] However, patterning by wet etching has problems of adhesion of resist patterns, side etching, and compatibility with other dry processes. In the case of physical patterning with a rare gas such as Ar, the selectivity, damage to the underlying ferroelectric thin film, dimensional conversion differences due to sputter re-attachment of Pt to the patterned Pt electrode or resist pattern, particle contamination, etc. There are many problems to be solved. As a solution to the redeposition, a method of performing multi-step etching by changing the incident angle of Ar + is disclosed in, for example, Japanese Patent Laid-Open No. 5-109668.
No. 6,086,045. According to this method, redeposition of Pt can be prevented to some extent, but an anisotropic shape cannot be obtained, which is not suitable for high integration of memories and the like. Japanese Patent Application Laid-Open No. 5-2405 discloses, for example, a method of removing the Pt side wall adhering film that has re-adhered with high pressure jet water such as a jet scrubber or a roller brush made of cotton fibers. According to this method, patterning can be performed while maintaining the anisotropic shape. However, microscopically, a broken surface of the Pt side wall adhesion film is newly formed, and there is a concern that the pattern shape may be deteriorated. Further, the risk of damage and particle contamination by the roller brush has not been solved.
【０００６】一方、反応生成物による側壁保護膜の利用
による異方性エッチングの試みも提案されている。例え
ば、第４０回応用物理学関係連合講演会（１９９３年春
季年会）講演予稿集講演番号３０ａ−ＺＥ−３にはＨＢ
ｒ／ＣＨ4 混合ガス系によるマグネトロンＲＩＥを用い
たプロセスの報告がある。また同様のガス系によりＥＣ
Ｒプラズマエッチング装置を採用した例が、Ｍｉｃｒｏ
Ｐｒｏｃｅｓｓ Ｃｏｎｆｅｒｅｎｃｅ予稿集Ｂ−７
−５，ｐ１４６（１９９３）に報告されている。いずれ
の例も、対レジストパターン選択比と異方性確保のた
め、カーボン系ポリマを堆積するＣＨ4 ガスを添加して
いるので、パーティクル汚染や、チャンバ内汚染による
エッチング再現性低下の虞れが残る。またエッチングレ
ートも２０ｎｍ／分程度と小さい。On the other hand, there has been proposed an attempt of anisotropic etching by utilizing a side wall protective film by a reaction product. For example, the 40th JSAP Lecture Meeting on Applied Physics (Spring Annual Meeting, 1993)
There is a report on a process using magnetron RIE using an r / CH 4 mixed gas system. In addition, similar gas systems use EC
An example using an R plasma etching apparatus is Micro
Proceedings of Process Conference B-7
-5, p146 (1993). In each case, CH 4 gas for depositing a carbon-based polymer is added in order to secure the selectivity and anisotropy with respect to the resist pattern, so that there is a possibility that particle contamination or deterioration in etching reproducibility due to contamination in the chamber may occur. Remains. Also, the etching rate is as low as about 20 nm / min.
【０００７】また通常の電極金属加工に用いられるハロ
ゲン系ガスをエッチングガスに用いると、反応生成物で
あるハロゲン化白金の蒸気圧が低いものが多いため、こ
の場合にはエッチングレートは極端に小さくなる。Further, when a halogen-based gas used for ordinary electrode metal processing is used as an etching gas, the vapor pressure of platinum halide, which is a reaction product, is often low, so that the etching rate is extremely low in this case. Become.
【０００８】[0008]
【発明が解決しようとする課題】そこで耐酸化性や加工
性、あるいは金属的な導電性にすぐれた電極材料とし
て、ＲｕＯ2 、ＩｒＯ2 あるいはＯｓＯ2 等のルチル型
酸化物や、ＳｒＲｕＯ3 、ＳｒＩｒＯ3 あるいはＲｅＯ
3 等のペロブスカイト型複合酸化物等の導電性セラミッ
クス材料を採用する動向がある。しかしながら、これら
導電性セラミックス膜による電極は、後の熱処理工程に
おいて、強誘電体複合酸化物からＰｂやＢａ等の金属元
素が導電性セラミックス膜に拡散する不具合がある。こ
のため強誘電体複合酸化物の組成ずれが生じ、強誘電体
容量素子の特性劣化を発生する虞れが多い。Accordingly, rutile oxides such as RuO 2 , IrO 2 or OsO 2 , SrRuO 3 , and SrIrO 2 are used as electrode materials having excellent oxidation resistance, workability, or metallic conductivity. 3 or ReO
There is a trend to use conductive ceramic materials such as perovskite-type composite oxides such as 3rd grade. However, electrodes made of these conductive ceramic films have a problem that metal elements such as Pb and Ba diffuse from the ferroelectric composite oxide into the conductive ceramic film in a heat treatment step to be performed later. For this reason, there is a possibility that the composition shift of the ferroelectric composite oxide occurs and the characteristic of the ferroelectric capacitor element is deteriorated.
【０００９】本発明は上述した技術的背景のもとに提案
するものであり、加工性に優れると同時に、強誘電体複
合酸化物の組成ずれを生じることのない、強誘電体容量
絶縁膜用積層電極を提供することをその課題とする。ま
た本発明の別の課題は、かかる電極を用いた特性の優れ
た強誘電体容量素子を提供することである。The present invention has been proposed based on the above technical background, and has excellent workability and does not cause a composition shift of a ferroelectric composite oxide. It is an object to provide a laminated electrode. Another object of the present invention is to provide a ferroelectric capacitor having excellent characteristics using such an electrode.
【００１０】[0010]
【課題を解決するための手段】本願の強誘電体容量絶縁
膜用積層電極は上述の課題を解決するために提案するも
のであり、強誘電体容量絶縁膜の上部電極および下部電
極の少なくとも何れか一方に、導電性セラミックス膜を
用いた電極であって、この強誘電体容量絶縁膜と導電性
セラミックス膜との間に、白金薄膜を有することを特徴
とする。この白金薄膜の厚さは、５ｎｍ以上１００ｎｍ
以下であることが望ましく、１０ｎｍ以上７０ｎｍ以下
であることがさらに望ましい。白金薄膜は、スパッタリ
ング法やレーザアブレーション法等により成膜するが、
膜の連続性や均一性の観点からは厚さ５ｎｍ未満では不
適切であり、１０ｎｍ以上が好ましい。また厚さ１００
ｎｍを超えると加工性が劣化するので、７０ｎｍ以下を
選ぶことが好ましい。SUMMARY OF THE INVENTION The laminated electrode for a ferroelectric capacitor insulating film of the present invention is proposed to solve the above-mentioned problem, and at least one of an upper electrode and a lower electrode of the ferroelectric capacitor insulating film. On the other hand, an electrode using a conductive ceramic film is characterized in that a platinum thin film is provided between the ferroelectric capacitor insulating film and the conductive ceramic film. The thickness of this platinum thin film is 5 nm or more and 100 nm
The thickness is preferably not more than 10 nm and more preferably not more than 10 nm. Platinum thin film is formed by sputtering method or laser ablation method, etc.
If the thickness is less than 5 nm, it is inappropriate from the viewpoint of the continuity and uniformity of the film, and the thickness is preferably 10 nm or more. Also thickness 100
If it exceeds nm, workability deteriorates, so it is preferable to select 70 nm or less.
【００１１】本発明で採用する強誘電体容量絶縁膜とし
ては、鉛系ペロブスカイト型複合酸化物やバリウム系ペ
ロブスカイト型複合酸化物、あるいはビスマス系層状複
合酸化物が例示される。また本発明で採用する導電性セ
ラミックス膜としては、ルチル型酸化物あるいはペロブ
スカイト型複合酸化物が例示される。これら強誘電体容
量絶縁膜や導電性セラミックス膜は、いずれも構成金属
のアルキル化合物やアルコキシド化合物を用いたＭＯＣ
ＶＤ法やＭＯＤ法、あるいはレーザアブレーション法に
より成膜することができる。ＭＯＤ法は、有機金属化合
物を含む前駆体溶液を基板上に塗布し、これに熱処理を
加えて成膜する方法である。ルチル型酸化物の場合に
は、Ｒｕ等の金属を蒸着あるいはスパッタリング成膜し
た後に熱酸化して導電性セラミックス膜としてもよい。Examples of the ferroelectric capacitor insulating film employed in the present invention include a lead-based perovskite-type composite oxide, a barium-based perovskite-type composite oxide, and a bismuth-based layered composite oxide. Examples of the conductive ceramic film used in the present invention include a rutile oxide and a perovskite composite oxide. Both the ferroelectric capacitor insulating film and the conductive ceramic film are made of MOC using an alkyl compound or an alkoxide compound as a constituent metal.
The film can be formed by a VD method, a MOD method, or a laser ablation method. The MOD method is a method in which a precursor solution containing an organometallic compound is applied onto a substrate, and a heat treatment is applied thereto to form a film. In the case of a rutile oxide, a conductive ceramic film may be formed by vapor-depositing or sputtering a metal such as Ru and then thermally oxidizing it.
【００１２】本発明の強誘電体容量素子は、前述した強
誘電体容量絶縁膜用積層電極を用いたことを特徴とす
る。A ferroelectric capacitor according to the present invention is characterized by using the above-mentioned laminated electrode for a ferroelectric capacitor insulating film.
【００１３】本発明の強誘電体容量絶縁膜用積層電極に
おいては、膜にピンホール等が発生せずに連続性があ
り、必要最小限の厚さの白金薄膜を強誘電体容量絶縁膜
と導電性セラミックス膜との界面に設けることにより、
金属元素の拡散を防止し、強誘電体容量絶縁膜の組成ず
れを防止することができる。導電性セラミックス膜のエ
ッチングは、通常のハロゲン系化学種を用いたプラズマ
エッチングが容易である。白金薄膜は極く薄い膜である
ので、ウェットエッチングにおいてアンダカットやサイ
ドエッチングが入る虞れが少なく、またＡｒ+ を用いた
スパッタエッチングやイオンビームエッチングにおいて
も短時間でエッチングできる。したがって、強誘電体容
量絶縁膜等の下地材料層のダメージを最小限度に留めら
れ、微細加工性を損ねる懸念はない。このため、高集積
度の強誘電体容量素子の性能を低下することなく、信頼
性高く製造することができる。In the laminated electrode for a ferroelectric capacitor insulating film of the present invention, the film has continuity without generating pinholes and the like, and a platinum thin film having a necessary minimum thickness is formed as a ferroelectric capacitor insulating film. By providing at the interface with the conductive ceramic film,
The diffusion of the metal element can be prevented, and the composition deviation of the ferroelectric capacitor insulating film can be prevented. Plasma etching using a normal halogen-based chemical species is easy to etch the conductive ceramic film. Since the platinum thin film is an extremely thin film, undercut or side etching is less likely to occur in wet etching, and etching can be performed in a short time in sputter etching using Ar + or ion beam etching. Therefore, damage to the underlying material layer such as the ferroelectric capacitor insulating film can be minimized, and there is no concern that the fine workability is impaired. For this reason, a highly reliable ferroelectric capacitor can be manufactured with high reliability without deteriorating its performance.
【００１４】[0014]
【実施例】以下、本発明の具体的実施例につき、添付図
面を参照して説明する。まず本発明の強誘電体容量絶縁
膜用積層電極および強誘電体容量素子の構造につき、図
１に示した概略断面図を参照して説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings. First, the structure of the laminated electrode for a ferroelectric capacitor insulating film and the structure of the ferroelectric capacitor of the present invention will be described with reference to the schematic sectional view shown in FIG.
【００１５】本発明の強誘電体容量素子は、図１に示す
ように基板１上に順次形成された導電性セラミックス膜
２および白金薄膜３からなる下部強誘電体容量絶縁膜用
積層電極５、強誘電体容量絶縁膜４、白金薄膜３および
導電性セラミックス膜２からなる上部強誘電体容量絶縁
膜用積層電極６から概略構成される。As shown in FIG. 1, the ferroelectric capacitive element of the present invention comprises a laminated electrode 5 for a lower ferroelectric capacitive insulating film comprising a conductive ceramic film 2 and a platinum thin film 3 formed sequentially on a substrate 1; It is roughly composed of an upper ferroelectric capacitor insulating film laminated electrode 6 composed of a ferroelectric capacitor insulating film 4, a platinum thin film 3, and a conductive ceramic film 2.
【００１６】このうち基板１は単結晶シリコン等の半導
体基板や石英等の絶縁性基板等からなる。これら基板上
に多結晶シリコン膜や非晶質シリコン等の半導体薄膜や
配線層、あるいはＳｉＯ2 、Ｓｉ3 Ｎ4 等の絶縁膜が形
成されていてもよい。導電性セラミックス膜２は、Ｒｕ
Ｏ2 、ＩｒＯ2 あるいはＯｓＯ2 等のルチル型酸化物
や、ＳｒＲｕＯ3 、ＳｒＩｒＯ3 あるいはＲｅＯ3 等の
ペロブスカイト型複合酸化物からなる。強誘電体容量絶
縁膜４は、ＰｂＴｉＯ3 、Ｐｂ（Ｚｒx Ｔｉ1-x ）Ｏ3
あるいはＰｂy Ｌａ1-y （Ｚｒx Ｔｉ1-x ）Ｏ3 等の鉛
系ペロブスカイト型複合酸化物、Ｂａx Ｓｒ1-x ＴｉＯ
3 等のバリウム系ペロブスカイト型複合酸化物、あるい
はＳｒＢｉ2 Ｔａ2 Ｏ9 、Ｂｉ4 Ｔｉ3 Ｏ12等のビスマ
ス系層状複合化合物からなる。これら導電性セラミック
ス膜２と強誘電体容量絶縁膜４の界面には、白金薄膜３
が介在しており、拡散を防止する構成となっている。図
１に示した強誘電体容量素子構造は、本発明の最も基本
的な構造であり、導電性セラミックス膜２と白金薄膜３
からなる強誘電体容量絶縁膜用積層電極は、上部電極お
よび下部電極のいずれか一方のみに形成された構造であ
ってもよい。また強誘電体容量絶縁膜用積層電極は２層
構造に限らず、Ｒｕ、Ｉｒ等の金属薄膜やＴｉＮやＷＳ
ｉ等の金属化合物薄膜を含む多層構造であってもよい。The substrate 1 comprises a semiconductor substrate such as single crystal silicon or an insulating substrate such as quartz. A semiconductor thin film such as a polycrystalline silicon film or amorphous silicon or a wiring layer, or an insulating film such as SiO 2 or Si 3 N 4 may be formed on these substrates. The conductive ceramic film 2 is made of Ru
O 2, IrO 2 or OsO rutile oxide such as 2 or consists of SrRuO 3, SrIrO 3 or ReO perovskite complex oxides such as 3. The ferroelectric capacitor insulating film 4 is made of PbTiO 3 , Pb (Zr x Ti 1-x ) O 3
Alternatively Pb y La 1-y (Zr x Ti 1-x) O lead-based perovskite complex oxides such as 3, Ba x Sr 1-x TiO
3 or a barium-based perovskite-type composite oxide or a bismuth-based layered composite compound such as SrBi 2 Ta 2 O 9 or Bi 4 Ti 3 O 12 . At the interface between the conductive ceramic film 2 and the ferroelectric capacitor insulating film 4, a platinum thin film 3
Are interposed to prevent diffusion. The ferroelectric capacitor element structure shown in FIG. 1 is the most basic structure of the present invention, and includes a conductive ceramic film 2 and a platinum thin film 3.
The laminated electrode for a ferroelectric capacitor insulating film made of may have a structure formed on only one of the upper electrode and the lower electrode. The laminated electrode for the ferroelectric capacitor insulating film is not limited to the two-layer structure, but may be a metal thin film such as Ru or Ir, TiN or WS.
It may have a multilayer structure including a thin film of a metal compound such as i.
【００１７】これらの各膜は、有機金属化合物を用いた
ＭＯＣＶＤ法やＭＯＤ法、レーザアブレーション法、ス
パッタリング法あるいは蒸着法等により、基板１上に順
次形成される。この後、これらの積層膜上に形成した不
図示のレジストマスクやＳｉＯ2 等のハードマスクをエ
ッチングマスクとし、異方性エッチングを施して強誘電
体容量絶縁膜用積層電極および強誘電体容量素子を形成
する。異方性エッチングは、導電性セラミックス膜２と
強誘電体容量絶縁膜４に関しては、ハロゲン系化学種を
用いたＲＩＥやＥＣＲプラズマエッチング、あるいは誘
導結合プラズマエッチングやヘリコン波プラズマエッチ
ング等の高密度プラズマエッチングにより施すことがで
きる。また白金薄膜３に関しては、極薄であるのでＡｒ
+ イオンビーム等によるイオンミリングにより容易に加
工が可能である。また王水等を用いたウェットエッチン
グであっても、極薄であることから異方性を損ねずにパ
ターニングすることが可能である。These films are sequentially formed on the substrate 1 by an MOCVD method, an MOD method, a laser ablation method, a sputtering method or a vapor deposition method using an organic metal compound. Thereafter, using a resist mask (not shown) formed on these laminated films or a hard mask such as SiO 2 as an etching mask, anisotropic etching is performed to perform the ferroelectric capacitive insulating film laminated electrode and the ferroelectric capacitive element. To form In the anisotropic etching, the conductive ceramic film 2 and the ferroelectric capacitor insulating film 4 are formed by high-density plasma such as RIE or ECR plasma etching using a halogen-based chemical species, or inductively coupled plasma etching or helicon wave plasma etching. It can be applied by etching. Also, the platinum thin film 3 is extremely thin,
+ Easily processed by ion milling with an ion beam or the like. Also, even in the case of wet etching using aqua regia or the like, it is possible to perform patterning without impairing anisotropy because it is extremely thin.
【００１８】次に本発明の強誘電体容量素子および強誘
電体容量絶縁膜用積層電極の、より具体的な構成例につ
き、適宜比較例を加えながら説明する。Next, a more specific configuration example of the ferroelectric capacitor element and the laminated electrode for a ferroelectric capacitor insulating film according to the present invention will be described while appropriately adding comparative examples.
【００１９】実施例１ 高抵抗シリコン基板を熱酸化してＳｉＯ2 膜を３００ｎ
ｍの厚さに形成した基板１上に、スパッタリングおよび
反応性スパッタリングによりＲｕ膜を２００ｎｍ、Ｒｕ
Ｏ2 からなる導電性セラミックス膜２を５０ｎｍ、白金
薄膜３を例えば５０ｎｍの厚さに順次成膜し、下部強誘
電体容量絶縁膜用積層電極５を形成した。さらに下部強
誘電体容量絶縁膜用積層電極５上に、ＭＯＤ法によりＳ
ｒＢｉ2Ｔａ2 Ｏ9 からなる強誘電体容量絶縁膜４を３
００ｎｍの厚さに形成した。成膜温度は７００℃〜８０
０℃の範囲とした。強誘電体容量絶縁膜４上に、さらに
白金薄膜３を例えば５０ｎｍ、ＲｕＯ2 からなる導電性
セラミックス膜２を５０ｎｍ、およびＲｕ膜を２００ｎ
ｍの厚さに順次スパッタリングおよび反応性スパッタリ
ングにより形成し、上部強誘電体容量絶縁膜用積層電極
６を形成した。この後、エッチングマスクを形成し、ハ
ロゲン系化学種を用いたＲＩＥおよびＡｒガスを用いた
イオンミリングによりパターニングして、図１に示す強
誘電体容量素子を完成した。EXAMPLE 1 A high-resistance silicon substrate was thermally oxidized to form an SiO 2 film of 300 n.
On the substrate 1 formed to a thickness of 200 m, a Ru film is formed to a thickness of 200 nm by sputtering and reactive sputtering.
A conductive ceramic film 2 made of O 2 and a platinum thin film 3 were sequentially formed to a thickness of 50 nm and a thickness of, for example, 50 nm, to form a laminated electrode 5 for a lower ferroelectric capacitor insulating film. Furthermore, S is formed on the lower ferroelectric capacitor insulating film laminated electrode 5 by the MOD method.
The ferroelectric capacitor insulating film 4 made of rBi 2 Ta 2 O 9 is
It was formed to a thickness of 00 nm. The film formation temperature is 700 ° C to 80
The range was 0 ° C. On the ferroelectric capacitive insulating film 4, further for example, 50nm platinum film 3, the conductive ceramic layer 2 made of RuO 2 50nm, and Ru film 200n
m, and the laminated electrode 6 for the upper ferroelectric capacitor insulating film was formed in order by sputtering and reactive sputtering to a thickness of m. Thereafter, an etching mask was formed, and patterning was performed by RIE using a halogen-based chemical species and ion milling using an Ar gas to complete the ferroelectric capacitor shown in FIG.
【００２０】この強誘電体容量素子のＸ線回折結果を図
２に示す。各回折ピークは、ＳｒＢｉ2 Ｔａ2 Ｏ9 、Ｒ
ｕＯ2 、ＲｕおよびＰｔに対応するもののみであり、拡
散による反応層形成や組成ずれがが発生していないこと
が明らかである。FIG. 2 shows the result of X-ray diffraction of this ferroelectric capacitor. Each diffraction peak is represented by SrBi 2 Ta 2 O 9 , R
It is only those corresponding to uO 2 , Ru and Pt, and it is clear that there is no reaction layer formation or composition deviation due to diffusion.
【００２１】実施例２ 本実施例は、充分に洗浄した高抵抗シリコン基板上に、
直接に実施例１と同様の構成の下部強誘電体容量絶縁膜
用積層電極５、強誘電体容量絶縁膜４および上部強誘電
体容量絶縁膜用積層電極６を順次形成した他は、前実施
例１に準拠して強誘電体容量素子を形成した。本実施例
によってもＸ線回折の結果、拡散による反応層形成や組
成ずれの発生はなかった。Embodiment 2 In this embodiment, a sufficiently cleaned high-resistance silicon substrate is
Except that the laminated electrode 5 for the lower ferroelectric capacitor insulating film, the ferroelectric capacitor insulating film 4 and the laminated electrode 6 for the upper ferroelectric capacitor insulating film having the same configuration as that of the first embodiment were directly formed in this order, A ferroelectric capacitor was formed according to Example 1. According to the present example, as a result of X-ray diffraction, there was no formation of a reaction layer or composition deviation due to diffusion.
【００２２】実施例３ 本実施例は導電性セラミックス膜をゾルゲル法により形
成した例である。高抵抗シリコン基板上を熱酸化してＳ
ｉＯ2 膜を３００ｎｍの厚さに形成した基板１上に、ル
テニウムアルコキシドを含むゾル溶液を用いてゾルゲル
法によりＲｕＯ2 からなる導電性セラミックス膜２を２
００ｎｍ成膜し、この上にスパッタリングにより白金薄
膜３を例えば５０ｎｍ形成して下部強誘電体容量絶縁膜
用積層電極５を形成した。つぎに下部強誘電体容量絶縁
膜用積層電極５上にＭＯＤ法によりＳｒＢｉ2 Ｔａ2 Ｏ
9 からなる強誘電体容量絶縁膜４を３００ｎｍの厚さに
形成した。成膜温度は７００℃〜８００℃の範囲とし
た。この強誘電体容量絶縁膜４上にスパッタリングによ
り白金薄膜３を例えば５０ｎｍ形成した後、再びゾルゲ
ル法によりＲｕＯ2 からなる導電性セラミックス膜２を
２００ｎｍ成膜して上部強誘電体容量絶縁膜用積層電極
６を形成した。この後、エッチングマスクを形成し、ハ
ロゲン系化学種を用いたＲＩＥおよびＡｒガスを用いた
イオンミリングによりパターニングして、図１に示す強
誘電体容量素子を完成した。本実施例によってもＸ線回
折の結果、拡散による反応層形成や組成ずれの発生はな
かった。Embodiment 3 This embodiment is an example in which a conductive ceramic film is formed by a sol-gel method. Thermal oxidation on high resistance silicon substrate
A conductive ceramic film 2 made of RuO 2 was formed on a substrate 1 on which an iO 2 film was formed to a thickness of 300 nm by a sol-gel method using a sol solution containing ruthenium alkoxide.
A platinum thin film 3 having a thickness of, for example, 50 nm was formed thereon by sputtering to form a laminated electrode 5 for a lower ferroelectric capacitor insulating film. Next, SrBi 2 Ta 2 O is formed on the lower ferroelectric capacitor insulating film laminated electrode 5 by the MOD method.
A ferroelectric capacitor insulating film 4 of 9 was formed to a thickness of 300 nm. The film formation temperature was in the range of 700 ° C to 800 ° C. After forming a platinum thin film 3 of, for example, 50 nm on the ferroelectric capacitor insulating film 4 by sputtering, a 200 nm-thick conductive ceramic film 2 made of RuO 2 is again formed by a sol-gel method, and a stack for the upper ferroelectric capacitor insulating film is formed. The electrode 6 was formed. Thereafter, an etching mask was formed, and patterning was performed by RIE using a halogen-based chemical species and ion milling using an Ar gas to complete the ferroelectric capacitor shown in FIG. According to the present example, as a result of X-ray diffraction, there was no formation of a reaction layer or composition deviation due to diffusion.
【００２３】実施例４ 本実施例は、充分に洗浄した高抵抗シリコン基板上に、
直接に実施例３と同様の構成の下部強誘電体容量絶縁膜
用積層電極５、強誘電体容量絶縁膜４および上部強誘電
体容量絶縁膜用積層電極６を順次形成した他は、前実施
例３に準拠して強誘電体容量素子を形成した。本実施例
によってもＸ線回折の結果、拡散による反応層形成や組
成ずれの発生はなかった。Embodiment 4 In this embodiment, a sufficiently cleaned high-resistance silicon substrate is
Except that the laminated electrode 5 for lower ferroelectric capacitor insulating film, the ferroelectric capacitor insulating film 4 and the laminated electrode 6 for upper ferroelectric capacitor insulating film having the same structure as in Example 3 were formed in this order, A ferroelectric capacitor was formed according to Example 3. According to the present example, as a result of X-ray diffraction, there was no formation of a reaction layer or composition deviation due to diffusion.
【００２４】実施例５ 本実施例は導電性セラミックス膜をレーザアブレーショ
ン法により形成した例である。高抵抗シリコン基板を熱
酸化してＳｉＯ2 膜を３００ｎｍの厚さに形成した基板
１上に、レーザアブレーション法によりＳｒＲｕＯ3 か
らなる導電性セラミックス膜２を２００ｎｍ成膜し、こ
の上にスパッタリングにより白金薄膜３を例えば５０ｎ
ｍ形成して下部強誘電体容量絶縁膜用積層電極５を形成
した。つぎに下部強誘電体容量絶縁膜用積層電極５上に
ＭＯＤ法によりＳｒＢｉ2 Ｔａ2 Ｏ9 からなる強誘電体
容量絶縁膜４を３００ｎｍの厚さに形成した。成膜温度
は７００℃〜８００℃の範囲とした。この強誘電体容量
絶縁膜４上にスパッタリングにより白金薄膜３を例えば
５０ｎｍ形成した後、再びレーザアブレーション法によ
りＳｒＲｕＯ3 からなる導電性セラミックス膜２を２０
０ｎｍ成膜して上部強誘電体容量絶縁膜用積層電極６を
形成した。この後、エッチングマスクを形成し、ハロゲ
ン系化学種を用いたＲＩＥおよびＡｒガスを用いたイオ
ンミリングによりパターニングして、図１に示す強誘電
体容量素子を完成した。本実施例によってもＸ線回折の
結果、拡散による反応層形成や組成ずれの発生はなかっ
た。Embodiment 5 This embodiment is an example in which a conductive ceramic film is formed by a laser ablation method. On a substrate 1 on which a high-resistance silicon substrate was thermally oxidized to form a SiO 2 film with a thickness of 300 nm, a conductive ceramic film 2 made of SrRuO 3 was formed to a thickness of 200 nm by a laser ablation method. The thin film 3 is, for example, 50 n
Thus, a laminated electrode 5 for a lower ferroelectric capacitor insulating film was formed. Next, a 300 nm thick ferroelectric capacitor insulating film 4 made of SrBi 2 Ta 2 O 9 was formed on the lower ferroelectric capacitor insulating film laminated electrode 5 by the MOD method. The film formation temperature was in the range of 700 ° C to 800 ° C. After forming a platinum thin film 3 of, for example, 50 nm on the ferroelectric capacitor insulating film 4 by sputtering, a conductive ceramic film 2 of SrRuO 3 is again formed by laser ablation method.
An upper ferroelectric capacitor insulating film laminated electrode 6 was formed to a thickness of 0 nm. Thereafter, an etching mask was formed, and patterning was performed by RIE using a halogen-based chemical species and ion milling using an Ar gas to complete the ferroelectric capacitor shown in FIG. According to the present example, as a result of X-ray diffraction, there was no formation of a reaction layer or composition deviation due to diffusion.
【００２５】実施例６ 本実施例は、充分に洗浄した高抵抗シリコン基板上に、
直接に実施例５と同様の構成の下部強誘電体容量絶縁膜
用積層電極５、強誘電体容量絶縁膜４および上部強誘電
体容量絶縁膜用積層電極６を順次形成した他は、前実施
例５に準じて強誘電体容量素子を形成した。本実施例に
よってもＸ線回折の結果、拡散による反応層形成や組成
ずれの発生はなかった。Embodiment 6 In this embodiment, a sufficiently cleaned high-resistance silicon substrate is
Except that the laminated electrode 5 for the lower ferroelectric capacitor insulating film, the ferroelectric capacitor insulating film 4 and the laminated electrode 6 for the upper ferroelectric capacitor insulating film having the same configuration as in the fifth embodiment were directly formed in this order, A ferroelectric capacitor was formed according to Example 5. According to the present example, as a result of X-ray diffraction, there was no formation of a reaction layer or composition deviation due to diffusion.
【００２６】比較例 高抵抗シリコン基板を熱酸化してＳｉＯ2 膜を３００ｎ
ｍの厚さに形成した基板上に、ルテニウムアルコキシド
を含むゾル溶液を用いてゾルゲル法によりＲｕＯ2 から
なる導電性セラミックス膜を２００ｎｍ成膜して下部強
誘電体容量絶縁膜用電極を形成した。つぎに下部強誘電
体容量絶縁膜用電極上にＭＯＤ法によりＳｒＢｉ2 Ｔａ
2 Ｏ9 からなる強誘電体容量絶縁膜を３００ｎｍの厚さ
に形成した。成膜温度は７００℃〜８００℃の範囲とし
た。この強誘電体容量絶縁膜上に、再びゾルゲル法によ
りＲｕＯ2 からなる導電性セラミックス膜２を２００ｎ
ｍ成膜して上部強誘電体容量絶縁膜用電極を形成した。
この後、エッチングマスクを形成し、ハロゲン系化学種
を用いたＲＩＥによりパターニングして、強誘電体容量
素子を完成した。本比較例による強誘電体容量素子のＸ
線回折結果を図３に示す。図３から明らかなように、Ｓ
ｒＢｉ2 Ｔａ2 Ｏ9 およびＲｕＯ2 の他に、両者の拡散
により生成した複合酸化物Ｂｉ2 （Ｒｕ2-x Ｂｉx ）Ｏ
7 に基づくピークが観測された。また電気的特性測定の
結果、強誘電体容量素子の特性劣化が認められた。COMPARATIVE EXAMPLE A high-resistance silicon substrate was thermally oxidized to form an SiO 2 film of 300 nm.
A 200-nm-thick conductive ceramic film made of RuO 2 was formed on a substrate having a thickness of m by a sol-gel method using a sol solution containing ruthenium alkoxide to form an electrode for a lower ferroelectric capacitor insulating film. Next, SrBi 2 Ta is formed on the lower ferroelectric capacitor insulating film electrode by the MOD method.
A ferroelectric capacitor insulating film made of 2 O 9 was formed to a thickness of 300 nm. The film formation temperature was in the range of 700 ° C to 800 ° C. On the ferroelectric capacitor insulating film, a conductive ceramic film 2 made of RuO 2 was again formed by a sol-gel method for 200 nm.
Thus, an electrode for an upper ferroelectric capacitor insulating film was formed.
Thereafter, an etching mask was formed and patterned by RIE using a halogen-based chemical species to complete a ferroelectric capacitor. X of the ferroelectric capacitor according to this comparative example
FIG. 3 shows the results of the line diffraction. As is apparent from FIG.
Other rBi 2 Ta 2 O 9 and RuO 2, complex oxide was produced by diffusion of both Bi 2 (Ru 2-x Bi x) O
A peak based on 7 was observed. In addition, as a result of the measurement of the electric characteristics, it was confirmed that the characteristics of the ferroelectric capacitor were deteriorated.
【００２７】以上本発明を詳細に説明したが、本発明は
これら実施例に限定されるものではない。例えば、強誘
電体容量絶縁膜としてビスマス系層状複合化合物以外
に、鉛系、バリウム系等のペロブスカイト型複合酸化物
を用いることが可能である。導電性セラミックス膜や強
誘電体容量絶縁膜、あるいは白金薄膜の層厚や層構成も
各種変更が可能である。また強誘電体容量素子としてキ
ャパシタの他にＦＲＡＭや不揮発性メモリ、圧電素子あ
るいは光スイッチ等への適用が可能である。Although the present invention has been described in detail, the present invention is not limited to these embodiments. For example, in addition to a bismuth-based layered composite compound, a perovskite-type composite oxide such as a lead-based or barium-based composite oxide can be used as the ferroelectric capacitor insulating film. The layer thickness and layer configuration of the conductive ceramic film, the ferroelectric capacitor insulating film, or the platinum thin film can be variously changed. Further, the present invention can be applied to a ferroelectric capacitive element other than a capacitor, such as an FRAM, a nonvolatile memory, a piezoelectric element, or an optical switch.
【００２８】[0028]
【発明の効果】以上の説明から明らかなように、本発明
の強誘電体容量絶縁膜用積層電極によれば、強誘電体複
合酸化物の拡散による組成ずれや、これによる誘電体特
性の劣化を生じることのない、強誘電体容量絶縁膜用積
層電極を提供することが可能となった。本発明の強誘電
体容量絶縁膜用積層電極は、微細加工性にすぐれるの
で、高集積度の強誘電体容量素子を信頼性高く提供する
ことができる。As is clear from the above description, according to the laminated electrode for a ferroelectric capacitor insulating film of the present invention, the composition shift due to the diffusion of the ferroelectric composite oxide and the deterioration of the dielectric characteristics due to the composition shift. It has become possible to provide a laminated electrode for a ferroelectric capacitor insulating film, which does not cause the problem. Since the laminated electrode for a ferroelectric capacitor insulating film of the present invention is excellent in fine workability, a highly integrated ferroelectric capacitor element can be provided with high reliability.
【図１】本発明を適用した強誘電体容量絶縁膜用積層電
極および強誘電体容量素子の一構成例を示す概略断面図
である。FIG. 1 is a schematic cross-sectional view showing one configuration example of a laminated electrode for a ferroelectric capacitor insulating film and a ferroelectric capacitor element to which the present invention is applied.
【図２】実施例１の強誘電体容量素子のＸ線回折チャー
トである。FIG. 2 is an X-ray diffraction chart of the ferroelectric capacitor of Example 1.
【図３】比較例の強誘電体容量素子のＸ線回折チャート
である。FIG. 3 is an X-ray diffraction chart of a ferroelectric capacitor of a comparative example.
１…基板、２…導電性セラミックス膜、３…白金薄膜、
４…強誘電体容量絶縁膜、５…下部強誘電体容量絶縁膜
用積層電極、６…上部強誘電体容量絶縁膜用積層電極1 ... substrate, 2 ... conductive ceramic film, 3 ... platinum thin film,
4 ... ferroelectric capacitor insulating film, 5 ... layer electrode for lower ferroelectric capacitor insulating film, 6 ... layer electrode for upper ferroelectric capacitor insulating film
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 Ｈ０１Ｌ 27/04 Ｃ 27/10 ４５１ 29/78 ３７１ 21/8247 29/788 29/792 37/02 (72)発明者 田中 均洋 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical indication location H01L 21/822 H01L 27/04 C 27/10 451 29/78 371 21/8247 29/788 29/792 37 / 02 (72) Inventor Hitoshi Tanaka 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation
Claims (9)
部電極の少なくとも何れか一方に、導電性セラミックス
膜を用いた電極であって、 前記強誘電体容量絶縁膜と前記導電性セラミックス膜と
の間に、 白金薄膜を有することを特徴とする強誘電体容量絶縁膜
用積層電極。1. An electrode using a conductive ceramic film for at least one of an upper electrode and a lower electrode of a ferroelectric capacitor insulating film, wherein the ferroelectric capacitor insulating film, the conductive ceramic film, A laminated electrode for a ferroelectric capacitor insulating film, comprising a platinum thin film between them.
０ｎｍ以下であることを特徴とする請求項１記載の強誘
電体容量絶縁膜用積層電極。2. The thickness of the platinum thin film is not less than 5 nm and not more than 10 nm.
2. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein the thickness is 0 nm or less.
０ｎｍ以下であることを特徴とする請求項１記載の強誘
電体容量絶縁膜用積層電極。3. The thickness of the platinum thin film is 10 nm or more and 7
2. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein the thickness is 0 nm or less.
する請求項１記載の強誘電体容量絶縁膜用積層電極。4. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein said ferroelectric capacitor insulating film is made of a lead-based perovskite-type composite oxide.
特徴とする請求項１記載の強誘電体容量絶縁膜用積層電
極。5. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein the ferroelectric capacitor insulating film is made of a barium-based perovskite-type composite oxide.
求項１記載の強誘電体容量絶縁膜用積層電極。6. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein said ferroelectric capacitor insulating film is made of a bismuth-based layered composite oxide.
の強誘電体容量絶縁膜用積層電極。7. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein the conductive ceramic film is made of a rutile oxide.
請求項１記載の強誘電体容量絶縁膜用積層電極。8. The laminated electrode for a ferroelectric capacitor insulating film according to claim 1, wherein said conductive ceramic film is made of a perovskite-type composite oxide.
誘電体容量絶縁膜用積層電極を用いたことを特徴とする
強誘電体容量素子。9. A ferroelectric capacitor using the laminated electrode for a ferroelectric capacitor insulating film according to claim 1. Description:
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| JP18322996A JP3297794B2 (en) | 1996-07-12 | 1996-07-12 | Ferroelectric capacitor and semiconductor device provided with the same |
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| JP18322996A JP3297794B2 (en) | 1996-07-12 | 1996-07-12 | Ferroelectric capacitor and semiconductor device provided with the same |
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| JP3297794B2 JP3297794B2 (en) | 2002-07-02 |
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| KR100323711B1 (en) * | 1999-06-10 | 2002-02-07 | 구자홍 | method of fabricating ferroelectric memory |
| US6680251B2 (en) | 2001-03-22 | 2004-01-20 | Samsung Electronics Co., Ltd. | Methods of chemical vapor depositing ruthenium by varying chemical vapor deposition parameters |
| US6727156B2 (en) | 2000-08-25 | 2004-04-27 | Samsung Electronics Co., Ltd. | Semiconductor device including ferroelectric capacitor and method of manufacturing the same |
| WO2004079311A1 (en) * | 2003-03-07 | 2004-09-16 | Fujitsu Limited | Electromagnetic radiation sensor and method for fabricating the same |
| JP2005175457A (en) * | 2003-12-08 | 2005-06-30 | Sharp Corp | Rram memory cell electrode |
| US7338814B2 (en) | 2004-03-25 | 2008-03-04 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating ferroelectric capacitive element and ferroelectric capacitive element |
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| US6727156B2 (en) | 2000-08-25 | 2004-04-27 | Samsung Electronics Co., Ltd. | Semiconductor device including ferroelectric capacitor and method of manufacturing the same |
| US6680251B2 (en) | 2001-03-22 | 2004-01-20 | Samsung Electronics Co., Ltd. | Methods of chemical vapor depositing ruthenium by varying chemical vapor deposition parameters |
| WO2004079311A1 (en) * | 2003-03-07 | 2004-09-16 | Fujitsu Limited | Electromagnetic radiation sensor and method for fabricating the same |
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| US7338814B2 (en) | 2004-03-25 | 2008-03-04 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating ferroelectric capacitive element and ferroelectric capacitive element |
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| JP3297794B2 (en) | 2002-07-02 |
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