JPH10242326A - Multilayered wiring board - Google Patents
Multilayered wiring boardInfo
- Publication number
- JPH10242326A JPH10242326A JP9043672A JP4367297A JPH10242326A JP H10242326 A JPH10242326 A JP H10242326A JP 9043672 A JP9043672 A JP 9043672A JP 4367297 A JP4367297 A JP 4367297A JP H10242326 A JPH10242326 A JP H10242326A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- thermal expansion
- wiring board
- multilayer wiring
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、半導体素
子収納用パッケージなどに適した、少なくとも有機樹脂
を含む複合材料からなる絶縁基板を具備した多層配線基
板に関するもので、今後の実装形態であるフリップチッ
プに対応した多層配線板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having an insulating substrate made of a composite material containing at least an organic resin and suitable for, for example, a package for accommodating a semiconductor element. The present invention relates to a multilayer wiring board compatible with flip chips.
【０００２】[0002]
【従来技術】従来より、多層配線基板、例えば、半導体
素子を収納するパッケージに使用される多層配線基板と
して、高密度の配線が可能なセラミック多層配線基板が
多用されている。この多層セラミック配線基板は、アル
ミナなどの絶縁基板と、その表面に形成されたＷやＭｏ
等の高融点金属からなる配線導体とから構成されるもの
で、この絶縁基板の一部に凹部が形成され、この凹部内
に半導体素子が収納され、蓋体によって凹部を気密に封
止されるものである。2. Description of the Related Art Conventionally, ceramic multilayer wiring boards capable of high-density wiring have been frequently used as multilayer wiring boards, for example, multilayer wiring boards used for packages containing semiconductor elements. This multilayer ceramic wiring board is composed of an insulating substrate such as alumina and W or Mo formed on the surface thereof.
And a wiring conductor made of a metal having a high melting point such as the above. A concave portion is formed in a part of the insulating substrate, the semiconductor element is accommodated in the concave portion, and the concave portion is hermetically sealed by the lid. Things.
【０００３】ところが、このようなセラミック多層配線
基板の絶縁基板を構成するセラミックスは、硬くて脆い
性質を有することから、製造工程または搬送工程におい
て、セラミックスの欠けや割れ等が発生しやすく、半導
体素子の気密封止性が損なわれることがあるために歩留
りが低い等の問題があった。However, since the ceramics constituting the insulating substrate of such a ceramic multilayer wiring board has a hard and brittle property, chipping or cracking of the ceramics is liable to occur in a manufacturing process or a transporting process. There is a problem that the yield is low because the hermetic sealing property of the resin may be impaired.
【０００４】また、多層セラミック配線基板において
は、焼結前のグリーンシートにメタライズインクを印刷
して、印刷後のシートを積層して焼結させて製造される
が、その製造工程において、高温での焼成により焼成収
縮が生じるために、得られる基板に反り等の変形や寸法
のばらつき等が発生しやすいという問題があり、回路基
板の超高密度化やフリップチップ等のような基板の平坦
度の厳しい要求に対して、十分に対応できないという問
題があった。On the other hand, a multilayer ceramic wiring board is manufactured by printing metallized ink on a green sheet before sintering, laminating and sintering the printed sheet, and in the manufacturing process, it is performed at a high temperature. There is a problem that deformation such as warpage or dimensional variation is liable to occur in the obtained substrate due to firing shrinkage due to firing of the substrate. There was a problem that it was not possible to sufficiently respond to the strict requirements of the above.
【０００５】そこで、最近では、銅箔を接着した有機樹
脂を含む絶縁基板表面にエッチング法により微細な回路
を形成し、しかるのちにこの基板を積層して多層化した
プリント基板も提案されている。また、このようなプリ
ント基板においては、その強度を高めるために、有機樹
脂に対して、球状あるいは繊維状の無機質フィラーを分
散させた基板も提案されており、これらの複合材料から
なる絶縁基板上に多数の半導体素子を搭載したマルチチ
ップモジュール（ＭＣＭ）等への適用も検討されてい
る。Therefore, recently, a printed circuit board has been proposed in which a fine circuit is formed by etching on the surface of an insulating substrate containing an organic resin to which a copper foil is adhered, and then this board is laminated to form a multilayer. . In order to increase the strength of such a printed circuit board, a substrate in which a spherical or fibrous inorganic filler is dispersed in an organic resin has been proposed. Application to a multi-chip module (MCM) or the like in which a large number of semiconductor elements are mounted is also being studied.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、このよ
うな少なくとも有機樹脂を含む複合材料を絶縁基板とす
る従来のプリント基板によれば、基板の熱膨張係数が１
２〜１９×１０-6／℃程度であるのに対して、絶縁基板
上に搭載されるＳｉ系半導体素子の熱膨張係数２．５×
１０-6／℃と離れているため半導体素子との接続信頼性
が悪くなる。この傾向は、半導体素子の実装形態である
プリップチップ実装において特に顕著で、フリップチッ
プやＢＧＡ等の両方の実装に対応した多層配線プリント
基板の開発が望まれていた。However, according to a conventional printed circuit board using such a composite material containing at least an organic resin as an insulating substrate, the thermal expansion coefficient of the substrate is one.
The thermal expansion coefficient of the Si-based semiconductor element mounted on the insulating substrate is 2.5 × 10 × 10 −6 / ° C.
Since the distance is 10 −6 / ° C., the connection reliability with the semiconductor element deteriorates. This tendency is particularly remarkable in flip chip mounting, which is a mounting form of a semiconductor element, and development of a multilayer wiring printed board compatible with mounting of both flip chip and BGA has been desired.
【０００７】そこで、プリント基板の絶縁層を半導体素
子の熱膨張係数と近似させることが考えられるが、その
場合、プリント基板を、ガラス−エポキシ系複合材料等
からなるマザーボードに接続する場合、一般にそれらマ
ザーボードの熱膨張係数は、１２〜１９×１０-6／℃と
大きいために、半導体素子を搭載した多層プリント配線
基板をマザーボードに実装した場合に、マザーボードと
の接続信頼性が悪くなるという問題があった。このマザ
ーボードとの熱膨張差による接続信頼性の低下は、例え
ば、最下層の絶縁層に取り付けられたボール状の接続端
子を半田等により実装する、いわゆるボールグリッドア
レイなどの配線基板のマザーボードへの実装において特
に顕著である。Therefore, it is conceivable that the insulating layer of the printed circuit board is approximated to the thermal expansion coefficient of the semiconductor element. In this case, when connecting the printed circuit board to a motherboard made of a glass-epoxy composite material or the like, it is generally required Since the coefficient of thermal expansion of the motherboard is as large as 12 to 19 × 10 −6 / ° C., there is a problem that when a multilayer printed wiring board on which a semiconductor element is mounted is mounted on the motherboard, the connection reliability with the motherboard deteriorates. there were. The decrease in connection reliability due to the difference in thermal expansion with the motherboard is caused, for example, by mounting a ball-shaped connection terminal attached to the lowermost insulating layer by soldering or the like, a so-called ball grid array or other wiring board to the motherboard. This is particularly noticeable in implementation.
【０００８】[0008]
【課題を解決するための手段】本発明者は、上記のよう
な課題について鋭意検討した結果、少なくとも有機樹脂
を含む絶縁層と、金属からなる配線回路とを具備した多
層配線基板において、半導体素子が実装される最上層の
絶縁層の室温〜２５０℃における熱膨張係数が１０×１
０-6／℃以下で、前記最下層の室温〜２５０℃における
熱膨張係数が１０〜２５×１０-6／℃とすることによ
り、半導体素子とマザーボードの両方の接続信頼性を向
上させることができ、今後の実装形態であるフリップチ
ップ実装やＢＧＡの実装に適した多層配線基板であるこ
とを見いだし本発明に至った。Means for Solving the Problems As a result of intensive studies on the above problems, the present inventor has found that a multi-layered wiring board having at least an insulating layer containing an organic resin and a wiring circuit made of metal has a semiconductor element. Has a thermal expansion coefficient of 10 × 1 at room temperature to 250 ° C. of the uppermost insulating layer on which is mounted
When the thermal expansion coefficient of the lowermost layer at room temperature to 250 ° C. is 10 to 25 × 10 −6 / ° C. or lower at 0 −6 / ° C. or lower, the connection reliability of both the semiconductor element and the mother board can be improved. The present invention was found to be a multilayer wiring board suitable for flip-chip mounting and BGA mounting, which are future mounting forms, and led to the present invention.
【０００９】即ち、本発明の多層配線基板は、少なくと
も有機樹脂を含む絶縁層と、金属からなる配線回路とを
具備し、最上層の絶縁層の表面に半導体素子が搭載され
る多層配線基板において、前記最上層の絶縁層の室温〜
２５０℃における熱膨張係数が１０×１０-6／℃以下で
あり、且つ前記最下層の室温〜２５０℃における熱膨張
係数が１０×１０-6／℃よりも大きく、２５×１０-6／
℃以下であることを特徴とするものであり、さらには、
前記半導体素子は、前記最上層の絶縁層にフリップチッ
プ実装されること、前記最下層の絶縁層は、半田を介し
てマザーボードと接続されることを特徴とするものであ
る。That is, a multilayer wiring board of the present invention comprises an insulating layer containing at least an organic resin, and a wiring circuit made of a metal, wherein the semiconductor element is mounted on the surface of the uppermost insulating layer. , The room temperature of the uppermost insulating layer
The coefficient of thermal expansion at 250 ° C. is 10 × 10 −6 / ° C. or less, and the coefficient of thermal expansion at room temperature to 250 ° C. of the lowermost layer is greater than 10 × 10 −6 / ° C. and 25 × 10 −6 /
℃ or less, and further,
The semiconductor element is flip-chip mounted on the uppermost insulating layer, and the lowermost insulating layer is connected to a motherboard via solder.
【００１０】[0010]
【発明の実施の形態】本発明の多層配線基板は、少なく
とも有機樹脂を含む絶縁層と、例えば、銅、アルミニウ
ム、銀、金のうち少なくとも１種の低抵抗金属からなる
配線回路とを具備するものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to the present invention comprises an insulating layer containing at least an organic resin and a wiring circuit made of at least one low-resistance metal of, for example, copper, aluminum, silver or gold. Things.
【００１１】絶縁層中に含まれる有機樹脂としては、Ｐ
ＰＥ（ポリフェニレンエーテル）、ＢＴレジン（ビスマ
レイミドトリアジン）、エポキシ樹脂、ポリイミド樹
脂、フッ素樹脂、フェノール樹脂等が挙げられ、製造上
の点から、とりわけ原料として室温で液体の熱硬化性樹
脂であることが望ましい。The organic resin contained in the insulating layer is P
PE (polyphenylene ether), BT resin (bismaleimide triazine), epoxy resin, polyimide resin, fluororesin, phenol resin and the like. From the viewpoint of production, it is a thermosetting resin which is liquid as a raw material at room temperature. Is desirable.
【００１２】また、絶縁層中には、上記有機樹脂の他
に、絶縁層の強度や、熱膨張特性など種々の特性を制御
することを目的として、フィラー成分として、無機化合
物、有機繊維及び無機繊維のうち少なくとも１種を含む
ことが望ましい。これらのフィラー成分は、絶縁層中に
５０〜８０体積％の割合で含有されていることが望まし
い。この含有量によって所望の熱膨張係数の絶縁基板を
得ることができる。[0012] In addition to the organic resin, the insulating layer contains, as a filler component, an inorganic compound, an organic fiber and an inorganic fiber for the purpose of controlling various characteristics such as strength and thermal expansion characteristics of the insulating layer. It is desirable to include at least one of the fibers. It is desirable that these filler components are contained in the insulating layer at a ratio of 50 to 80% by volume. With this content, an insulating substrate having a desired coefficient of thermal expansion can be obtained.
【００１３】具体的なフィラー成分としては、Ｓｉ
Ｏ2 、Ａｌ2 Ｏ3 、ＺｒＯ2 、ＴｉＯ2、ＡｌＮ、Ｂａ
ＴｉＯ3 、ＳｒＴｉＯ3 、ゼオライト、ＣａＴｉＯ3 、
ＭｇＴｉＯ3 、ほう酸アルミニウム等の公知の材料が使
用できる。フィラーの形状は平均粒径が２０μｍ以下、
特に１０μｍ以下、最適には７μｍ以下の略球形状の粉
末の他、平均アスペクト比が２以上、特に５以上の繊維
状のものも使用できる。有機繊維としてはアラミド繊
維、セルロース繊維等があり、織布、不織布のいずれを
用いても構わない。また、無機繊維としては、ガラス繊
維が用いられ、織布、不織布のいずれを用いても構わな
い。As a specific filler component, Si
O 2 , Al 2 O 3 , ZrO 2 , TiO 2 , AlN, Ba
TiO 3 , SrTiO 3 , zeolite, CaTiO 3 ,
Known materials such as MgTiO 3 and aluminum borate can be used. The filler has an average particle size of 20 μm or less,
Particularly, in addition to a substantially spherical powder having a particle size of 10 μm or less, optimally 7 μm or less, a fibrous powder having an average aspect ratio of 2 or more, particularly 5 or more can be used. Organic fibers include aramid fibers and cellulose fibers, and any of woven and non-woven fabrics may be used. Glass fibers are used as the inorganic fibers, and any of a woven fabric and a nonwoven fabric may be used.
【００１４】次に、本発明の多層配線基板の一例を図１
に示す。図１の多層配線基板によれば、絶縁層１ａ〜１
ｄが複数層積層されて絶縁基板１を構成しており、絶縁
基板１の最上面、絶縁基板内部、さらには、絶縁基板の
底面には、銅、アルミニウム、銀、金のうち少なくとも
１種の低抵抗金属からなる配線回路２が配設されてい
る。この配線回路２は、金属箔や、これらの低抵抗金属
を含むペーストを塗布して形成されたものである。Next, an example of the multilayer wiring board of the present invention is shown in FIG.
Shown in According to the multilayer wiring board of FIG.
The insulating substrate 1 is formed by laminating a plurality of layers d. At least one of copper, aluminum, silver, and gold is provided on the uppermost surface of the insulating substrate 1, the inside of the insulating substrate, and the bottom surface of the insulating substrate. A wiring circuit 2 made of a low-resistance metal is provided. The wiring circuit 2 is formed by applying a metal foil or a paste containing these low-resistance metals.
【００１５】そして、配線基板Ａにおける最上層の絶縁
層１ａの表面には、半導体素子３がを接続するための配
線回路２ａが形成されており、この配線回路２ａは、半
導体素子３と電気的に接続される。図１の例では、半導
体素子３がフリップチップ実装された構造を示すもので
あり、半導体素子３の電極（図示せず）が、半田４を介
して配線回路２ａと電気的に接続される。A wiring circuit 2a for connecting the semiconductor element 3 is formed on the surface of the uppermost insulating layer 1a of the wiring board A. The wiring circuit 2a is electrically connected to the semiconductor element 3. Connected to. The example of FIG. 1 shows a structure in which the semiconductor element 3 is flip-chip mounted, and electrodes (not shown) of the semiconductor element 3 are electrically connected to the wiring circuit 2 a via the solder 4.
【００１６】一方、絶縁基板における最下層の絶縁層１
ｄの表面には、マザーボード５と接続するための接続端
子６が形成されている。なお、接続端子６は、絶縁基板
の最上面に形成された配線回路２ａと、内部に形成され
た配線回路を通じて電気的に接続されている。図１の配
線基板では、ボールグリッドアレイの例を示すもので、
この接続端子は６は、ボール状の高融点半田等から構成
され、マザーボード５と低融点半田により接続される。On the other hand, the lowermost insulating layer 1 on the insulating substrate
A connection terminal 6 for connecting to the motherboard 5 is formed on the surface of d. The connection terminal 6 is electrically connected to a wiring circuit 2a formed on the uppermost surface of the insulating substrate through a wiring circuit formed inside. 1 shows an example of a ball grid array,
The connection terminal 6 is formed of a ball-shaped high melting point solder or the like, and is connected to the motherboard 5 by a low melting point solder.
【００１７】本発明によれば、図１に示されるような多
層配線基板において、最上層の絶縁層１ａの室温〜２５
０℃における熱膨張係数を１０×１０-6／℃以下、特に
２〜７×１０-6／℃以下とすることが重要である。この
熱膨張係数が１０×１０-6／℃よりも大きいと、フリッ
プチップ実装された半導体素子との接続信頼性が低下す
る。According to the present invention, in the multilayer wiring board as shown in FIG.
It is important that the coefficient of thermal expansion at 0 ° C. be 10 × 10 −6 / ° C. or less, especially 2 to 7 × 10 −6 / ° C. or less. If the coefficient of thermal expansion is larger than 10 × 10 −6 / ° C., the connection reliability with the semiconductor element mounted on the flip chip is reduced.
【００１８】なお、半導体素子をフリップチップ実装す
る場合、実装面は精度の高い平坦度が要求される。この
ような平坦度を実現する上で、半導体素子が搭載される
絶縁層１ａ表面に形成される配線回路２ａは、図１に示
されるように、絶縁層１ａ表面に埋め込まれた状態であ
ることが望ましい。このような配線回路２ａの埋め込み
は、絶縁層表面に配線回路を形成する際、あるいは形成
後に圧力を印加して強制的に埋め込み処理すればよい。When a semiconductor element is flip-chip mounted, the mounting surface is required to have high precision and flatness. In order to realize such flatness, the wiring circuit 2a formed on the surface of the insulating layer 1a on which the semiconductor element is mounted must be embedded in the surface of the insulating layer 1a as shown in FIG. Is desirable. The embedding of the wiring circuit 2a may be performed when a wiring circuit is formed on the surface of the insulating layer or by applying a pressure after the formation to forcibly perform the embedding process.
【００１９】さらに、本発明によれば、配線基板の最下
層１ｄの室温〜２５０℃における熱膨張係数を１０×１
０-6／℃よりも大きく、２５×１０-6／℃以下、特に１
２〜２０×１０-6／℃とすることが重要である。これ
は、本発明の配線基板をマザーボード等の外部電気回路
基板に実装した場合の接続信頼性を高めるものであり、
最下層の熱膨張係数が１０×１０-6／℃以下、あるいは
２５×１０-6／℃よりも大きいと、マザーボードとの熱
膨張差が大きくなり、接続信頼性が低下するためであ
る。Further, according to the present invention, the thermal expansion coefficient of the lowermost layer 1d of the wiring board at room temperature to 250.degree.
Greater than 0 -6 / ° C and less than 25 × 10 -6 / ° C, especially 1
It is important to make it 2 to 20 × 10 −6 / ° C. This is to improve the connection reliability when the wiring board of the present invention is mounted on an external electric circuit board such as a motherboard,
If the coefficient of thermal expansion of the lowermost layer is 10 × 10 −6 / ° C. or less, or greater than 25 × 10 −6 / ° C., the difference in thermal expansion from the motherboard increases, and the connection reliability decreases.
【００２０】また、最上層の絶縁層１ａと最下層の絶縁
層１ｄとの間に存在する絶縁層１ｂ、１ｃの熱膨張係数
は、最上層の絶縁層１ａから最下層の絶縁層１ｄにかけ
て次第に熱膨張係数が大きくなるように変化させること
が望ましい。これは、最上層の絶縁層１ａと最下層の絶
縁層１ｄとの熱膨張差による配線基板内での熱応力の発
生を抑制し多層配線構造の信頼性を高めるためである。The thermal expansion coefficients of the insulating layers 1b and 1c existing between the uppermost insulating layer 1a and the lowermost insulating layer 1d gradually increase from the uppermost insulating layer 1a to the lowermost insulating layer 1d. It is desirable to change so that the coefficient of thermal expansion becomes large. This is to suppress the occurrence of thermal stress in the wiring board due to the difference in thermal expansion between the uppermost insulating layer 1a and the lowermost insulating layer 1d, thereby improving the reliability of the multilayer wiring structure.
【００２１】絶縁層の熱膨張係数の制御は、例えば、絶
縁層を構成する有機樹脂が、一般に熱膨張係数が５０〜
１００×１０-6／℃以上と高いことから、絶縁層中に熱
膨張係数の小さいフィラー成分を配合し、その配合量を
調整することにより、任意の熱膨張係数の絶縁層を作製
することができる。特に、熱膨張係数の小さいフィラー
として、溶融ＳｉＯ2 、Ａｌ2 Ｏ3 、ＢａＴｉＯ3 、Ｃ
ａＴｉＯ3 、ＭｇＴｉＯ3 等が好適である。これらのフ
ィラーは、いずれもそれ自体で、１０×１０-6／℃以下
の熱膨張係数を有することから、有機樹脂との組み合わ
せにより、熱膨張係数の制御が容易である。The control of the thermal expansion coefficient of the insulating layer is performed, for example, in such a manner that the organic resin forming the insulating layer generally has a thermal expansion coefficient of 50 to 50.
Since it is as high as 100 × 10 −6 / ° C. or more, it is possible to prepare an insulating layer having an arbitrary coefficient of thermal expansion by mixing a filler component having a small coefficient of thermal expansion into the insulating layer and adjusting the amount thereof. it can. In particular, as fillers having a small coefficient of thermal expansion, molten SiO 2 , Al 2 O 3 , BaTiO 3 , C
aTiO 3, MgTiO 3 and the like. Since these fillers each have a thermal expansion coefficient of 10 × 10 −6 / ° C. or less, the thermal expansion coefficient can be easily controlled by combination with an organic resin.
【００２２】従って、絶縁基板を同一の有機樹脂とフィ
ラー成分によって構成する場合、半導体素子が搭載され
る最上層の絶縁層中の低熱膨張のフィラー量を最も多く
し、最下層の絶縁層の前記フィラー量を少なく設定すれ
ばよく、さらには、最上層の絶縁層と最下層の絶縁層間
の絶縁層におけるフィラー量を徐々に変化させることに
より、熱膨張係数を徐々に変化させることが可能とな
る。Therefore, when the insulating substrate is made of the same organic resin and filler component, the amount of low thermal expansion filler in the uppermost insulating layer on which the semiconductor element is mounted is maximized, and It is sufficient to set the filler amount to be small, and furthermore, it is possible to gradually change the thermal expansion coefficient by gradually changing the filler amount in the insulating layer between the uppermost insulating layer and the lowermost insulating layer. .
【００２３】このような多層配線基板は、例えば次のよ
うに作製される。まず、絶縁層を形成するに、目的とす
る熱膨張係数を得ることのできる、無機質フィラーに液
状の有機樹脂に加えた絶縁性組成物を、混練機（ニー
ダ）や３本ロールなどの混練機等の手段によって十分に
混合する。十分に混合されたものを圧延法、押し出し
法、ドクターブレード法などの周知の樹脂成形方法によ
り、シート状に成形して絶縁層を得る。Such a multilayer wiring board is manufactured, for example, as follows. First, to form an insulating layer, a kneading machine such as a kneader or a three-roller is used to form an insulating composition obtained by adding a liquid organic resin to an inorganic filler, which can obtain a desired coefficient of thermal expansion. Mix well by such means. A well-mixed product is formed into a sheet by a well-known resin molding method such as a rolling method, an extrusion method, a doctor blade method, etc. to obtain an insulating layer.
【００２４】この時、有機樹脂を半硬化させておくのが
望ましく、半硬化には、有機樹脂は熱可塑性樹脂の場合
には、加熱下で混合したものを冷却し、熱硬化性樹脂の
場合には、完全固化するに十分な温度よりもやや低い温
度に加熱すればよい。また、フィラー成分として有機繊
維及び無機繊維を含む場合、織布または不織布にワニス
状の樹脂を含浸、乾燥させ半硬化のプリプレグを得る。At this time, it is desirable that the organic resin is semi-cured. For the semi-curing, in the case where the organic resin is a thermoplastic resin, the organic resin is cooled under heating, and the mixture is cooled. In this case, heating may be performed to a temperature slightly lower than a temperature sufficient for complete solidification. When organic fibers and inorganic fibers are included as a filler component, a woven or nonwoven fabric is impregnated with a varnish-like resin and dried to obtain a semi-cured prepreg.
【００２５】次に、上記のようにして作製した絶縁層に
対して、所望により打ち抜き法やレーザー加工によりビ
アホールを形成して導体ペーストを充填する。導体ペー
スト中に配合される金属粉末としては、銅、アルミニウ
ム、銀、金のうち少なくとも１種の低抵抗金属からなる
ことが望ましく、有機溶剤とバインダーを添加しペース
トを得ることができる。Next, the insulating layer formed as described above is filled with a conductive paste by forming a via hole by punching or laser processing as required. The metal powder to be blended in the conductor paste is desirably made of at least one low-resistance metal among copper, aluminum, silver, and gold, and a paste can be obtained by adding an organic solvent and a binder.
【００２６】そして、この半硬化状の絶縁層表面に配線
回路を形成する。配線回路の形成には、銅等の金属箔を
絶縁層に接着剤で張りつけた後に、回路パターンのレジ
ストを形成して酸等によって不要な部分の金属をエッチ
ング除去するか、予め打ち抜き加工した金属箔を張りつ
ける。他の方法としては、絶縁層の表面に銅、アルミニ
ウム、金、銀などの金属粉末を含む導体ペーストを回路
パターンにスクリーン印刷や、フォトレジスト法等によ
って形成した後、乾燥して加圧し、配線回路を絶縁層表
面に埋め込むことができる。また、配線回路をフィル
ム、ガラス、金属板上にメッキ、金属箔を形成し、これ
をエッチング等により回路パターンを形成し、絶縁層上
に加圧しながら転写することにより、配線回路を絶縁層
表面に埋め込むことができる。Then, a wiring circuit is formed on the surface of the semi-cured insulating layer. To form a wiring circuit, a metal foil such as copper is adhered to an insulating layer with an adhesive, and then a resist for a circuit pattern is formed and unnecessary metal is removed by etching with an acid or the like, or a metal punched in advance is used. Attach foil. As another method, a conductor paste containing a metal powder such as copper, aluminum, gold, and silver is formed on the surface of the insulating layer by screen printing or a photoresist method, and then dried and pressed to form a wiring. The circuit can be embedded on the surface of the insulating layer. Also, the wiring circuit is plated on a film, glass, or metal plate, a metal foil is formed, a circuit pattern is formed by etching or the like, and the wiring circuit is transferred onto the insulating layer while being pressed. Can be embedded in
【００２７】そして、上記に示すように作製した絶縁層
を所望の枚数積層し、１５０〜３００℃で硬化し接着さ
せることにより、多層配線基板を作製できる。Then, a desired number of the insulating layers manufactured as described above are laminated, cured at 150 to 300 ° C. and adhered, whereby a multilayer wiring board can be manufactured.
【００２８】このように、少なくとも有機樹脂を含む絶
縁層と低抵抗金属からなる配線回路とを具備した多層配
線基板において、半導体素子が搭載される最上層の絶縁
層の熱膨張係数およびマザーボードに実装される最下層
の絶縁層の熱膨張係数を前述したように制御することに
より、多層配線基板の半導体素子とマザーボードの両方
の接続信頼性を向上させることができる。それにより、
半導体素子のフリップチップ実装や、ボールグリッドア
レイ型の実装に適した多層配線基板を作製することがで
きる。Thus, in a multilayer wiring board having at least an insulating layer containing an organic resin and a wiring circuit made of a low-resistance metal, the thermal expansion coefficient of the uppermost insulating layer on which a semiconductor element is mounted and the mounting on a motherboard By controlling the thermal expansion coefficient of the lowermost insulating layer as described above, the connection reliability of both the semiconductor element and the mother board of the multilayer wiring board can be improved. Thereby,
A multilayer wiring board suitable for flip-chip mounting of a semiconductor element or mounting of a ball grid array type can be manufactured.
【００２９】[0029]
【実施例】本発明の多層配線基板を製造するために、無
機フィラーとして平均粒径が５μｍの溶融シリカを５０
〜８０体積％、有機樹脂としてＢＴレジン、ポリイミド
樹脂、熱硬化型ＰＰＥ（ポリフェニレンエーテル）樹脂
を５０〜２０体積％の範囲で表１に示すような熱膨張係
数になるように秤量し、これに溶媒として酢酸ブチルを
加え、さらに有機樹脂の硬化を促進させるための触媒を
添加し、攪拌翼が公転および自転する攪拌機により１時
間混合した後、スラリーを調製した。このスラリーをド
クターブレード法により、厚み２００μｍのシート状に
成形して絶縁層を形成した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to manufacture the multilayer wiring board of the present invention, 50 μm of fused silica having an average particle size of 5 μm was used as an inorganic filler.
BT resin, polyimide resin, and thermosetting PPE (polyphenylene ether) resin as an organic resin are weighed in a range of 50 to 20% by volume so as to have a thermal expansion coefficient as shown in Table 1, Butyl acetate was added as a solvent, a catalyst for accelerating the curing of the organic resin was further added, and the mixture was mixed for 1 hour by a stirrer in which a stirring blade revolved and rotated, and then a slurry was prepared. This slurry was formed into a sheet having a thickness of 200 μm by a doctor blade method to form an insulating layer.
【００３０】また、有機繊維としてアラミド繊維、無機
繊維としてガラス繊維にＢＴレジンを５０体積％含浸乾
燥させ厚さ２００μｍのプリプレグの絶縁層を作製した
これらの絶縁層を１５０ｍｍ□にカットし、ＣＯ2 レー
ザーによりビアホールを形成した。この絶縁層に銅を主
成分とする導体ペーストをスクリーン印刷法により線幅
５０μｍ、回路間距離５０μｍの回路を形成し、ビアホ
ールにも同様の導体ペーストを埋め込んだ。Further, cut aramid fibers as organic fibers, these insulating layers to form a dielectric layer of the prepreg having a thickness of 200μm impregnated dried 50% by volume of BT resin glass fiber as the inorganic fibers to 150 mm □, CO 2 Via holes were formed by laser. A circuit having a line width of 50 μm and an inter-circuit distance of 50 μm was formed by screen printing using a conductor paste containing copper as a main component on the insulating layer, and the same conductor paste was embedded in the via holes.
【００３１】このようにして得られた絶縁層を最上層お
よび最下層の絶縁層の熱膨張係数が表１であり、最上層
と最下層との間の絶縁層の熱膨張係数が徐々に変化する
ように絶縁層を選択し、合計８層を積層し、２００℃、
３０分、窒素中で有機樹脂を硬化し、多層配線基板を得
た。なお、絶縁層の熱膨張係数はＴＭＡ法により測定し
た。そして、多層配線基板の最下層の絶縁層表面には、
共晶半田からなるボール状の接続端子を多数半田接続し
た。The thermal expansion coefficients of the uppermost and lowermost insulating layers obtained in this manner are shown in Table 1, and the thermal expansion coefficient of the insulating layer between the uppermost layer and the lowermost layer changes gradually. Insulation layer is selected so that a total of 8 layers are laminated,
The organic resin was cured in nitrogen for 30 minutes to obtain a multilayer wiring board. The coefficient of thermal expansion of the insulating layer was measured by a TMA method. Then, on the surface of the lowermost insulating layer of the multilayer wiring board,
A large number of ball-shaped connection terminals made of eutectic solder were connected by soldering.
【００３２】そして、多層配線板の最上層の絶縁層表面
に形成した配線回路にＳｉ半導体チップを半田によりフ
リップチップ実装し、チップを実装した多層配線基板を
ＦＲ−４（エポキシ樹脂−ガラス布複合材料）のマザー
ボードの電極に、ボール状接続端子を半田付け実装し
た。Then, a Si semiconductor chip is flip-chip mounted on a wiring circuit formed on the uppermost insulating layer surface of the multilayer wiring board by soldering, and the multilayer wiring board on which the chip is mounted is FR-4 (epoxy resin-glass cloth composite). The ball-shaped connection terminals were soldered and mounted on the electrodes of the motherboard of (material).
【００３３】次に、各試料について２０個につき、−４
０〜１２０℃の温度サイクル試験を１０００サイクル行
い、電気的接続が変化しないものを良品、電気的接続が
変化したものを不良品とし、不良率を表１に示した。Next, for each of the 20 samples, -4
1000 cycles of a temperature cycle test at 0 to 120 ° C. were performed, and those having no change in electrical connection were determined to be good products, and those having changed electrical connection were determined to be defective products.
【００３４】[0034]
【表１】 [Table 1]
【００３５】表１に示すように、多層配線基板の最上層
の室温〜２５０℃における熱膨張係数が１０×１０-6／
℃以下、最下層の室温〜２５０℃における熱膨張係数が
１０×１０×１０-6／℃を越え、２５×１０-6／℃以下
とするとすることによりフリップチップ実装及びＢＧＡ
によるマザーボードへの表面実装に適した多層配線基板
を得ることができた。As shown in Table 1, the uppermost layer of the multilayer wiring board has a coefficient of thermal expansion from room temperature to 250 ° C. of 10 × 10 -6 /
Flip chip mounting and BGA by setting the thermal expansion coefficient at room temperature to 250 ° C. of the lowermost layer to be lower than 25 × 10 −6 / ° C. and lower than 10 × 10 × 10 −6 / ° C.
A multi-layer wiring board suitable for surface mounting on a motherboard was obtained.
【００３６】[0036]
【発明の効果】以上詳述したように、本発明によれば、
少なくとも有機樹脂を含む絶縁層と銅、アルミニウム、
銀、金のうち少なくとも１種の低抵抗金属からなる配線
回路とを具備した多層配線基板において、最上層の絶縁
層の熱膨張係数と最下層の熱膨張係数を制御することに
より、半導体素子とマザーボードの両方に対する接続信
頼性を向上させることができ、半導体素子のフリップチ
ップ実装やボールグリッドアレイによる配線基板の実装
において、長期にわたり接続信頼性に優れた多層配線基
板を提供することができる。As described in detail above, according to the present invention,
Insulating layer containing at least organic resin and copper, aluminum,
In a multilayer wiring board comprising a wiring circuit made of at least one low-resistance metal of silver and gold, the semiconductor element is controlled by controlling the thermal expansion coefficient of the uppermost insulating layer and the thermal expansion coefficient of the lowermost layer. The reliability of connection to both the motherboards can be improved, and a multilayer wiring board having excellent connection reliability can be provided for a long time in flip-chip mounting of semiconductor elements or mounting of a wiring board by a ball grid array.
【図１】本発明の多層配線基板の構造を説明するための
概略図である。FIG. 1 is a schematic diagram for explaining the structure of a multilayer wiring board according to the present invention.
【符号の説明】 Ａ 多層配線基板 １ 絶縁基板 １ａ〜１ｄ 絶縁層 ２ 配線回路 ３ 半導体素子 ４ 半田 ５ マザーボード ６ 接続端子[Description of Symbols] A Multilayer wiring board 1 Insulating board 1a-1d Insulating layer 2 Wiring circuit 3 Semiconductor element 4 Solder 5 Motherboard 6 Connection terminal
Claims (3)
からなる配線回路とを具備し、最上層の絶縁層の表面に
半導体素子が搭載される多層配線基板において、前記最
上層の絶縁層の室温〜２５０℃における熱膨張係数が１
０×１０-6／℃以下であり、且つ前記最下層の室温〜２
５０℃における熱膨張係数が１０×１０-6／℃よりも大
きく、２５×１０-6／℃以下であることを特徴とする多
層配線基板。1. A multilayer wiring board comprising: an insulating layer containing at least an organic resin; and a wiring circuit made of metal, wherein a semiconductor element is mounted on a surface of an uppermost insulating layer. The coefficient of thermal expansion between room temperature and 250 ° C is 1
0 × 10 −6 / ° C. or less, and room temperature of the lowermost layer to 2
A multilayer wiring board having a thermal expansion coefficient at 50 ° C. of more than 10 × 10 −6 / ° C. and 25 × 10 −6 / ° C. or less.
フリップチップ実装される請求項１記載の多層配線基
板。2. The multilayer wiring board according to claim 1, wherein said semiconductor element is flip-chip mounted on said uppermost insulating layer.
し、該接続端子が、半田を介してマザーボードと接続さ
れる請求項１記載の多層配線基板。3. The multilayer wiring board according to claim 1, wherein the lowermost insulating layer has connection terminals, and the connection terminals are connected to a mother board via solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04367297A JP3537620B2 (en) | 1997-02-27 | 1997-02-27 | Multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04367297A JP3537620B2 (en) | 1997-02-27 | 1997-02-27 | Multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242326A true JPH10242326A (en) | 1998-09-11 |
| JP3537620B2 JP3537620B2 (en) | 2004-06-14 |
Family
ID=12670343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04367297A Expired - Fee Related JP3537620B2 (en) | 1997-02-27 | 1997-02-27 | Multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3537620B2 (en) |
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| JP2003101175A (en) * | 2001-09-25 | 2003-04-04 | Hitachi Chem Co Ltd | Semiconductor mounting substrate and semiconductor package |
| JP2003101176A (en) * | 2001-09-26 | 2003-04-04 | Hitachi Chem Co Ltd | Compound material for wiring board and production method therefor |
| JP2005223226A (en) * | 2004-02-06 | 2005-08-18 | Murata Mfg Co Ltd | Composite multilayer substrate |
| WO2006087769A1 (en) * | 2005-02-15 | 2006-08-24 | Fujitsu Limited | Package mounted module and package board module |
| JP2006237324A (en) * | 2005-02-25 | 2006-09-07 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| JP2008085089A (en) * | 2006-09-28 | 2008-04-10 | Matsushita Electric Ind Co Ltd | Resin wiring board and semiconductor device |
| JP2007227967A (en) * | 2007-04-27 | 2007-09-06 | Hitachi Ltd | Semiconductor module, and method of manufacturing same |
| JP2011029623A (en) * | 2009-06-29 | 2011-02-10 | Murata Mfg Co Ltd | Substrate with built-in component, module component using the substrate with built-in component, and method for manufacturing substrate with built-in component |
| JP2010251783A (en) * | 2010-06-14 | 2010-11-04 | Hitachi Chem Co Ltd | Substrate for mounting semiconductor and semiconductor package |
| JP2010258462A (en) * | 2010-06-14 | 2010-11-11 | Hitachi Chem Co Ltd | Composite material for wiring board and production method thereof |
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