JPH09237972A - Multilayered wiring board - Google Patents
Multilayered wiring boardInfo
- Publication number
- JPH09237972A JPH09237972A JP8042523A JP4252396A JPH09237972A JP H09237972 A JPH09237972 A JP H09237972A JP 8042523 A JP8042523 A JP 8042523A JP 4252396 A JP4252396 A JP 4252396A JP H09237972 A JPH09237972 A JP H09237972A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- thermal expansion
- wiring board
- inorganic filler
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁層が無機質フ
ィラーと有機樹脂との複合材料からなり、半導体用パッ
ケージや混成集積回路基板等に用いられる多層配線基板
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having an insulating layer made of a composite material of an inorganic filler and an organic resin, which is used for a semiconductor package, a hybrid integrated circuit board or the like.
【０００２】[0002]
【従来技術】従来より、配線基板、例えば、半導体素子
を収納するパッケージに使用される配線基板として、比
較的高密度の配線が可能な多層セラミック配線基板が多
用されている。この多層セラミック配線基板は、アルミ
ナなどの絶縁基板と、その表面に形成されたＷやＭｏ等
の高融点金属からなる配線導体とから構成されるもの
で、この絶縁基板の一部に凹部が形成され、この凹部内
に半導体素子が収納され、蓋体によって凹部を気密に封
止されるものである。2. Description of the Related Art Hitherto, as a wiring board, for example, a wiring board used for a package accommodating a semiconductor element, a multilayer ceramic wiring board capable of relatively high-density wiring has been widely used. This multilayer ceramic wiring board is composed of an insulating substrate such as alumina and a wiring conductor made of a high melting point metal such as W or Mo formed on the surface thereof, and a concave portion is formed in a part of the insulating substrate. The semiconductor element is housed in the recess, and the recess is hermetically sealed by the lid.
【０００３】ところが、このような多層セラミック配線
基板を構成するセラミックスは、硬くて脆い性質を有す
ることから、製造工程または搬送工程において、セラミ
ックスの欠けや割れ等が発生しやすく、半導体素子の気
密封止性が損なわれることがあるために歩留りが低い等
の問題があった。However, since the ceramics constituting such a multilayer ceramic wiring board are hard and brittle, they are likely to be chipped or cracked during the manufacturing process or the transporting process, and the hermetic sealing of the semiconductor element is difficult. There is a problem that yield is low because stopping performance may be impaired.
【０００４】また、多層セラミック配線基板において
は、焼結前のグリーンシートにメタライズインクを印刷
して、印刷後のシートを積層して焼結させて製造される
が、その製造工程において、高温での焼成により焼成収
縮が生じるために、得られる基板に反り等の変形や寸法
のばらつき等が発生しやすいという問題があり、回路基
板の超高密度化やフリップチップ等のような基板の平坦
度の厳しい要求に対して、十分に対応できないという問
題があった。On the other hand, a multilayer ceramic wiring board is manufactured by printing metallized ink on a green sheet before sintering, laminating and sintering the printed sheet, and in the manufacturing process, it is performed at a high temperature. There is a problem that deformation such as warpage or dimensional variation is liable to occur in the obtained substrate due to firing shrinkage due to firing of the substrate. There was a problem that it was not possible to sufficiently respond to the strict requirements of the above.
【０００５】そこで、最近では、プリント基板では銅箔
を接着した基板表面にエッチング法により微細な回路を
形成し、しかるのちにこの基板を積層して多層化した基
板も提案されている。また、このようなプリント基板に
おいては、その強度を高めるために、有機樹脂に対し
て、球状あるいは繊維状の無機質フィラーを分散させた
基板も提案されており、これらの複合材料からなる絶縁
基板上に多数の半導体素子を搭載したマルチチップモジ
ュール（ＭＣＭ）等への適用も検討されている。Therefore, recently, a printed circuit board has been proposed in which a fine circuit is formed by etching on the surface of a board to which a copper foil is adhered, and then the boards are laminated to form a multilayer. In order to increase the strength of such a printed circuit board, a substrate in which a spherical or fibrous inorganic filler is dispersed in an organic resin has been proposed. Application to a multi-chip module (MCM) or the like in which a large number of semiconductor elements are mounted is also being studied.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、このよ
うな有機樹脂と無機質フィラーとの複合材料からなる絶
縁基板によれば、複合材料の一成分である有機樹脂の熱
膨張係数が約１００×１０-6／℃であるのに対して、絶
縁基板上に搭載される半導体素子の熱膨張係数は２．５
×１０-6／℃と大きく異なる。そのために、半導体素子
を搭載した基板に対して、繰り返し熱履歴が負荷される
と、半導体素子と基板との間に発生する応力によって、
半導体素子の搭載状態が劣化し、長期安定性に欠ける等
の問題があった。However, according to the insulating substrate made of the composite material of the organic resin and the inorganic filler, the thermal expansion coefficient of the organic resin which is one component of the composite material is about 100 × 10 −. 6 / ℃, the thermal expansion coefficient of the semiconductor element mounted on the insulating substrate is 2.5
It is significantly different from × 10 -6 / ° C. Therefore, when the thermal history is repeatedly applied to the substrate on which the semiconductor element is mounted, the stress generated between the semiconductor element and the substrate causes
There is a problem that the mounting state of the semiconductor element is deteriorated and lacks long-term stability.
【０００７】また、絶縁基板の熱膨張係数を半導体素子
に整合することも考えられるが、絶縁基板としての性能
上、電気絶縁性、誘電率、誘電損失あるいは強度などの
特性や、内部に配設された導体回路やスルーホール等と
の熱膨張のマッチングなどの特性を満足させることも必
要であり、最近ではコンデンサやフィルターとしての機
能を内蔵させる場合もあり、これら絶縁基板として要求
される種々の特性を満足しつつ熱膨張係数を半導体素子
に整合するのは、材料設計上も非常に難しい問題であっ
た。It is also possible to match the coefficient of thermal expansion of the insulating substrate with the semiconductor element, but in terms of performance as an insulating substrate, characteristics such as electrical insulation, dielectric constant, dielectric loss or strength, and the internal arrangement. It is also necessary to satisfy the characteristics such as matching of thermal expansion with the conductor circuits and through holes, etc., and recently, there are cases where functions such as capacitors and filters are built in. Matching the coefficient of thermal expansion to the semiconductor element while satisfying the characteristics has been a very difficult problem in terms of material design.
【０００８】[0008]
【課題を解決するための手段】本発明者らは、上記のよ
うな問題点について鋭意検討した結果、無機質フィラー
と有機樹脂との複合材料からなる絶縁層と、導体回路と
が多層に積層された多層配線基板において、その最外層
のみを低熱膨張化させることにより、配線基板の絶縁層
としての種々の要求特性を満足しつつ、半導体素子との
熱膨張特性の整合を図ることができることを知見し本発
明に至った。Means for Solving the Problems As a result of intensive studies on the above problems, the present inventors have found that an insulating layer made of a composite material of an inorganic filler and an organic resin and a conductor circuit are laminated in multiple layers. In a multi-layered wiring board, it was found that by reducing the thermal expansion of only the outermost layer, the thermal expansion characteristics of the semiconductor element can be matched while satisfying various required characteristics as the insulating layer of the wiring board. The present invention has been achieved.
【０００９】即ち、本発明の多層配線基板は、無機質フ
ィラーと有機樹脂とを均一に混合した複合材料よりなる
絶縁層と低抵抗金属からなる導体回路とが多層に積層さ
れてなる多層配線基板であって、最外層の絶縁層の熱膨
張係数が内部の絶縁層の熱膨張係数よりも小さいことを
特徴とするものであり、具体的には、前記絶縁層中に低
熱膨張の無機質フィラーを含み、前記最外層の絶縁層中
の前記低熱膨張の無機質フィラー含有量が、前記内部の
絶縁層中のそれよりも多いものである。また、前記低熱
膨張の無機質フィラーが、Ｓｉを含む酸化物からなるこ
とが望ましい。That is, the multilayer wiring board of the present invention is a multilayer wiring board in which an insulating layer made of a composite material in which an inorganic filler and an organic resin are uniformly mixed and a conductor circuit made of a low resistance metal are laminated in multiple layers. It is characterized in that the coefficient of thermal expansion of the outermost insulating layer is smaller than the coefficient of thermal expansion of the inner insulating layer, specifically, contains a low thermal expansion inorganic filler in the insulating layer. The content of the low thermal expansion inorganic filler in the outermost insulating layer is higher than that in the inner insulating layer. Further, it is desirable that the low thermal expansion inorganic filler is made of an oxide containing Si.
【００１０】さらに、室温から２５０℃における熱膨張
係数が前記最外層の絶縁層が１０〜６０×１０-6／℃で
あり、前記内部の絶縁層が３０〜１００×１０-6／℃で
あり、前記最外層の絶縁層の上面に半導体素子が搭載さ
れることを特徴とするものである。Further, the coefficient of thermal expansion from room temperature to 250 ° C. is 10 to 60 × 10 −6 / ° C. in the outermost insulating layer and 30 to 100 × 10 −6 / ° C. in the inner insulating layer. A semiconductor element is mounted on the upper surface of the outermost insulating layer.
【００１１】[0011]
【作用】本発明の高密度多層配線基板は、フィラーと樹
脂とを均一に混合した複合材料よりなる基板表面に、
銅、アルミニウム等低抵抗金属よりなる回路を印刷等の
方法で形成した回路基板を積層し、最外層に内部の絶縁
層よりも低膨張係数の絶縁層を積層することにより、絶
縁基板としての電気的特性や内部導体回路等とのマッチ
ングを図るために高熱膨張の絶縁基板を用いた場合にお
いても、半導体素子との熱膨張係数の整合を行うことが
できるために、過酷な熱サイクルが付与された場合にお
いても半導体素子と配線基板との間に発生する応力によ
って、半導体素子の搭載状態が劣化することがなく長期
安定性が得られる。The high-density multi-layer wiring board of the present invention has a substrate surface made of a composite material in which a filler and a resin are uniformly mixed,
By laminating a circuit board on which a circuit made of low resistance metal such as copper or aluminum is formed by a method such as printing, and by laminating an insulating layer having a lower expansion coefficient than the internal insulating layer on the outermost layer Even if an insulating substrate with high thermal expansion is used to achieve matching with the electrical characteristics and internal conductor circuits, etc., the thermal expansion coefficient can be matched with the semiconductor element, so a severe thermal cycle is applied. Even in such a case, the stress generated between the semiconductor element and the wiring substrate does not deteriorate the mounting state of the semiconductor element, and long-term stability can be obtained.
【００１２】これにより、多層配線基板における回路の
超微細化、精密化の要求に応えつつ、過酷な条件で使用
されるような携帯情報端末等の小型情報機器の基板やメ
モリーカード等小型薄膜基板等としてその信頼性を高め
ることができる。As a result, while satisfying the demands for ultra-miniaturization and precision of the circuit in the multilayer wiring board, the board for small-sized information equipment such as a portable information terminal which is used under severe conditions and the small-sized thin-film board such as a memory card. As a result, the reliability can be increased.
【００１３】[0013]
【発明の実施の形態】本発明の多層配線基板の概略図を
図１に示した。本発明の多層配線基板１は、複数の絶縁
層２と、導体回路３をと具備し、導体回路３は、絶縁層
２間、または絶縁層２の表面に形成されている。FIG. 1 is a schematic view of a multilayer wiring board according to the present invention. The multilayer wiring board 1 of the present invention includes a plurality of insulating layers 2 and a conductive circuit 3, and the conductive circuits 3 are formed between the insulating layers 2 or on the surface of the insulating layer 2.
【００１４】本発明によれば、上記絶縁層は、無機質フ
ィラーと有機樹脂との複合材料からなり、無機質フィラ
ーは、は有機樹脂中に５０〜８０体積％の割合で均一に
分散されたものである。According to the present invention, the insulating layer is made of a composite material of an inorganic filler and an organic resin, and the inorganic filler is uniformly dispersed in the organic resin at a ratio of 50 to 80% by volume. is there.
【００１５】この複合材料を構成する無機質フィラーと
しては、ＳｉＯ2 、Ａｌ2 Ｏ3 、ＺｒＯ2 、ＴｉＯ2 、
ＡｌＮ、ＳｉＣ、ＢａＴｉＯ3 、ＳｒＴｉＯ3 、ゼオラ
イト、ＣａＴｉＯ3 、ほう酸アルミニウム等の公知の材
料が使用できる。フィラーの形状は平均粒径が２０μｍ
以下、特に１０μｍ以下、最適には７μｍ以下の略球形
状の粉末の他、平均アスペクト比が２以上、特に５以上
の繊維状のものや、織布物も使用できる。Inorganic fillers constituting this composite material include SiO 2 , Al 2 O 3 , ZrO 2 , TiO 2 ,
Known materials such as AlN, SiC, BaTiO 3 , SrTiO 3 , zeolite, CaTiO 3 and aluminum borate can be used. Filler has an average particle size of 20 μm
In addition to the substantially spherical powder of 10 μm or less, optimally 7 μm or less, fibrous or woven fabric having an average aspect ratio of 2 or more, particularly 5 or more, can also be used.
【００１６】一方、無機質フィラーが分散される有機樹
脂としては、ＰＰＥ（ポリフェニレンエーテル）、ＢＴ
レジン（ビスマレイミドトリアジン）、エポキシ樹脂、
ポリイミド樹脂、フッ素樹脂、フェノール樹脂等の樹脂
からなり、とりわけ原料として室温で液体の熱硬化性樹
脂であることが望ましい。On the other hand, as the organic resin in which the inorganic filler is dispersed, PPE (polyphenylene ether), BT
Resin (bismaleimide triazine), epoxy resin,
It is made of a resin such as a polyimide resin, a fluororesin, and a phenol resin, and it is particularly preferable that the raw material is a thermosetting resin that is liquid at room temperature.
【００１７】本発明によれば、上記の配線基板におい
て、最外層の絶縁層４の熱膨張係数が、内部の絶縁層５
の熱膨張係数よりも小さいことが大きな特徴である。最
外層の絶縁層も無機質フィラーと有機樹脂との複合材料
から構成されるものであるが、熱膨張係数を小さくする
ためには、内部の絶縁層中の無機質フィラーよりも比較
的熱膨張係数の小さい無機質フィラーを含有させたり、
内部および最外層ともに同様のフィラーを用いた場合、
熱膨張係数の小さいフィラーの量を内部の絶縁層よりも
最外層の絶縁層における含有量を多くすればよい。According to the present invention, in the above wiring board, the coefficient of thermal expansion of the outermost insulating layer 4 is equal to that of the inner insulating layer 5.
It is a great feature that it is smaller than the coefficient of thermal expansion. The outermost insulating layer is also composed of a composite material of an inorganic filler and an organic resin, but in order to reduce the thermal expansion coefficient, in order to reduce the thermal expansion coefficient, the thermal expansion coefficient of the inorganic filler is relatively higher than that of the inorganic filler in the internal insulating layer. Or include a small inorganic filler,
When the same filler is used for both the inner and outermost layers,
The content of the filler having a small coefficient of thermal expansion may be larger in the outermost insulating layer than in the inner insulating layer.
【００１８】このような比較的熱膨張係数の小さいフィ
ラーとしては、溶融ＳｉＯ2 、ＳｉＣ、Ｓｉ3 Ｎ4 が挙
げられ、これらの中でもＳｉＯ2 が最も効果的である。
このようなフィラーを用いて、そのフィラーの含有量を
制御することにより、最外層の絶縁層の熱膨張係数を半
導体素子の熱膨張係数により近似させることができる。Examples of such a filler having a relatively small thermal expansion coefficient include molten SiO 2 , SiC and Si 3 N 4 , and among these, SiO 2 is most effective.
By using such a filler and controlling the content of the filler, the thermal expansion coefficient of the outermost insulating layer can be approximated to the thermal expansion coefficient of the semiconductor element.
【００１９】具体的には、最外層の室温〜２５０℃にお
ける熱膨張係数は１０〜６０×１０-6／℃、特に１０〜
４０×１０-6／℃、前記内部の絶縁層が３０〜１００×
１０-6／℃であることが好適である。Specifically, the coefficient of thermal expansion of the outermost layer at room temperature to 250 ° C. is 10 to 60 × 10 −6 / ° C., and particularly 10 to 10.
40 × 10 −6 / ° C., the inner insulating layer is 30 to 100 ×
It is preferably 10 −6 / ° C.
【００２０】なお、熱膨張係数の小さい絶縁層は、最外
層として、最上面のみでは、熱膨張差により配線基板が
変形する場合があるため、配線基板の最上面と最下面の
両側に形成することが望ましい。そして、これら最外層
の絶縁層の表面、または別途低熱膨張のポリイミド等か
らなる配線層を介して半導体素子６を搭載させることに
より、信頼性の高い配線基板を提供できる。The insulating layer having a small coefficient of thermal expansion is formed as an outermost layer on both sides of the uppermost surface and the lowermost surface of the wiring board because the wiring board may be deformed due to the difference in thermal expansion only on the uppermost surface. Is desirable. Then, by mounting the semiconductor element 6 on the surface of these outermost insulating layers or separately via a wiring layer made of polyimide or the like having a low thermal expansion, a highly reliable wiring board can be provided.
【００２１】また、本発明において、導体回路として
は、銅、アルミニウム、金、銀等からなることが望まし
い。また、回路の必要に応じて、Ｎｉ−Ｃｒ等の高抵抗
の金属を用いる場合もある。In the present invention, the conductor circuit is preferably made of copper, aluminum, gold, silver or the like. Further, a high resistance metal such as Ni-Cr may be used depending on the need of the circuit.
【００２２】次ぎに、上記の配線基板を作製するには、
まず、絶縁層として、無機質フィラー粉末と粉末または
液状の有機樹脂とを混練機等の手段によって十分に混合
し、これをドクターブレード法等によってシート状に成
形した後、有機樹脂を半硬化させる。半硬化には、有機
樹脂は熱可塑性樹脂の場合には、加熱下で混合したもの
を冷却し、熱硬化性樹脂の場合には、完全固化するに十
分な温度よりもやや低い温度に加熱すればよい。Next, to manufacture the above wiring board,
First, as the insulating layer, the inorganic filler powder and the powder or liquid organic resin are sufficiently mixed by a means such as a kneader, and this is molded into a sheet by a doctor blade method or the like, and then the organic resin is semi-cured. For semi-curing, when the organic resin is a thermoplastic resin, the mixture mixed under heating is cooled, and in the case of a thermosetting resin, it is heated to a temperature slightly lower than a temperature sufficient for complete solidification. Good.
【００２３】そして、この絶縁層の表面に導体回路を形
成する。導体回路の形成には、銅等の金属箔を絶縁層に
接着剤で張りつけた後に、回路パターンのレジストを形
成して酸等によって不要な部分の金属をエッチング除去
するか、予め打ち抜きした金属箔を張りつける。他の方
法としては、絶縁層の表面に導体ペーストを回路パター
ンにスクリーン印刷や、フォトレジスト法等によって形
成した後、乾燥して加圧し、絶縁層に密着させることで
形成できる。Then, a conductor circuit is formed on the surface of the insulating layer. To form a conductive circuit, after attaching a metal foil such as copper to the insulating layer with an adhesive, form a resist for the circuit pattern and etch away the unnecessary metal with acid or the like, or use a metal foil that has been punched in advance. Stick it. As another method, the conductive paste can be formed on the surface of the insulating layer by screen printing, a photoresist method or the like on the surface of the insulating layer, and then dried and pressed to be adhered to the insulating layer.
【００２４】次に、導体回路を形成した絶縁層を所望に
よっては、打ち抜き法はレーザー加工によりビアホール
を形成して導体を充填後に、複数の絶縁層を積層して、
絶縁層の有機樹脂が完全に硬化させる。Next, if desired, the insulating layer on which the conductor circuit is formed is punched out by forming a via hole by laser processing and filling the conductor, and then laminating a plurality of insulating layers.
The organic resin of the insulating layer is completely cured.
【００２５】本発明では、上記の積層工程において、多
層基板の最外層に、熱膨張係数が内部の絶縁層の熱膨張
係数よりも小さい絶縁層を積層する。この熱膨張係数の
小さい絶縁層は、前述した通り、内部の絶縁層中の無機
質フィラーよりも比較的熱膨張係数の小さい無機質フィ
ラーを含有するか、または、内部および最外層ともに同
様のフィラーを用いた場合、熱膨張係数の小さいフィラ
ーの量を内部の絶縁層よりも最外層の絶縁層における含
有量の多い絶縁層を作製して、これを積層すればよい。In the present invention, in the above laminating step, an insulating layer having a thermal expansion coefficient smaller than that of the internal insulating layer is laminated on the outermost layer of the multilayer substrate. As described above, the insulating layer having a small coefficient of thermal expansion contains an inorganic filler having a relatively small coefficient of thermal expansion as compared with the inorganic filler in the inner insulating layer, or the same filler is used for both the inner and outermost layers. In such a case, an insulating layer having a larger amount of the filler having a smaller coefficient of thermal expansion in the outermost insulating layer than in the inner insulating layer may be prepared and laminated.
【００２６】[0026]
【実施例】無機質フィラーとして、平均粒径が５μｍの
ＳｉＯ2 粉末、平均アスペクト比２０、短径１０μｍの
ＳｉＯ2 ガラスファイバー、平均粒径が３μｍのＢａＴ
ｉＯ3 粉末を用い、有機樹脂として、ＢＴレジン（ビス
マレイミドトリアジン）、エポキシ樹脂、フェノール樹
脂、ＰＰＥ（ポリフェニレンエーテル）、液晶ポリマー
（液晶性芳香族ポリエステル）、ポリイミド樹脂を用い
て、これらを内部絶縁層用、最外層絶縁層用として表１
の比率で混合してスラリーを調製した。そして、ポリエ
チレンテレフタレート（ＰＥＴ）樹脂からなる転写シー
ト表面に形成された厚さ１２μｍの銅箔に対して、予め
エッチングによって銅配線パターンを形成し、そのパタ
ーンに上記のスラリーを流し加熱して半硬化させた後、
上記転写シートを剥がして回路パターンが形成された絶
縁層を形成した。Example As an inorganic filler, SiO 2 powder having an average particle size of 5 μm, SiO 2 glass fiber having an average aspect ratio of 20, and a short diameter of 10 μm, BaT having an average particle size of 3 μm.
TiO 3 powder is used, and BT resin (bismaleimide triazine), epoxy resin, phenol resin, PPE (polyphenylene ether), liquid crystal polymer (liquid crystalline aromatic polyester), and polyimide resin are used as an organic resin to insulate them internally. Table 1 for layers and outermost insulating layers
To prepare a slurry. Then, a copper wiring pattern having a thickness of 12 μm formed on the surface of a transfer sheet made of polyethylene terephthalate (PET) resin is preliminarily etched to form a copper wiring pattern, and the slurry is poured into the pattern and heated to be semi-cured. After letting
The transfer sheet was peeled off to form an insulating layer having a circuit pattern.
【００２７】また、無機質フィラーとして、ガラスクロ
スを用いたものは、有機樹脂に溶剤を混合して、この混
合液をガラスクロスに含浸させた。そして、有機樹脂が
含浸されたガラス含有クロスを上記銅配線パターンに乗
せて加熱により半硬化させた後、転写シートを剥がして
パターンを転写させた。In the case of using glass cloth as the inorganic filler, a solvent was mixed with the organic resin and the mixed solution was impregnated into the glass cloth. Then, a glass-containing cloth impregnated with an organic resin was placed on the copper wiring pattern and semi-cured by heating, and then the transfer sheet was peeled off to transfer the pattern.
【００２８】このようにして作製した内部絶縁層を５層
積層して、さらに最上層および最下層に最外層絶縁層を
積層した後、これを再度加熱して完全硬化させて多層配
線基板を作製した。After laminating the five inner insulating layers thus produced and further laminating the outermost insulating layers on the uppermost layer and the lowermost layer, this is heated again and completely cured to produce a multilayer wiring board. did.
【００２９】なお、最外層および内部層の室温〜２５０
℃における熱膨張係数を測定し、表１に示した。また、
得られた基板に対しては、半導体素子をダイボンディン
グペーストにより最外層の表面に接着した後、−４０℃
から１２５℃の繰り返し温度サイクルを付与し、１００
サイクル処理後の基板の状態を観察して、半導体素子の
搭載状態が劣化したものや、配線の抵抗に変化が見られ
たものの不良品の個数を表１に示した。The outermost layer and the inner layer are at room temperature to 250
The coefficient of thermal expansion at ° C was measured and is shown in Table 1. Also,
For the obtained substrate, after bonding the semiconductor element to the surface of the outermost layer with a die bonding paste, -40 ° C
Repeated temperature cycle from 100 to 125 ° C
The state of the substrate after the cycle treatment was observed, and the number of defective products in which the mounting state of the semiconductor element was deteriorated and the wiring resistance was changed was shown in Table 1.
【００３０】[0030]
【表１】 [Table 1]
【００３１】表１の試料Ｎo.１と試料Ｎo.２、試料Ｎo.
３と試料Ｎo.４、試料Ｎo.５と試料Ｎo.６、試料Ｎo.７
〜１０、試料Ｎo.１１と試料Ｎo.１２、試料Ｎo.１３と
試料Ｎo.１４の比較から明らかなように、最外層に低熱
膨張係数の絶縁層を積層した本発明品では、同一材質に
より形成した試料Ｎo.１、３、５、７、１１、１３に対
して、いずれも熱サイクル試験後の不良率が低下し信頼
性の高い配線基板を作製することができた。また、試料
Ｎo.１５〜２０に示されるように、あらゆる材質の組み
合わせも可能であり、これにより信頼性の高い基板を作
製できる。Sample No. 1, Sample No. 2 and Sample No. 2 in Table 1
3 and sample No. 4, sample No. 5 and sample No. 6, sample No. 7
As is clear from the comparison between Sample No. 11, Sample No. 11 and Sample No. 12, and Sample No. 13 and Sample No. 14, the product of the present invention in which an insulating layer having a low thermal expansion coefficient is laminated on the outermost layer is made of the same material. With respect to each of the formed samples No. 1, 3, 5, 7, 11, and 13, the defective rate after the thermal cycle test was lowered, and a highly reliable wiring board could be manufactured. Further, as shown in Sample Nos. 15 to 20, it is possible to combine all materials, whereby a highly reliable substrate can be manufactured.
【００３２】[0032]
【発明の効果】以上詳述した通り、本発明の高密度多層
配線基板は、配線基板の最外層に内部の絶縁層よりも低
膨張係数の絶縁層を積層することにより、高熱膨張の絶
縁層を用いた場合においても、半導体素子との熱膨張係
数の整合を行うことができるために、半導体素子を搭載
するパッケージなどの配線基板として、回路の超微細
化、精密化の要求に応えつつ、耐久性を有するものであ
り、過酷な条件下で用いられる携帯情報端末等の小型情
報機器の基板やメモリーカード等小型基板として最適な
特性を発揮することができる。As described above in detail, the high-density multilayer wiring board of the present invention has a high thermal expansion insulating layer by laminating an insulating layer having a lower expansion coefficient than the internal insulating layer on the outermost layer of the wiring board. Even when using, because it is possible to match the coefficient of thermal expansion with the semiconductor element, as a wiring board such as a package on which the semiconductor element is mounted, while responding to the demand for ultra-fine and precise circuits, Since it has durability, it can exhibit optimum characteristics as a substrate of a small information device such as a portable information terminal used under severe conditions and a small substrate of a memory card.
【図１】本発明の多層配線基板の概略図である。FIG. 1 is a schematic view of a multilayer wiring board according to the present invention.
１ 多層配線基板 ２ 絶縁層 ３ 導体回路 ４ 最外層の絶縁層 ５ 内部の絶縁層 ６ 半導体素子 DESCRIPTION OF SYMBOLS 1 Multilayer wiring board 2 Insulating layer 3 Conductor circuit 4 Outermost insulating layer 5 Inner insulating layer 6 Semiconductor element
───────────────────────────────────────────────────── フロントページの続き (72)発明者 笹森 理一 鹿児島県国分市山下町１番４号 京セラ株 式会社総合研究所内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Riichi Sasamori 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute
Claims (5)
らなる絶縁層と、低抵抗金属からなる導体回路とが多層
に積層された多層配線基板であって、最外層の絶縁層の
熱膨張係数が内部の絶縁層の熱膨張係数よりも小さいこ
とを特徴とする多層配線基板。1. A multilayer wiring board in which an insulating layer made of a composite material of an inorganic filler and an organic resin and a conductor circuit made of a low resistance metal are laminated in multiple layers, and the thermal expansion coefficient of the outermost insulating layer. Is smaller than the coefficient of thermal expansion of the internal insulating layer.
を含み、前記最外層の絶縁層中の前記低熱膨張の無機質
フィラー含有量が、前記内部の絶縁層中のそれよりも多
いことを特徴とする請求項１記載の多層配線基板。2. The low thermal expansion inorganic filler is contained in the insulating layer, and the content of the low thermal expansion inorganic filler in the outermost insulating layer is higher than that in the internal insulating layer. The multilayer wiring board according to claim 1.
含む酸化物からなる請求項２記載の多層配線基板。3. The multilayer wiring board according to claim 2, wherein the inorganic filler having a low thermal expansion is made of an oxide containing Si.
最外層の絶縁層が１０〜６０×１０-6／℃、前記内部の
絶縁層が３０〜１００×１０-6／℃である請求項１乃至
請求項３のうちのいずれか１つの多層配線基板。4. The coefficient of thermal expansion at room temperature to 250 ° C. is 10 to 60 × 10 −6 / ° C. for the outermost insulating layer and 30 to 100 × 10 −6 / ° C. for the inner insulating layer. The multilayer wiring board according to any one of claims 1 to 3.
搭載される請求項１乃至請求項４のうちのいずれか１つ
の多層配線基板。5. The multilayer wiring board according to any one of claims 1 to 4, wherein a semiconductor element is mounted on an upper surface of the outermost insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8042523A JPH09237972A (en) | 1996-02-29 | 1996-02-29 | Multilayered wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8042523A JPH09237972A (en) | 1996-02-29 | 1996-02-29 | Multilayered wiring board |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003386943A Division JP2004140385A (en) | 2003-11-17 | 2003-11-17 | Multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09237972A true JPH09237972A (en) | 1997-09-09 |
Family
ID=12638450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8042523A Pending JPH09237972A (en) | 1996-02-29 | 1996-02-29 | Multilayered wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09237972A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023252A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| JP2003023253A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| JP2003023251A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| US7883765B2 (en) | 2006-06-02 | 2011-02-08 | Murata Manufacturing Co., Ltd. | Multilayer ceramic substrate, method for producing same, and electronic component |
| JP2011114121A (en) * | 2009-11-26 | 2011-06-09 | Kyocera Corp | Wiring board |
| US8030579B2 (en) | 2001-03-14 | 2011-10-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2013021374A (en) * | 2012-10-29 | 2013-01-31 | Ibiden Co Ltd | Multilayer printed board |
| US9232642B2 (en) | 2012-07-20 | 2016-01-05 | Shinko Electric Industries Co., Ltd. | Wiring substrate, method for manufacturing the wiring substrate, and semiconductor package |
-
1996
- 1996-02-29 JP JP8042523A patent/JPH09237972A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8030579B2 (en) | 2001-03-14 | 2011-10-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US8324512B2 (en) | 2001-03-14 | 2012-12-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US9040843B2 (en) | 2001-03-14 | 2015-05-26 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2003023252A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| JP2003023253A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| JP2003023251A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| US7883765B2 (en) | 2006-06-02 | 2011-02-08 | Murata Manufacturing Co., Ltd. | Multilayer ceramic substrate, method for producing same, and electronic component |
| JP2011114121A (en) * | 2009-11-26 | 2011-06-09 | Kyocera Corp | Wiring board |
| US9232642B2 (en) | 2012-07-20 | 2016-01-05 | Shinko Electric Industries Co., Ltd. | Wiring substrate, method for manufacturing the wiring substrate, and semiconductor package |
| JP2013021374A (en) * | 2012-10-29 | 2013-01-31 | Ibiden Co Ltd | Multilayer printed board |
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