JPH1022418A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH1022418A JPH1022418A JP8172182A JP17218296A JPH1022418A JP H1022418 A JPH1022418 A JP H1022418A JP 8172182 A JP8172182 A JP 8172182A JP 17218296 A JP17218296 A JP 17218296A JP H1022418 A JPH1022418 A JP H1022418A
- Authority
- JP
- Japan
- Prior art keywords
- sealing resin
- peeling
- groove
- metal plate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子、特に
金属板を内蔵した樹脂封止型パッケージを備えた半導体
素子における、金属板と封止樹脂との界面に発生および
拡大する封止樹脂の剥離の防止技術に関し、例えば、放
熱板を備えて大電流を通電させる半導体チップの実装に
利用して信頼性、品質向上に有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a resin-sealed package having a built-in metal plate. The present invention relates to a technique for preventing peeling, which is effective for improving reliability and quality, for example, for use in mounting a semiconductor chip having a heat radiating plate and supplying a large current.
【０００２】[0002]
【従来の技術】大電流通電を実現するための半導体素子
として、半導体チップを金属板に半田付けした構造があ
る。この半田付けされる金属板は大電流通電時に半導体
チップから発生する熱を放出する作用と、半導体チップ
を支持し、かつ封止樹脂を支持する構造となっている。
このような金属板においては、通常、金属板の封止樹脂
密着面側に、金属板と封止樹脂との熱膨張係数の違いに
よる剪断応力を緩和するための溝が１本だけ形成されて
いる。2. Description of the Related Art As a semiconductor element for realizing a large current flow, there is a structure in which a semiconductor chip is soldered to a metal plate. The metal plate to be soldered has a function of releasing heat generated from the semiconductor chip when a large current flows, and a structure for supporting the semiconductor chip and supporting the sealing resin.
In such a metal plate, usually, only one groove is formed on the sealing resin contact surface side of the metal plate to alleviate shear stress due to a difference in thermal expansion coefficient between the metal plate and the sealing resin. I have.
【０００３】[0003]
【発明が解決しようとする課題】上記のような金属板を
内蔵する樹脂封止型パッケージを備えた半導体素子は、
気相熱衝撃試験に代表される繰り返し熱衝撃印加状態下
において、金属板と封止樹脂との熱膨張係数の違いによ
って金属板と封止樹脂との界面に発生する剪断応力を緩
和するための溝を１本形成し、その１本の溝の内部に充
填される封止樹脂の投錨効果（樹脂や接着剤が非接着面
にある空隙に侵入、固化し、釘または楔のような働きを
する効果、アンカー効果とも云う）をもって剪断応力を
緩和する構造となっている。しかし、後述する理由によ
り、１本の溝だけでは熱衝撃による繰り返し剪断応力に
対して十分に抗することができず、剥離が発生すると、
その剥離が繰り返し剪断応力によって剥離面積を拡大し
ていき、その結果、半導体チップを金属板に接着してい
る半田層にクラックを発生させるという問題点があっ
た。SUMMARY OF THE INVENTION A semiconductor device having a resin-sealed type package having a built-in metal plate as described above,
In order to reduce the shear stress generated at the interface between the metal plate and the sealing resin due to the difference in the thermal expansion coefficient between the metal plate and the sealing resin under the conditions of repeated thermal shock application represented by the gas phase thermal shock test One groove is formed, and the anchoring effect of the sealing resin filled in the single groove (resin or adhesive penetrates and solidifies into the voids on the non-adhesive surface, and acts like a nail or wedge. Effect, also referred to as an anchor effect) to relieve the shear stress. However, for the reasons described below, only one groove cannot sufficiently withstand repeated shear stress due to thermal shock, and when peeling occurs,
The peeling repeatedly increases the peeling area due to the shearing stress, and as a result, there is a problem that cracks are generated in the solder layer bonding the semiconductor chip to the metal plate.
【０００４】前述の剪断応力を緩和する溝が１本で構成
される半導体素子において、１本の溝だけでは熱衝撃に
よる繰り返し剪断応力に対して十分に抗することができ
ない理由は以下の如くである。[0004] In the above-described semiconductor device having a single groove for relaxing the shear stress, the reason why the single groove alone cannot sufficiently withstand the repetitive shear stress due to thermal shock is as follows. is there.
【０００５】すなわち、封止樹脂の剥離は、半導体素子
に印加された熱衝撃による繰り返し剪断応力により、封
止樹脂端面から金属板と封止樹脂との界面の中心に向け
て拡大していくもの（以下、外からの剥離という）と、
金属板と封止樹脂との界面の中心付近から封止樹脂端面
に向けて拡大していくもの（以下、内からの剥離とい
う）との２つの剥離過程に依存し、また溝はその内部に
充填された封止樹脂の投錨効果によって剥離する面積拡
大を防止するようになっている。[0005] That is, the peeling of the sealing resin expands from the sealing resin end face toward the center of the interface between the metal plate and the sealing resin due to the repeated shearing stress caused by the thermal shock applied to the semiconductor element. (Hereinafter referred to as peeling from the outside)
The groove depends on two peeling processes, that is, the one that expands from the vicinity of the center of the interface between the metal plate and the sealing resin toward the sealing resin end surface (hereinafter referred to as peeling from inside), and The expansion of the peeling area due to the anchoring effect of the filled sealing resin is prevented.
【０００６】しかし、従来構造の半導体素子は１本の溝
で剪断応力を緩和する構造であるため、外からの剥離と
内からの剥離との両剥離が溝を挟み込んで、溝領域で接
触して繋がった場合には、溝に充填された封止樹脂の投
錨効果は失われてしまう。そのため、投錨効果を失った
封止樹脂は、繰り返し剪断応力によって広範囲にわたっ
てその剥離面積を急速に拡大していき、その結果、剪断
応力は半導体チップに集中し、半田クラックを発生させ
ることが本発明者によって明らかにされた。However, since the semiconductor element of the conventional structure has a structure in which the shear stress is relieved by one groove, both the peeling from the outside and the peeling from the inside sandwich the groove and make contact in the groove region. If they are connected, the anchoring effect of the sealing resin filled in the groove is lost. For this reason, the sealing resin that has lost the anchoring effect rapidly expands its peeling area over a wide range due to repeated shearing stress, and as a result, the shearing stress concentrates on the semiconductor chip and solder cracks are generated. Was revealed by
【０００７】本発明は、上記のごとき従来技術の問題を
解決するためになされたものであり、金属板を内蔵する
樹脂封止型パッケージを備えた半導体素子において、封
止樹脂の金属板からの剥離の発生と剥離の拡大を防止す
ることの出来る半導体素子を提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above. In a semiconductor device having a resin-sealed type package having a built-in metal plate, the present invention relates to a method of forming a sealing resin from a metal plate. An object of the present invention is to provide a semiconductor element capable of preventing occurrence of peeling and expansion of peeling.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、特許請求の範囲に記載するよう
に構成している。すなわち、請求項１に記載の発明にお
いては、半導体チップを載置した金属板と、上記半導体
チップを封止する樹脂封止パッケージと、を備えた半導
体素子であって、金属板の封止樹脂密着面に、上記半導
体チップの大部分を平面上で少なくともほぼ囲む形状の
溝または楔を少なくとも２重以上に設けるように構成し
ている。なお、上記の溝または楔は、半導体チップを切
れ目なしで完全に囲むものでなくてもよいが、半導体チ
ップの大部分を平面上で少なくともほぼ囲む形状（完全
に囲むか若しくは切れ目を有してほぼ囲む形状）で少な
くとも２重以上に設ける必要がある。Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, according to the first aspect of the present invention, there is provided a semiconductor element including a metal plate on which a semiconductor chip is mounted, and a resin sealing package for sealing the semiconductor chip, wherein a sealing resin for the metal plate is provided. At least two or more grooves or wedges are formed on the contact surface so as to at least substantially surround the majority of the semiconductor chip on a plane. The above-mentioned groove or wedge does not have to completely surround the semiconductor chip without any breaks, but may have a shape that completely surrounds most of the semiconductor chip on a plane at least substantially (completely surrounds or has a break. It is necessary to provide at least two or more layers in a shape that is substantially enclosed.
【０００９】また、請求項２においては、上記の溝また
は楔の断面形状を、Ｖ字型またはＵ字型若しくはＶ字型
とＵ字型との合成型にしたものである。According to a second aspect of the present invention, the groove or the wedge has a V-shaped or U-shaped cross-section or a combined V-shaped and U-shaped cross-section.
【００１０】上記のように、本発明においては、金属板
の封止樹脂密着面に、上記半導体チップを平面上で少な
くともほぼ囲む形状の溝または楔を少なくとも２重以上
に設けたものである。As described above, in the present invention, at least two or more grooves or wedges are formed on the sealing resin contact surface of the metal plate so as to at least substantially surround the semiconductor chip on a plane.
【００１１】上記の構成によれば、熱衝撃による繰り返
し剪断応力により、金属板と封止樹脂との界面に対して
これを剥離させようとする力が作用し、金属板から封止
樹脂が剥離し、封止樹脂の投錨効果が希薄な界面上にて
その剥離面積を拡大していったとしても、例えば封止樹
脂の金属板密着面上において、溝が多重に設けられてい
る、すなわち、従来の溝の内側（または外側）に、新た
な溝または楔が設けられているので、従来構造の溝は外
からの剥離の拡大を防止せしめる効果を発揮し、新たな
溝は内からの剥離の拡大を防止せしめる効果を発揮す
る。そのため、従来構造の溝と新たな溝または楔との間
には剥離の発生しない領域が形成され、剥離の発生しな
い領域の封止樹脂と金属板との密着は保たれて、その剥
離の発生しない領域を囲む溝または楔による封止樹脂の
投錨効果をもって剪断応力を十分に緩和し、剥離力に対
して極めて強く抗することができる。したがって、外か
らの剥離と内からの剥離とが繋がるような広範囲にわた
る剥離の面積拡大は防止される。[0011] According to the above structure, a force for peeling the interface between the metal plate and the sealing resin acts on the interface between the metal plate and the sealing resin due to the repeated shearing stress due to the thermal shock, and the sealing resin is separated from the metal plate. And, even if the anchoring effect of the sealing resin increases its peeling area on a thin interface, for example, on the metal plate contact surface of the sealing resin, grooves are provided in multiples, that is, Since a new groove or wedge is provided inside (or outside) of the conventional groove, the groove of the conventional structure has an effect of preventing the spread of the peeling from the outside, and the new groove has the peeling from the inside. It has the effect of preventing the expansion of Therefore, a region where no peeling occurs is formed between the groove of the conventional structure and the new groove or wedge, and the adhesion between the sealing resin and the metal plate in the region where the peeling does not occur is maintained. The shearing stress can be sufficiently reduced by the anchoring effect of the sealing resin by the groove or the wedge surrounding the region not to be covered, and the peeling force can be extremely strongly resisted. Therefore, an increase in the area of the peeling over a wide range where the peeling from the outside and the peeling from the inside are connected is prevented.
【００１２】また、剥離は封止樹脂等による投錨効果の
希薄な界面上にて発生するが、従来構造の溝と新たな構
造である溝または楔との間の界面においては、その両構
造によって形成される封止樹脂または楔の投錨効果が、
剥離力に対して極めて強く抗するため、剥離は発生しな
い。The peeling occurs on the interface where the anchoring effect is weak due to the sealing resin or the like. At the interface between the groove of the conventional structure and the groove or wedge which is a new structure, both the structures are used. The anchoring effect of the formed sealing resin or wedge,
Peeling does not occur because it is extremely resistant to peeling force.
【００１３】すなわち、本発明の作用の概要を説明すれ
ば、従来の溝に加えて１本以上の溝または楔を金属板に
設けて２重以上の剥離拡大防止構造を形成することによ
り、熱衝撃での繰り返し応力により発生する外からと内
からとの２種類の剥離に対して、２重以上の剥離防止構
造が独立してそれぞれの両剥離の面積拡大の防止効果を
発揮するため、両剥離が繋がることはなく、剥離の拡大
は確実に防止される。さらに、新たに開設する溝または
楔の立体形状によって形成される封止樹脂の投錨効果に
よる剥離防止効果も同時に発揮されるのは前述の通りで
ある。That is, the outline of the operation of the present invention is as follows. In addition to the conventional grooves, one or more grooves or wedges are provided on a metal plate to form a double or more peeling prevention structure. For two types of peeling from outside and inside caused by repeated stress due to impact, the double or more peeling prevention structures independently exert the effect of preventing the area expansion of both peeling, The peeling is not connected, and the spread of the peeling is surely prevented. Further, as described above, the separation prevention effect due to the anchoring effect of the sealing resin formed by the newly formed groove or the three-dimensional shape of the wedge is also exerted as described above.
【００１４】[0014]
【発明の効果】金属板の封止樹脂密着面に、半導体チッ
プを平面上で少なくともほぼ囲む形状の溝または楔を少
なくとも２重以上に設けたことにより、熱衝撃に伴って
発生する応力によって金属板と封止樹脂が剥離した場合
でも、２重に設けた溝または楔で剥離の拡大を防止でき
るため、半導体チップを金属板に接着している半田層の
クラックの発生を防止することができ、半導体素子の耐
環境性、特に耐熱衝撃性を大幅に向上できる、という効
果が得られる。According to the present invention, at least two or more grooves or wedges are formed on the sealing resin contact surface of the metal plate so as to substantially surround the semiconductor chip on a plane. Even when the plate and the sealing resin are separated, the spread of the separation can be prevented by the double groove or wedge, so that the occurrence of cracks in the solder layer bonding the semiconductor chip to the metal plate can be prevented. This has the effect of significantly improving the environmental resistance, especially the thermal shock resistance, of the semiconductor element.
【００１５】[0015]
【発明の実施の形態】図１は本発明の一実施の形態であ
る樹脂封止パッケージを備えている半導体素子を示す断
面図、図２はそのパッケージに付属している金属板３の
樹脂密着面の平面図である。FIG. 1 is a cross-sectional view showing a semiconductor device having a resin-sealed package according to an embodiment of the present invention. FIG. 2 is a diagram showing resin adhesion of a metal plate 3 attached to the package. It is a top view of a surface.
【００１６】本実施の形態において、樹脂封止パッケー
ジを備えている半導体素子１は封止樹脂２と金属板３と
を備えており、金属板３はパッケージング以前には図２
に示されているように構成されている。すなわち、金属
板３の封止樹脂密着面側には、金属板と封止樹脂との熱
膨張係数の違いによる剪断応力を緩和する溝６に加え
て、封止樹脂の剥離の発生および拡大を防止する溝７を
溝６の内側に備えている。溝６の断面構造は通常Ｖ字状
であり、本実施の形態では溝７も断面構造をＶ字状とし
ている。溝７は、金属板３に金型プレス加工を施すこと
により形成される。例えば、溝６を形成するプレス金型
に溝７を形成する楔を形成することにより、溝７は溝６
のプレス加工と同時に金属板３に形成することができ
る。また、金属板３にエッチング加工を施しても溝６は
形成できるし、溝７も同様にして形成することができ
る。In the present embodiment, a semiconductor element 1 having a resin-sealed package has a sealing resin 2 and a metal plate 3, and the metal plate 3 has a structure shown in FIG.
It is configured as shown in FIG. In other words, on the sealing resin contact surface side of the metal plate 3, in addition to the grooves 6 for alleviating the shear stress due to the difference in the thermal expansion coefficient between the metal plate and the sealing resin, the occurrence and expansion of the sealing resin are prevented. A groove 7 for prevention is provided inside the groove 6. The cross-sectional structure of the groove 6 is usually V-shaped, and in this embodiment, the cross-sectional structure of the groove 7 is also V-shaped. The groove 7 is formed by subjecting the metal plate 3 to die pressing. For example, the groove 7 is formed by forming a wedge for forming the groove 7 in a press die for forming the groove 6.
Can be formed on the metal plate 3 at the same time as the pressing process. The groove 6 can be formed even when the metal plate 3 is etched, and the groove 7 can be formed in the same manner.
【００１７】また、上記の溝６、７は、図２に示すよう
に、金属板面に対して閉じている（半導体チップ５を完
全に囲む形状）ものでなくてもよいし、また、切れ目が
あってもよいが、半導体チップ５の大部分を平面上で少
なくともほぼ囲む形状（完全に囲むか若しくは切れ目を
有してほぼ囲む形状）で少なくとも２重（溝６と７で２
重に囲んでいる）以上に設ける必要がある。As shown in FIG. 2, the grooves 6 and 7 do not have to be closed (the shape completely surrounding the semiconductor chip 5) with respect to the surface of the metal plate. However, at least two portions (two or more portions in the trenches 6 and 7) are formed so as to surround at least substantially the entire surface of the semiconductor chip 5 on a plane (a shape that completely surrounds or substantially surrounds with a cut).
It is necessary to provide more.
【００１８】金属板３上には、集積回路を作り込まれた
半導体チップ５が接着剤９（銀ペースト、半田等）によ
ってボンディングされており、半導体チップ５の電極パ
ッド（図示せず）と各インナーリード１１との間にワイ
ヤ１０がそれぞれボンディングされている。また、半導
体チップ５の集積回路は電極パッド、ワイヤ１０、イン
ナーリード１１およびアウターリード４を介して電気的
に外部に引き出されるようになっている。On the metal plate 3, a semiconductor chip 5 in which an integrated circuit is formed is bonded by an adhesive 9 (silver paste, solder, etc.), and an electrode pad (not shown) of the semiconductor chip 5 is The wires 10 are respectively bonded to the inner leads 11. Further, the integrated circuit of the semiconductor chip 5 is electrically drawn to the outside via the electrode pads, the wires 10, the inner leads 11, and the outer leads 4.
【００１９】上記のごとき半導体素子において、半導体
チップ５の金属板３への接着剤９を用いたボンディング
作業は次のようにして行なわれる。まず、図２に示す金
属板３上の、あらかじめ塗布された銀ペースト上に、接
着剤９を塗布する。続いて、塗布された接着剤９上に、
集積回路を作り込まれた半導体チップ５を配置する。そ
して、ワイヤボンディングを行なった後、封止樹脂２を
用いて半導体チップ５は金属板３と一体成型される。こ
の封止樹脂２によって前記アウターリード４の一部、半
導体チップ５、ワイヤ１０およびインナーリード１１が
気密封止される。すなわち、金属板３上に封止樹脂２が
配置され、金属板３裏面は外部に露出し、封止樹脂２の
一端面からアウターリード４が突出された構造となる。In the semiconductor device as described above, the bonding operation of the semiconductor chip 5 to the metal plate 3 using the adhesive 9 is performed as follows. First, an adhesive 9 is applied on a previously applied silver paste on the metal plate 3 shown in FIG. Subsequently, on the applied adhesive 9,
A semiconductor chip 5 in which an integrated circuit is built is arranged. After performing the wire bonding, the semiconductor chip 5 is integrally molded with the metal plate 3 using the sealing resin 2. The sealing resin 2 hermetically seals a part of the outer lead 4, the semiconductor chip 5, the wire 10, and the inner lead 11. That is, the sealing resin 2 is disposed on the metal plate 3, the back surface of the metal plate 3 is exposed to the outside, and the outer leads 4 project from one end surface of the sealing resin 2.
【００２０】次に作用を説明する。前記構成にかかる半
導体素子は出荷前に抜き取り検査を施される。抜き取り
検査では気相熱衝撃試験を含む環境試験が実施される。
また、この半導体素子がプリント配線基板等に実装され
る際には、半田ディップやフロー半田処理によって半導
体素子は加熱される。Next, the operation will be described. The semiconductor device according to the above configuration is subjected to a sampling inspection before shipment. In the sampling inspection, an environmental test including a gas phase thermal shock test is performed.
When the semiconductor element is mounted on a printed wiring board or the like, the semiconductor element is heated by solder dip or flow soldering.
【００２１】このような環境試験または実装時に熱衝撃
が半導体素子に加えられた場合、構成材料の熱膨張係数
差によって封止樹脂２の内部に応力が発生する。図３
は、上記内部応力を示す断面図であり、曲線が内部応力
を示す。When a thermal shock is applied to the semiconductor element during such an environmental test or mounting, a stress is generated inside the sealing resin 2 due to a difference in thermal expansion coefficient between constituent materials. FIG.
FIG. 3 is a cross-sectional view showing the internal stress, and a curve shows the internal stress.
【００２２】封止樹脂２の内部応力は、主に半導体チッ
プ５の上辺付近および金属板３と封止樹脂２との界面に
加えて金属板３上の溝付近にて発生する。ただし、半導
体チップ５を金属板３に接着している接着剤９のクラッ
クはこの程度の応力集中では発生しない。しかし、度重
なる熱衝撃による繰返し応力により、金属板３と封止樹
脂２との界面に外からの剥離と内からの剥離が発生して
拡大し、両剥離が繋がって溝内部に充填された封止樹脂
の投錨効果が失われると、溝付近に分散されていた応力
が半導体チップ５に集中して過大な応力が作用するた
め、半田層にクラックが発生する。The internal stress of the sealing resin 2 is mainly generated near the upper side of the semiconductor chip 5 and near the groove on the metal plate 3 in addition to the interface between the metal plate 3 and the sealing resin 2. However, cracks in the adhesive 9 that bonds the semiconductor chip 5 to the metal plate 3 do not occur at such a stress concentration. However, due to repeated stress due to repeated thermal shock, peeling from the outside and peeling from the inside occurred at the interface between the metal plate 3 and the sealing resin 2 and expanded, and both peels were connected to fill the inside of the groove. When the anchoring effect of the sealing resin is lost, the stress dispersed near the groove concentrates on the semiconductor chip 5 and an excessive stress acts, so that a crack occurs in the solder layer.
【００２３】しかし、本実施の形態においては、金属板
３に溝６および溝７が構成されているため、封止樹脂２
と金属板３との界面に半田層クラックを発生させる程の
広範囲な剥離が発生することは無い。すなわち、前述し
たような熱衝撃による繰り返し応力により、金属板３と
封止樹脂２との界面に対してこれを剥離させようとする
力が作用し、外からの剥離と内からの剥離とが発生して
拡大したとしても、溝６に加えて溝７が新たに開設され
ていることから、外からの剥離に対しては溝６でその剥
離の拡大を防止し、内からの剥離に対しては溝７でその
剥離の拡大を防止する。そのため、外からの剥離と内か
らの剥離が繋がることはなく、剥離はそれ以上面積を拡
大できないため、溝６および溝７に充填された封止樹脂
２は投錨効果を保持し、故に半導体チップ５に熱応力が
集中することは無く、半田クラックは確実に防止され
る。そして、剥離が発生しない場合には、半導体チップ
５の上辺付近および金属板３と封止樹脂２との界面に応
力が加わったとしても、溝６および溝７に充填された封
止樹脂の投錨効果によって応力は分散され、半田層にク
ラックが発生しないのは前述した通りである。However, in this embodiment, since the metal plate 3 has the groove 6 and the groove 7, the sealing resin 2
Extensive peeling that does not cause solder layer cracking at the interface between the metal plate 3 and the metal plate 3 does not occur. That is, due to the repetitive stress caused by the thermal shock as described above, a force is applied to the interface between the metal plate 3 and the sealing resin 2 so as to separate the metal plate 3 and the sealing resin 2 from each other. Even if it occurs and expands, since the groove 7 is newly opened in addition to the groove 6, the groove 6 prevents the expansion of the separation from the outside, and prevents the expansion from the inside by the groove 6. The groove 7 prevents the separation from spreading. Therefore, the peeling from the outside and the peeling from the inside are not connected, and the peeling cannot increase the area any more. Therefore, the sealing resin 2 filled in the groove 6 and the groove 7 retains the anchoring effect, and thus the semiconductor chip No thermal stress is concentrated on the solder paste 5, and solder cracks are reliably prevented. When the peeling does not occur, even if stress is applied to the vicinity of the upper side of the semiconductor chip 5 and the interface between the metal plate 3 and the sealing resin 2, the anchoring of the sealing resin filled in the grooves 6 and 7 is performed. As described above, the stress is dispersed by the effect and no crack occurs in the solder layer.
【００２４】前記実施の形態によれば次の効果が得られ
る。すなわち、金属板に、従来より開設されている溝に
加えて、重複して溝を追加することにより、熱衝撃に伴
って発生する応力により金属板と封止樹脂が剥離した場
合でも、封止樹脂の端面から封止樹脂と金属板との界面
内部へ向けて拡大する剥離と、封止樹脂と金属板との界
面内部から封止樹脂の端面に向けて拡大する剥離との、
両剥離が繋がることによる広範囲な面積拡大を防止でき
るため、半導体チップを金属板に接着している接着剤層
のクラックの発生を防止することができる。According to the above embodiment, the following effects can be obtained. In other words, by adding a groove to the metal plate in addition to the groove that has been established in the past, the sealing is performed even when the metal plate and the sealing resin are separated due to the stress generated by the thermal shock. The peeling that expands from the end face of the resin toward the inside of the interface between the sealing resin and the metal plate, and the peeling that expands from the inside of the interface between the sealing resin and the metal plate toward the end face of the sealing resin,
Since a wide area can be prevented from being increased due to the connection of the two separations, the occurrence of cracks in the adhesive layer that bonds the semiconductor chip to the metal plate can be prevented.
【００２５】次に、図３は本発明の第２の実施の形態を
示す断面図である。この実施の形態は、前記図１の実施
の形態における、樹脂の剥離の発生および拡大を防止す
る溝７に代えて、楔８を金属板３上に設けたものであ
り、その作用および効果は前記図１の実施の形態と同様
である。FIG. 3 is a sectional view showing a second embodiment of the present invention. In this embodiment, a wedge 8 is provided on the metal plate 3 in place of the groove 7 for preventing the occurrence and expansion of the resin in the embodiment of FIG. This is the same as the embodiment of FIG.
【００２６】以上、本発明者によってなされた発明を実
施の形態に基づき具体的に説明してきたが、本発明は前
記実施の形態に限定されるものではなく、その要旨を逸
脱しない範囲で種々変更可能であることはいうまでもな
い。例えば、樹脂の剥離の発生および拡大を防止する溝
または楔は、直線状、曲線状、多角線状、点線状等のよ
うな形状を問うものではない。Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible. For example, the shape of the groove or wedge that prevents the occurrence and expansion of resin peeling is not limited to a straight line, a curved line, a polygonal line, a dotted line, or the like.
【００２７】また溝６および溝７のように金属板面に対
して閉じている必要もなく、封止樹脂２と金属板３との
界面内に重複して位置すれば効果を発揮するのは言うま
でもない。ただし、溝６と溝７（または楔８）は切れ目
なしで完全に囲むものでなくてもよいが、半導体チップ
の大部分を平面上で少なくともほぼ囲む形状（完全に囲
むか若しくは多少の切れ目を有してほぼ囲む形状）で多
重（少なくとも２重以上）に設ける必要がある。It is not necessary to close the metal plate surface like the groove 6 and the groove 7, and the effect is exerted if it is located in the interface between the sealing resin 2 and the metal plate 3. Needless to say. However, the groove 6 and the groove 7 (or the wedge 8) do not need to completely surround the semiconductor chip without a break, but may have a shape that completely surrounds most of the semiconductor chip on a plane at least substantially (completely surrounds or slightly cuts). It is necessary to provide multiple (at least double or more) in a shape that has a shape that substantially surrounds it.
【００２８】また、溝または楔の断面形状は、Ｖ字状に
形成するに限らず、Ｕ字状またはＶ字状とＵ字状との合
成型でも効果を発揮する。The cross-sectional shape of the groove or wedge is not limited to the V-shape, and the effect can also be obtained with a U-shape or a combined type of the V-shape and the U-shape.
【００２９】また、半導体チップ５を金属板３に接着し
ている半田層のクラックを防止するには、封止樹脂２と
金属板３との界面の接着を強化することが根幹にあるこ
とはいうまでもない。In order to prevent cracks in the solder layer bonding the semiconductor chip 5 to the metal plate 3, it is essential to strengthen the bonding at the interface between the sealing resin 2 and the metal plate 3. Needless to say.
【００３０】また、以上の説明では、主として本発明者
によってなされた発明をその背景となった利用分野であ
る樹脂封止パッケージを備えた半導体素子に適用した場
合について説明してきたが、それに限定されるものでは
なく、その他の形式の樹脂封止型パッケージを備えた半
導体素子等の半導体素子全般に適用することができるも
のである。In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor device having a resin-sealed package, which is the field of application as the background, has been described. Instead, the present invention can be applied to all types of semiconductor devices such as semiconductor devices provided with other types of resin-sealed packages.
【図１】本発明の第１の実施の形態を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２】図１のパッケージに付属している金属板３の樹
脂密着面の平面図。FIG. 2 is a plan view of a resin contact surface of a metal plate 3 attached to the package of FIG.
【図３】本発明の第２の実施の形態を示す断面図。FIG. 3 is a sectional view showing a second embodiment of the present invention.
１…金属板付き樹脂封止型の半導体素子 ２…封止樹脂 ３…金属板 ４…アウターリード ５…半導体チップ ６…熱衝撃による繰返し剪断応力を緩和するための溝 ７…樹脂の剥離の発生および拡大を防止するための溝 ８…樹脂の剥離の発生および拡大を防止するための楔 ９…接着剤 １０…ワイヤ １１…インナーリード DESCRIPTION OF SYMBOLS 1 ... Resin sealing type semiconductor element with a metal plate 2 ... Encapsulation resin 3 ... Metal plate 4 ... Outer lead 5 ... Semiconductor chip 6 ... Groove for relieving repetitive shear stress by thermal shock 7 ... Release of resin And a groove for preventing expansion 8... A wedge for preventing the occurrence and expansion of resin peeling 9... An adhesive 10... A wire 11.
Claims (2)
導体チップを封止する樹脂封止パッケージと、を備えた
半導体素子であって、 金属板の封止樹脂密着面に、上記半導体チップの大部分
を平面上で少なくともほぼ囲む形状の溝または楔を少な
くとも２重以上に設けたことを特徴とする半導体素子。1. A semiconductor element comprising: a metal plate on which a semiconductor chip is mounted; and a resin sealing package for sealing the semiconductor chip, wherein the semiconductor chip is provided on a sealing resin contact surface of the metal plate. Characterized in that at least two or more grooves or wedges having a shape that at least substantially surrounds on a plane at least are provided.
はＵ字型若しくはＶ字型とＵ字型との合成型であること
を特徴とする請求項１に記載の半導体素子。2. The semiconductor device according to claim 1, wherein the cross-sectional shape of the groove or the wedge is a V-shape, a U-shape, or a combination of a V-shape and a U-shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8172182A JPH1022418A (en) | 1996-07-02 | 1996-07-02 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8172182A JPH1022418A (en) | 1996-07-02 | 1996-07-02 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1022418A true JPH1022418A (en) | 1998-01-23 |
Family
ID=15937105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8172182A Pending JPH1022418A (en) | 1996-07-02 | 1996-07-02 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1022418A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018154635A1 (en) * | 2017-02-21 | 2018-08-30 | 三菱電機株式会社 | Semiconductor device |
-
1996
- 1996-07-02 JP JP8172182A patent/JPH1022418A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018154635A1 (en) * | 2017-02-21 | 2018-08-30 | 三菱電機株式会社 | Semiconductor device |
| JP6394810B1 (en) * | 2017-02-21 | 2018-09-26 | 三菱電機株式会社 | Semiconductor device |
| KR20190102082A (en) * | 2017-02-21 | 2019-09-02 | 미쓰비시덴키 가부시키가이샤 | Semiconductor devices |
| CN110392924A (en) * | 2017-02-21 | 2019-10-29 | 三菱电机株式会社 | Semiconductor device |
| US11309231B2 (en) | 2017-02-21 | 2022-04-19 | Mitsubishi Electric Corporation | Semiconductor device |
| CN110392924B (en) * | 2017-02-21 | 2022-11-15 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
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