JPH10223795A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JPH10223795A JPH10223795A JP1955697A JP1955697A JPH10223795A JP H10223795 A JPH10223795 A JP H10223795A JP 1955697 A JP1955697 A JP 1955697A JP 1955697 A JP1955697 A JP 1955697A JP H10223795 A JPH10223795 A JP H10223795A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor chip
- insulating support
- inner connection
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケ−ジ
の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor package.
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）が代表的である。これを多端子化する場合は、端子
ピッチを縮小することが必要であるが、０．５ｍｍピッ
チ以下の領域では、配線板との接続に高度な技術が必要
になる。後者のアレイタイプは比較的大きなピッチで端
子配列が可能なため、多ピン化に適している。従来、ア
レイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ Ｇｒｉ
ｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は
挿入型となり、表面実装には適していない。このため、
表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）と称するパッケージが開発されている。2. Description of the Related Art As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, I / O terminals are arranged in a line around the package,
There is a type that is arranged in multiple rows not only around but also inside.
The former is a QFP (Quad Flat Package).
e) is representative. In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in the region of 0.5 mm pitch or less, advanced technology is required for connection with a wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch. Conventionally, the array type is a PGA (Pin Gri) having connection pins.
d Array) is common, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason,
Surface mountable BGA (Ball Grid Array)
A package called y) has been developed.
【０００３】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるチップサイズパッケージ（ＣＳ
Ｐ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案さ
れている。これは、半導体チップの周辺部でなく、実装
領域内に外部配線基板との接続部を有するパッケージで
ある。具体例としては、バンプ付きポリイミドフィルム
を半導体チップの表面に接着し、チップと金リード線に
より電気的接続を図った後、エポキシ樹脂などをポッテ
ィングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩ
ＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．
１４０，ｐ１８−１９）や、仮基板上に半導体チップ及
び外部配線基板との接続部に相当する位置に金属バンプ
を形成し、半導体チップをフェースダウンボンディング
後、仮基板上でトランスファーモールドしたもの（Ｓｍ
ａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃ
ｋａｇｅ ＣＳＰ； ＴｈｅＳｅｃｏｎｄ ＶＬＳＩ
Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐ
ａｎ，ｐ４６−５０，１９９４）などがある。[0003] On the other hand, with the miniaturization of electronic equipment, the demand for further miniaturization of the package size has increased. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring board in a mounting region, not in a peripheral portion of a semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, and after electrically connecting the chip to a gold lead wire, epoxy resin or the like is potted and sealed (NIKKEI MATERI).
ALS & TECHNOLOGY 94.4, No.
140, pp. 18-19), and a method in which metal bumps are formed on the temporary substrate at positions corresponding to connection portions between the semiconductor chip and the external wiring board, and the semiconductor chip is face-down bonded and then transfer molded on the temporary substrate ( Sm
allest Flip-Chip-Like Pac
kage CSP; The Second VLSI
Packaging Works of Jap
an, p. 46-50, 1994).
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来提
案されている半導体パッケージの多くは、小型で高集積
度化に対応でき、かつはんだリフロ−時にパッケージク
ラック、剥離、ふくれ発生などの不良を防止し信頼性に
優れ、しかも生産性に優れるものではない。本発明は、
パッケージクラックなどの不良を防止し信頼性に優れる
小型の半導体パッケ−ジの製造方法を提供するものであ
る。However, many of the semiconductor packages proposed in the prior art are small in size and can be adapted to high integration, and prevent defects such as package cracking, peeling and blistering during solder reflow. It is excellent in reliability and not excellent in productivity. The present invention
An object of the present invention is to provide a method of manufacturing a small semiconductor package which prevents defects such as package cracks and has excellent reliability.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体パッケ−
ジの製造方法は Ａ．絶縁性支持基板の一表面には複数組の配線が形成さ
れており、前記配線は少なくとも半導体チップ電極と接
続するインナ−接続部及び半導体チップ搭載領域部を有
すものであり、前記絶縁性支持基板の前記半導体チップ
搭載領域内であって前記配線のない箇所に、少なくとも
１個の貫通穴が設けられた半導体パッケ−ジ用チップ支
持基板を準備し、 Ｂ．前記半導体チップ搭載箇所に、裏面に絶縁性のフィ
ルム状接着剤が形成された半導体チップを搭載し、 Ｃ．半導体チップ搭載後、チップの電極部と前記絶縁性
支持基板のインナ−接続部を電気的に接続し、さらにチ
ップ搭載面を封止材を用いて封止するする工程を備える
ことを特徴とするものである。SUMMARY OF THE INVENTION A semiconductor package according to the present invention is provided.
The method of manufacturing the dice is as follows. Plural sets of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to a semiconductor chip electrode and a semiconductor chip mounting area, and the insulating support B. preparing a semiconductor package chip supporting substrate provided with at least one through hole in the semiconductor chip mounting area of the substrate and at a location where the wiring is not provided; B. mounting a semiconductor chip having an insulating film adhesive on the back surface at the semiconductor chip mounting location; After mounting the semiconductor chip, the method further comprises a step of electrically connecting an electrode portion of the chip and an inner connection portion of the insulating support substrate, and further sealing the chip mounting surface with a sealing material. Things.
【０００６】[0006]
【発明の実施の形態】本発明の半導体パッケ−ジの製造
方法は、具体的には ａ．絶縁性支持基板の一表面には複数組の配線が形成さ
れており、前記配線は少なくとも半導体チップ電極と接
続するインナ−接続部及び半導体チップ搭載領域部を有
すものであり、 ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前
記配線が形成されている箇所であって前記インナ−接続
部と導通するアウタ−接続部が設けらる箇所に、開口が
設けられており、 ｃ．前記絶縁性支持基板の前記半導体チップ搭載領域内
であって前記配線のない箇所に、少なくとも１個の貫通
穴が設けられた半導体パッケ−ジ用チップ支持基板を用
い、 ｄ．前記半導体チップ搭載箇所に、裏面に絶縁性のフィ
ルム状接着剤が形成された半導体チップを搭載し、 ｅ．半導体チップ搭載後、チップの電極部と前記絶縁性
支持基板のインナ−接続部をワイヤボンドにより接続
し、さらにチップ搭載面を封止材を用いて封止し、 ｆ．前記インナ−接続部と導通するアウタ−接続部に接
続用はんだボ−ルを形成する工程を備えることができ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor package according to the present invention includes the steps of a. A plurality of sets of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection portion connected to a semiconductor chip electrode and a semiconductor chip mounting region, b. In the insulating support substrate, an opening is provided at a position where the wiring of the insulating support substrate is formed and at a position where an outer connection portion that is electrically connected to the inner connection portion is provided. , C. Using a semiconductor package chip support substrate provided with at least one through hole in the semiconductor chip mounting area of the insulative support substrate in a location where the wiring is not provided; d. Mounting a semiconductor chip having an insulating film adhesive on the back surface at the semiconductor chip mounting location; e. After mounting the semiconductor chip, the electrode portion of the chip and the inner connection portion of the insulating support substrate are connected by wire bonding, and the chip mounting surface is sealed with a sealing material, f. The method may further include a step of forming a connection solder ball at an outer connection portion which is electrically connected to the inner connection portion.
【０００７】絶縁性支持基板としては、ポリイミド、エ
ポキシ樹脂、ポリイミド等のプラスチックフィルム、ポ
リイミド、エポキシ樹脂、ポリイミド等のプラスチック
をガラス不織布等基材に含浸・硬化したもの等が使用で
きる。絶縁性支持基板の一表面に複数組の配線を形成す
には、銅箔をエッチングする方法、所定の箇所に銅めっ
きをする方法、それらを併用する方法等が使用できる。
絶縁性支持基板に外部接続部、貫通穴などの開口を設け
るには、ドリル加工やパンチングなどの機械加工、エキ
シマレーザや炭酸ガスレーザなどのレーザ加工等により
行うことができる。また、接着性のある絶縁基材等に開
口部をあらかじめ設け、それを銅箔等の配線形成用金属
箔と張り合わせる方法、銅箔付きまたはあらかじめ配線
が形成された絶縁基材に開口部を設ける方法、それらを
併用する等が可能である。インナ−接続部と導通するア
ウタ−接続部は、絶縁性支持基板開口部にはんだボー
ル、めっき等によりバンプ等を形成することにより作成
することができる。これは外部の基板等に接続される。
フィルム状接着材搭載領域は、できるだけ均一に配線パ
ターンが配置されていることが好ましい。具体的には、
絶縁性フィルム状接着材が形成される領域の絶縁性支持
基板には、任意の点からその任意の点を含む半径１ミリ
メートルの範囲に少なくとも１つ以上の配線が形成され
ているように配線が配置されていることが好ましい。し
かし、配線だけでこのような条件が満足できな場合は、
別に独立のダミーパターン、位置合わせ用マーク、文字
・符号等などの金属パターンを設けても良い。[0007] As the insulating support substrate, a plastic film such as polyimide, epoxy resin or polyimide, or a substrate such as glass nonwoven fabric impregnated with a plastic such as polyimide, epoxy resin or polyimide and cured can be used. In order to form a plurality of sets of wiring on one surface of the insulating support substrate, a method of etching a copper foil, a method of plating a predetermined portion with copper, a method of using them in combination, or the like can be used.
An opening such as an external connection portion or a through hole can be provided in the insulating support substrate by mechanical processing such as drilling or punching, or laser processing such as excimer laser or carbon dioxide gas laser. Also, a method is provided in which an opening is provided in advance on an insulating base material having adhesiveness, and the opening is bonded to a metal foil for forming a wiring such as a copper foil. It is possible to provide them, use them together, or the like. The outer connection portion that is electrically connected to the inner connection portion can be formed by forming a bump or the like on the opening of the insulating support substrate by solder ball, plating, or the like. This is connected to an external substrate or the like.
It is preferable that the wiring pattern is arranged as uniformly as possible in the film-like adhesive mounting region. In particular,
The wiring is formed on the insulating support substrate in the region where the insulating film-like adhesive is formed, such that at least one wiring is formed in a range of 1 mm in radius including an arbitrary point from the arbitrary point. Preferably, they are arranged. However, if these conditions cannot be satisfied only with wiring,
Separately, an independent dummy pattern, a positioning mark, a metal pattern such as a character or a code may be provided.
【０００８】絶縁性フィルムには、ポリイミド、エポキ
シ樹脂、ポリイミド等のプラスチックフィルムに接着材
を片面もしくは両面に塗布したもの、または絶縁性のフ
ィルム状接着材が使用できる。絶縁性のフィルム状接着
材としては、例えば化１As the insulating film, a film obtained by applying an adhesive to one or both surfaces of a plastic film such as polyimide, epoxy resin, or polyimide, or an insulating film adhesive can be used. As an insulating film adhesive, for example,
【化１】 （ただし、ｎ＝２〜２０の整数を示す。）で表されるテ
トラカルボン酸二無水物（１）の含量が全テトラカルボ
ン酸二無水物の７０モル％以上であるテトラカルボン酸
二無水物と、ジアミンを反応させて得られるポリイミド
樹脂、更にエポキシ樹脂等の熱硬化性樹脂からなるフィ
ルム状接着材がある。更にこれにシリカ、アルミナ、等
の無機物質フィラーを含有させることもできる。絶縁性
のフィルム状接着材を使用する場合の厚みについては、
半導体チップと配線間の絶縁性を確保できる限り、薄く
したほうが絶縁性支持基板の貫通穴周辺部に接着しにく
くなる。具体的には、０．００５ｍｍ以上かつ０．０３
０ｍｍ以下が好ましく、さらには０．０１０ｍｍ以上か
つ０．０２０ｍｍ以下の範囲がより好ましい。また、絶
縁性フィルムに接着材を塗布したものを使用する場合
は、同様に接着材層の厚みは薄いほうが好ましい。裏面
に絶縁性のフィルム状接着剤が形成された半導体チップ
は、フィルムを融点以上の温度でウェハ−裏面に接着し
た後、ダイシングして作成できる。そのほかワニス状接
着材をウェハ−裏面にスピンコ−トし、乾燥してからダ
イシングする方法もある。貫通穴は、絶縁性フィルム搭
載領域に少なくとも１個以上形成される。穴径は特に問
わないが、例えば、０．０５ｍｍ以上かつ１．０００ｍ
ｍ以下が好ましい。配置も特に問わないが、なるべく均
等に複数個配置されていることが好ましく、これらの穴
径および配置は、配線パターンに応じて選択される。Embedded image (Wherein, n is an integer of 2 to 20) Tetracarboxylic dianhydride having a content of tetracarboxylic dianhydride (1) of 70 mol% or more of all tetracarboxylic dianhydrides And a film adhesive made of a thermosetting resin such as a polyimide resin obtained by reacting a diamine with an epoxy resin. Further, it may contain an inorganic filler such as silica, alumina, or the like. Regarding the thickness when using an insulating film adhesive,
As long as the insulation between the semiconductor chip and the wiring can be ensured, the thinner the film, the harder it is to adhere to the periphery of the through hole of the insulating support substrate. Specifically, 0.005 mm or more and 0.03
0 mm or less is preferable, and the range of 0.010 mm or more and 0.020 mm or less is more preferable. When using an insulating film coated with an adhesive, the thickness of the adhesive layer is preferably smaller. A semiconductor chip having an insulating film adhesive formed on the back surface can be prepared by bonding the film to the wafer back surface at a temperature equal to or higher than the melting point and then dicing. In addition, there is a method in which a varnish-like adhesive is spin-coated on the back surface of the wafer, dried, and then diced. At least one through-hole is formed in the insulating film mounting area. Although the hole diameter is not particularly limited, for example, 0.05 mm or more and 1.000 m
m or less is preferable. The arrangement is not particularly limited, but it is preferable to arrange a plurality of holes as evenly as possible, and the diameter and arrangement of these holes are selected according to the wiring pattern.
【０００９】本発明では、絶縁性支持基板の半導体チッ
プ搭載箇所に、裏面に絶縁性のフィルム状接着剤が形成
された半導体チップを搭載し、チップの電極部と前記絶
縁性支持基板のインナ−接続部をワイヤボンドにより接
続し、さらにチップ搭載面を封止材を用いてトランスフ
ァモ−ルド封止し、その後、前記インナ−接続部と導通
するアウタ−接続部の開口穴に接続用はんだボ−ルを形
成することにより半導体パッケ−ジを製造する。According to the present invention, a semiconductor chip having an insulating film-like adhesive formed on the back surface is mounted on a semiconductor chip mounting portion of the insulating support substrate, and an electrode portion of the chip and an inner surface of the insulating support substrate are mounted. The connection portion is connected by wire bonding, and the chip mounting surface is transfer-molded and sealed using a sealing material. Thereafter, a connection soldering hole is connected to the opening hole of the outer connection portion which is electrically connected to the inner connection portion. Forming a semiconductor package by forming a metal package.
【００１０】[0010]
【実施例】図１により、本発明の一実施例について説明
する。ポリイミド接着材をポリイミドフィルムの両面に
塗布した、厚さ０．０７ｍｍのポリイミドボンディング
シート１に、アウター接続部となる開口３及び貫通穴
（ベントホール）９をドリル加工で形成する。次に厚さ
０．０１８ｍｍの銅箔（日本電解製、商品名：ＳＬＰー
１８）を接着後、インナー接続部及び展開配線２を通常
のエッチング法で形成する。さらに、露出している配線
に無電解ニッケルめっき（膜厚：５μｍ）、無電解金め
っき（膜厚：０．８μｍ）を順次施す（不図示）。ここ
では、無電解めっきを使用したが、電解めっきを用いて
もよい。次に打ち抜き金型を用いてフレーム状に打ち抜
き、複数組のインナー接続部、展開配線、アウター接続
部を形成した支持基板を準備する（図１ａ）。支持基板
の作製方法として市販の２層（銅／ポリイミド）フレキ
シブル基板のポリイミドを、レーザ加工によりアウター
接続部穴等を形成する方法でもよい。次にウェハ−６の
裏面に、ダイボンドフィルム４（日立化成工業株式会社
製、商品名：ＤＦ−３３５、厚み０．０１５ｍｍ）を接
着する。接着の条件は、例えば温度１８０℃、時間５
秒、圧力１ｋｇｆ／ｃｍ2である。この後所定の寸法に
ダイシングしてダイボンド材付チップを作製する（図１
ｂ）。次に絶縁性支持基板の半導体チップ搭載領域に、
ダイボンド材付チップ６を接着する。接着条件は、例え
ば温度１８０℃、時間５秒、圧力１ｋｇｆ／ｃｍ2であ
る。この後１８０℃、１時間加熱し、ダイボンド材中の
熱硬化性樹脂分を硬化させるとともに揮発分を除去す
る。さらに、半導体チップ電極とインナー接続部を、金
ワイヤ５をボンディングして電気的に接続する（図１
ｃ）。このようにして形成したものをトランスファモー
ルド金型に装填し、半導体封止用エポキシ樹脂７（日立
化成工業（株）製、商品名：ＣＬ−７７００）を用いて
各々封止する（図１ｄ）。その後、アウター接続部とな
る開口部にはんだボール８を配置し溶融させ（図１
ｅ）、パンチにより個々のパッケージに分離し半導体パ
ッケージが得られる（図１ｆ）。FIG. 1 shows an embodiment of the present invention. An opening 3 serving as an outer connection portion and a through hole (vent hole) 9 are formed by drilling in a 0.07 mm thick polyimide bonding sheet 1 in which a polyimide adhesive is applied to both surfaces of a polyimide film. Next, after bonding a copper foil (product name: SLP-18, manufactured by Nihon Denshi) having a thickness of 0.018 mm, the inner connection portion and the development wiring 2 are formed by a normal etching method. Further, electroless nickel plating (film thickness: 5 μm) and electroless gold plating (film thickness: 0.8 μm) are sequentially applied to the exposed wiring (not shown). Here, electroless plating is used, but electrolytic plating may be used. Next, a support substrate having a plurality of sets of inner connection portions, developed wiring, and outer connection portions is prepared by punching out a frame using a punching die (FIG. 1A). As a method for manufacturing the supporting substrate, a method may be used in which polyimide of a commercially available two-layer (copper / polyimide) flexible substrate is formed by laser processing to form outer connection hole portions and the like. Next, a die bond film 4 (trade name: DF-335, thickness: 0.015 mm, manufactured by Hitachi Chemical Co., Ltd.) is bonded to the back surface of the wafer 6. Bonding conditions are, for example, a temperature of 180 ° C. and a time of 5 hours.
Second, the pressure is 1 kgf / cm 2 . Thereafter, dicing is performed to a predetermined size to produce a chip with a die bonding material (FIG. 1).
b). Next, in the semiconductor chip mounting area of the insulating support substrate,
The chip 6 with the die bonding material is bonded. The bonding conditions are, for example, a temperature of 180 ° C., a time of 5 seconds, and a pressure of 1 kgf / cm 2 . Thereafter, heating is performed at 180 ° C. for 1 hour to cure the thermosetting resin component in the die bonding material and remove volatile components. Further, the semiconductor chip electrode and the inner connection portion are electrically connected by bonding a gold wire 5 (FIG. 1).
c). The thus formed product is loaded into a transfer mold and sealed using a semiconductor sealing epoxy resin 7 (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 1d). . Thereafter, the solder balls 8 are arranged in the openings to be the outer connection portions and are melted (FIG. 1).
e) Separation into individual packages by punching to obtain a semiconductor package (FIG. 1f).
【００１１】[0011]
【発明の効果】本発明は、リフロ−時に発生する水蒸気
による内部圧を貫通穴を利用して緩和し、パッケージク
ラックなどの不良を防止する信頼性の高い小型半導体パ
ッケージの製造方法を提供するものである。一般的に
は、ダイドンド材としてはペ−ストが使用されペ−スト
を支持基板に塗ってからチップ付けを行う。しかしこの
方法では貫通穴を埋めてしまうため、パッケージクラッ
クが多発する。ダイボンド材としてフィルム状を使用
し、予め支持基板に貼付しておき、そのあとチップ付け
する方法も考えられるが、この方法は貼付条件やフィル
ム材質などを最適化した場合、貫通穴を塞がないため有
効ではある。しかし条件や材質によっては、予め支持基
板に貼付する時に下に垂れ下がり貫通穴を塞いでしまう
ことがある。本発明は、半導体チップ裏面に予めフィル
ム状ダイボンド材を接着しておき、この後支持基板へチ
ップ付けする製造法であるためにダイボンド材が下へ垂
れ下がり、貫通穴を塞いでしまう現象が全く発生しな
い。したがって、確実に水蒸気を逃がすことができるた
めに、リフロ−時にパッケージクラック、剥離、膨れな
どの不良が発生しない、信頼性の高い小型半導体パッケ
−ジの製造が可能となる。According to the present invention, there is provided a method of manufacturing a highly reliable small semiconductor package which reduces internal pressure due to water vapor generated at the time of reflow by using a through hole and prevents defects such as package cracks. It is. Generally, a paste is used as the die-doped material, and the paste is applied after the paste is applied to the supporting substrate. However, in this method, the through holes are filled, so that many package cracks occur. It is also possible to use a film as the die bond material, stick it to the support substrate in advance, and then attach the chip.However, this method does not block the through hole when the sticking conditions and film material are optimized. Therefore it is effective. However, depending on conditions and materials, there is a case where the adhesive layer hangs down and closes the through-hole when it is pasted on the support substrate in advance. The present invention is a manufacturing method in which a film-shaped die bonding material is bonded to the backside of a semiconductor chip in advance, and then the chip is attached to a supporting substrate. do not do. Therefore, since the water vapor can be reliably released, it is possible to manufacture a highly reliable small semiconductor package which does not cause defects such as package crack, peeling, and swelling during reflow.
【図１】本発明の一実施例を説明するための、半導体パ
ッケージ製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor package manufacturing process for explaining one embodiment of the present invention.
１ ポリイミドボンディングシート ２ インナ−接続部及び展開配線 ３ アウタ−接続部 ４ ダイボンドフィルム ５ 金ワイヤ ６ 半導体チップ ７ 半導体封止用エポキシ樹脂 ８ はんだボール ９ 貫通穴 １０ 外部基板 DESCRIPTION OF SYMBOLS 1 Polyimide bonding sheet 2 Inner connection part and development wiring 3 Outer connection part 4 Die bond film 5 Gold wire 6 Semiconductor chip 7 Epoxy resin for semiconductor sealing 8 Solder ball 9 Through hole 10 External board
フロントページの続き (72)発明者 湯佐 正己 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内Continued on the front page (72) Inventor Masami Yusa 48 Tsudai, Tsukuba-shi, Ibaraki Prefecture Tsukuba Development Laboratory, Hitachi Chemical Co., Ltd.
Claims (1)
配線が形成されており、前記配線は少なくとも半導体チ
ップ電極と接続するインナ−接続部及び半導体チップ搭
載領域部を有すものであり、前記絶縁性支持基板の前記
半導体チップ搭載領域内であって前記配線のない箇所
に、少なくとも１個の貫通穴が設けられた半導体パッケ
−ジ用チップ支持基板を準備し、 Ｂ．前記半導体チップ搭載箇所に、裏面に絶縁性のフィ
ルム状接着剤が形成された半導体チップを搭載し、 Ｃ．半導体チップ搭載後、チップの電極部と前記絶縁性
支持基板のインナ−接続部を電気的に接続し、さらにチ
ップ搭載面を封止材を用いて封止する工程を備える半導
体パッケ−ジの製造方法。1. A. Plural sets of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to a semiconductor chip electrode and a semiconductor chip mounting area, and the insulating support B. preparing a semiconductor package chip supporting substrate provided with at least one through hole in the semiconductor chip mounting area of the substrate and at a location where the wiring is not provided; B. mounting a semiconductor chip having an insulating film adhesive on the back surface at the semiconductor chip mounting location; Manufacturing a semiconductor package including a step of electrically connecting an electrode portion of the chip and an inner connection portion of the insulating support substrate after mounting the semiconductor chip, and further sealing the chip mounting surface with a sealing material. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1955697A JP3314142B2 (en) | 1997-02-03 | 1997-02-03 | Semiconductor package manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1955697A JP3314142B2 (en) | 1997-02-03 | 1997-02-03 | Semiconductor package manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002040745A Division JP2002270727A (en) | 2002-02-18 | 2002-02-18 | Method of manufacturing semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10223795A true JPH10223795A (en) | 1998-08-21 |
| JP3314142B2 JP3314142B2 (en) | 2002-08-12 |
Family
ID=12002600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1955697A Expired - Fee Related JP3314142B2 (en) | 1997-02-03 | 1997-02-03 | Semiconductor package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3314142B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010272734A (en) * | 2009-05-22 | 2010-12-02 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
| WO2011058998A1 (en) * | 2009-11-13 | 2011-05-19 | 日立化成工業株式会社 | Liquid adhesive composition for semiconductor, semiconductor device, and method for manufacturing semiconductor device |
| CN109737237A (en) * | 2019-01-29 | 2019-05-10 | 重庆大学 | Photo-thermal manipulates membrane type microvalve device and application method |
-
1997
- 1997-02-03 JP JP1955697A patent/JP3314142B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010272734A (en) * | 2009-05-22 | 2010-12-02 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
| US9112061B2 (en) | 2009-05-22 | 2015-08-18 | Ps4 Luxco S.A.R.L. | Semiconductor device and method of forming the same |
| WO2011058998A1 (en) * | 2009-11-13 | 2011-05-19 | 日立化成工業株式会社 | Liquid adhesive composition for semiconductor, semiconductor device, and method for manufacturing semiconductor device |
| CN109737237A (en) * | 2019-01-29 | 2019-05-10 | 重庆大学 | Photo-thermal manipulates membrane type microvalve device and application method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3314142B2 (en) | 2002-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6064111A (en) | Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package | |
| JPH10178145A (en) | Semiconductor device and its manufacturing method and insulation substrate for semiconductor device | |
| JP2003007918A (en) | Method of manufacturing circuit device | |
| JP2003007916A (en) | Method of manufacturing circuit device | |
| JP2003007917A (en) | Method manufacturing circuit device | |
| JPH08264581A (en) | Package and its manufacture | |
| KR100365050B1 (en) | Chip supporting substrate for semiconductor package, semiconductor device, and method for manufacturing them | |
| JP2002198458A (en) | Semiconductor device and its manufacturing method | |
| JP3915226B2 (en) | Chip support substrate for semiconductor package and semiconductor package | |
| JP3616742B2 (en) | Chip support substrate for semiconductor package | |
| JPH10223795A (en) | Manufacture of semiconductor package | |
| JP3247638B2 (en) | Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device | |
| JP3143081B2 (en) | Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device | |
| JP3448010B2 (en) | Chip support substrate for semiconductor package | |
| JP3661822B2 (en) | Chip support substrate for semiconductor packaging | |
| JP3293753B2 (en) | Semiconductor package chip support substrate and semiconductor package using the same | |
| JP3599142B2 (en) | Manufacturing method of semiconductor package | |
| JP2002270727A (en) | Method of manufacturing semiconductor package | |
| JP4452964B2 (en) | Semiconductor mounting substrate manufacturing method and semiconductor package manufacturing method | |
| JP3402416B2 (en) | Manufacturing method of semiconductor package | |
| JP3826458B2 (en) | Method of bonding die bonding material | |
| JP3560142B2 (en) | Method of manufacturing chip support substrate for semiconductor package, semiconductor package using chip support substrate for semiconductor package, and method of manufacturing the same | |
| JP3393026B2 (en) | Chip support substrate for semiconductor package | |
| JP3445895B2 (en) | Chip support substrate for semiconductor package | |
| JP2005101312A (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 7 Free format text: PAYMENT UNTIL: 20090531 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20100531 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20100531 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110531 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110531 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20120531 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130531 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |